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Searched refs:nvkm_pll_vals (Results 1 – 10 of 10) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
Dnv04.h6 struct nvkm_pll_vals;
20 void setPLL_single(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
21 void setPLL_double_highregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
22 void setPLL_double_lowregs(struct nvkm_devinit *, u32, struct nvkm_pll_vals *);
Dnv04.c144 struct nvkm_pll_vals *pv) in setPLL_single()
199 struct nvkm_pll_vals *pv) in setPLL_double_highregs()
277 struct nvkm_pll_vals *pv) in setPLL_double_lowregs()
360 struct nvkm_pll_vals pv; in nv04_devinit_pll_set()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
Dclk.h7 struct nvkm_pll_vals;
116 struct nvkm_pll_vals *pv);
117 int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv);
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dpriv.h25 struct nvkm_pll_vals *);
26 int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
Dnv04.c33 int clk, struct nvkm_pll_vals *pv) in nv04_clk_pll_calc()
49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
Dpll.h5 struct nvkm_pll_vals { struct
/drivers/gpu/drm/nouveau/dispnv04/
Dhw.c133 uint32_t pll2, struct nvkm_pll_vals *pllvals) in nouveau_hw_decode_pll()
165 struct nvkm_pll_vals *pllvals) in nouveau_hw_get_pllvals()
205 nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pv) in nouveau_hw_pllvals_to_clk()
218 struct nvkm_pll_vals pllvals; in nouveau_hw_get_clock()
265 struct nvkm_pll_vals pv; in nouveau_hw_fix_bad_vpll()
Dhw.h44 struct nvkm_pll_vals *pllvals);
45 int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
Ddisp.h42 struct nvkm_pll_vals pllvals;
Dcrtc.c126 struct nvkm_pll_vals *pv = &regp->pllvals; in nv_crtc_calc_state_ext()