Home
last modified time | relevance | path

Searched refs:nvkm_rd32 (Results 1 – 25 of 202) sorted by relevance

123456789

/drivers/gpu/drm/nouveau/nvkm/engine/gr/
Dnv50.c35 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv50_gr_units()
244 u32 e0c = nvkm_rd32(device, ustatus_addr + 0x04); in nv50_gr_prop_trap()
245 u32 e10 = nvkm_rd32(device, ustatus_addr + 0x08); in nv50_gr_prop_trap()
246 u32 e14 = nvkm_rd32(device, ustatus_addr + 0x0c); in nv50_gr_prop_trap()
247 u32 e18 = nvkm_rd32(device, ustatus_addr + 0x10); in nv50_gr_prop_trap()
248 u32 e1c = nvkm_rd32(device, ustatus_addr + 0x14); in nv50_gr_prop_trap()
249 u32 e20 = nvkm_rd32(device, ustatus_addr + 0x18); in nv50_gr_prop_trap()
250 u32 e24 = nvkm_rd32(device, ustatus_addr + 0x1c); in nv50_gr_prop_trap()
286 u32 units = nvkm_rd32(device, 0x1540); in nv50_gr_mp_trap()
298 mp10 = nvkm_rd32(device, addr + 0x10); in nv50_gr_mp_trap()
[all …]
Dnv40.c36 return nvkm_rd32(gr->engine.subdev.device, 0x1540); in nv40_gr_units()
103 if (nvkm_rd32(device, 0x40032c) == inst) { in nv40_gr_chan_fini()
110 if (!(nvkm_rd32(device, 0x400300) & 0x00000001)) in nv40_gr_chan_fini()
113 u32 insn = nvkm_rd32(device, 0x400308); in nv40_gr_chan_fini()
122 if (nvkm_rd32(device, 0x400330) == inst) in nv40_gr_chan_fini()
238 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); in nv40_gr_intr()
239 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); in nv40_gr_intr()
240 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); in nv40_gr_intr()
241 u32 inst = nvkm_rd32(device, 0x40032c) & 0x000fffff; in nv40_gr_intr()
242 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); in nv40_gr_intr()
[all …]
Dgf100.c721 return nvkm_rd32(gr->engine.subdev.device, 0x409b00); in gf100_gr_ctxsw_inst()
734 u32 stat = nvkm_rd32(device, 0x409804); in gf100_gr_fecs_ctrl_ctxsw()
783 u32 stat = nvkm_rd32(device, 0x409800); in gf100_gr_fecs_bind_pointer()
803 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_virtual_address()
820 if (nvkm_rd32(device, 0x409800) == 0x00000001) in gf100_gr_fecs_set_reglist_bind_instance()
836 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_reglist_image_size()
874 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_pm_image_size()
890 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_zcull_image_size()
906 if ((*psize = nvkm_rd32(device, 0x409800))) in gf100_gr_fecs_discover_image_size()
928 u32 trace = nvkm_rd32(gr->base.engine.subdev.device, 0x40981c); in gf100_gr_chsw_load()
[all …]
Dnv20.c39 if (nvkm_rd32(device, 0x400144) & 0x00010000) in nv20_gr_chan_fini()
40 chid = (nvkm_rd32(device, 0x400148) & 0x1f000000) >> 24; in nv20_gr_chan_fini()
45 if (!nvkm_rd32(device, 0x400700)) in nv20_gr_chan_fini()
186 u32 stat = nvkm_rd32(device, NV03_PGRAPH_INTR); in nv20_gr_intr()
187 u32 nsource = nvkm_rd32(device, NV03_PGRAPH_NSOURCE); in nv20_gr_intr()
188 u32 nstatus = nvkm_rd32(device, NV03_PGRAPH_NSTATUS); in nv20_gr_intr()
189 u32 addr = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_ADDR); in nv20_gr_intr()
193 u32 data = nvkm_rd32(device, NV04_PGRAPH_TRAPPED_DATA); in nv20_gr_intr()
194 u32 class = nvkm_rd32(device, 0x400160 + subc * 4) & 0xfff; in nv20_gr_intr()
244 if (!nvkm_rd32(device, 0x400700)) in nv20_gr_init()
[all …]
Dg84.c134 for (tmp = nvkm_rd32(device, 0x400380); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
139 for (tmp = nvkm_rd32(device, 0x400384); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
144 for (tmp = nvkm_rd32(device, 0x400388); tmp && idle; tmp >>= 3) { in g84_gr_tlb_flush()
154 tmp = nvkm_rd32(device, 0x400700); in g84_gr_tlb_flush()
159 nvkm_rd32(device, 0x400380)); in g84_gr_tlb_flush()
161 nvkm_rd32(device, 0x400384)); in g84_gr_tlb_flush()
163 nvkm_rd32(device, 0x400388)); in g84_gr_tlb_flush()
169 if (!(nvkm_rd32(device, 0x100c80) & 0x00000001)) in g84_gr_tlb_flush()
Dnv10.c419 state[__i] = nvkm_rd32(device, NV10_PGRAPH_PIPE_DATA); \
454 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); in nv17_gr_mthd_lma_window()
455 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); in nv17_gr_mthd_lma_window()
551 if (nvkm_rd32(device, 0x400144) & 0x00010000) { in nv10_gr_channel()
552 int chid = nvkm_rd32(device, 0x400148) >> 24; in nv10_gr_channel()
589 xfmode0 = nvkm_rd32(device, NV10_PGRAPH_XFMODE0); in nv10_gr_load_pipe()
590 xfmode1 = nvkm_rd32(device, NV10_PGRAPH_XFMODE1); in nv10_gr_load_pipe()
827 int class = nvkm_rd32(device, NV10_PGRAPH_CTX_CACHE(i, 0)) & 0xfff; in nv10_gr_load_dma_vtxbuf()
839 ctx_user = nvkm_rd32(device, NV10_PGRAPH_CTX_USER); in nv10_gr_load_dma_vtxbuf()
841 ctx_switch[i] = nvkm_rd32(device, NV10_PGRAPH_CTX_SWITCH(i)); in nv10_gr_load_dma_vtxbuf()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/
Dgt215.c39 addr = nvkm_rd32(device, 0x10a4a0); in gt215_pmu_send()
41 u32 tmp = nvkm_rd32(device, 0x10a4b0); in gt215_pmu_send()
61 } while (nvkm_rd32(device, 0x10a580) != 0x00000001); in gt215_pmu_send()
94 u32 addr = nvkm_rd32(device, 0x10a4cc); in gt215_pmu_recv()
95 if (addr == nvkm_rd32(device, 0x10a4c8)) in gt215_pmu_recv()
101 } while (nvkm_rd32(device, 0x10a580) != 0x00000002); in gt215_pmu_recv()
106 process = nvkm_rd32(device, 0x10a1c4); in gt215_pmu_recv()
107 message = nvkm_rd32(device, 0x10a1c4); in gt215_pmu_recv()
108 data0 = nvkm_rd32(device, 0x10a1c4); in gt215_pmu_recv()
109 data1 = nvkm_rd32(device, 0x10a1c4); in gt215_pmu_recv()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/privring/
Dgf100.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0400)); in gf100_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0400)); in gf100_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0400)); in gf100_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0400)); in gf100_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0400)); in gf100_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0400)); in gf100_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0400)); in gf100_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0400)); in gf100_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0400)); in gf100_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x121c58); in gf100_privring_intr()
[all …]
Dgk104.c31 u32 addr = nvkm_rd32(device, 0x122120 + (i * 0x0800)); in gk104_privring_intr_hub()
32 u32 data = nvkm_rd32(device, 0x122124 + (i * 0x0800)); in gk104_privring_intr_hub()
33 u32 stat = nvkm_rd32(device, 0x122128 + (i * 0x0800)); in gk104_privring_intr_hub()
41 u32 addr = nvkm_rd32(device, 0x124120 + (i * 0x0800)); in gk104_privring_intr_rop()
42 u32 data = nvkm_rd32(device, 0x124124 + (i * 0x0800)); in gk104_privring_intr_rop()
43 u32 stat = nvkm_rd32(device, 0x124128 + (i * 0x0800)); in gk104_privring_intr_rop()
51 u32 addr = nvkm_rd32(device, 0x128120 + (i * 0x0800)); in gk104_privring_intr_gpc()
52 u32 data = nvkm_rd32(device, 0x128124 + (i * 0x0800)); in gk104_privring_intr_gpc()
53 u32 stat = nvkm_rd32(device, 0x128128 + (i * 0x0800)); in gk104_privring_intr_gpc()
61 u32 intr0 = nvkm_rd32(device, 0x120058); in gk104_privring_intr()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
Dnv04.c71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); in nv04_fifo_pause()
76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
146 u32 engine = nvkm_rd32(device, 0x003280); in nv04_fifo_swmthd()
154 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; in nv04_fifo_swmthd()
175 u32 pull0 = nvkm_rd32(device, 0x003250); in nv04_fifo_cache_error()
187 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
188 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
190 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
191 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
208 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); in nv04_fifo_cache_error()
[all …]
Dgf100.c86 !(nvkm_rd32(device, 0x00227c) & 0x00100000), in gf100_fifo_runlist_commit()
327 u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); in gf100_fifo_intr_sched_ctxsw()
355 u32 intr = nvkm_rd32(device, 0x00254c); in gf100_fifo_intr_sched()
376 u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); in gf100_fifo_intr_fault()
377 u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); in gf100_fifo_intr_fault()
378 u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); in gf100_fifo_intr_fault()
379 u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); in gf100_fifo_intr_fault()
409 u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
410 u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
411 u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); in gf100_fifo_intr_pbdma()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dgf119.c113 if (!(nvkm_rd32(device, 0x616618 + hoff) & 0x80000000)) in gf119_sor_dp_audio()
136 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
137 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
138 data[2] = nvkm_rd32(device, 0x61c130 + loff); in gf119_sor_dp_drive()
146 data[3] = nvkm_rd32(device, 0x61c13c + loff) & ~(0x000000ff << shift); in gf119_sor_dp_drive()
285 u32 ctrl = nvkm_rd32(device, 0x640200 + coff); in gf119_sor_state()
325 *pmask = (nvkm_rd32(device, 0x612004) & 0x0000ff00) >> 8; in gf119_sor_cnt()
342 u32 ctrl = nvkm_rd32(device, 0x640180 + coff); in gf119_dac_state()
373 *pmask = (nvkm_rd32(device, 0x612004) & 0x000000f0) >> 4; in gf119_dac_cnt()
407 data = nvkm_rd32(device, 0x640414 + hoff); in gf119_head_state()
[all …]
Dgv100.c82 if (!(nvkm_rd32(device, 0x616560 + hoff) & 0x80000000)) in gv100_sor_dp_audio()
166 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); in gv100_sor_state()
207 if (!((hda = nvkm_rd32(device, 0x08a15c)) & 0x40000000)) in gv100_sor_new()
208 hda = nvkm_rd32(device, 0x118fb0) >> 8; in gv100_sor_new()
218 *pmask = (nvkm_rd32(device, 0x610060) & 0x0000ff00) >> 8; in gv100_sor_cnt()
219 return (nvkm_rd32(device, 0x610074) & 0x00000f00) >> 8; in gv100_sor_cnt()
242 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; in gv100_head_rgpos()
243 *hline = nvkm_rd32(device, 0x616334 + hoff) & 0x0000ffff; in gv100_head_rgpos()
253 data = nvkm_rd32(device, 0x682064 + hoff); in gv100_head_state()
256 data = nvkm_rd32(device, 0x682068 + hoff); in gv100_head_state()
[all …]
Dnv50.c72 if (!(nvkm_rd32(device, 0x61e004 + poff) & 0x80000000)) in nv50_pior_power_wait()
121 u32 ctrl = nvkm_rd32(device, 0x610b80 + coff); in nv50_pior_state()
155 *pmask = (nvkm_rd32(device, 0x610184) & 0x70000000) >> 28; in nv50_pior_cnt()
173 if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000)) in nv50_sor_power_wait()
192 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) in nv50_sor_power()
202 u32 ctrl = nvkm_rd32(device, 0x610b70 + coff); in nv50_sor_state()
236 *pmask = (nvkm_rd32(device, 0x610184) & 0x03000000) >> 24; in nv50_sor_cnt()
273 if (!(nvkm_rd32(device, 0x61a004 + doff) & 0x80000000)) in nv50_dac_power_wait()
300 u32 ctrl = nvkm_rd32(device, 0x610b58 + coff); in nv50_dac_state()
332 *pmask = (nvkm_rd32(device, 0x610184) & 0x00700000) >> 20; in nv50_dac_cnt()
[all …]
Dnv04.c47 u32 data = nvkm_rd32(device, 0x600868 + (head->id * 0x2000)); in nv04_head_rgpos()
57 state->vblanks = nvkm_rd32(device, 0x680800 + hoff) & 0x0000ffff; in nv04_head_state()
58 state->vtotal = nvkm_rd32(device, 0x680804 + hoff) & 0x0000ffff; in nv04_head_state()
60 state->hblanks = nvkm_rd32(device, 0x680820 + hoff) & 0x0000ffff; in nv04_head_state()
61 state->htotal = nvkm_rd32(device, 0x680824 + hoff) & 0x0000ffff; in nv04_head_state()
84 u32 crtc0 = nvkm_rd32(device, 0x600100); in nv04_disp_intr()
85 u32 crtc1 = nvkm_rd32(device, 0x602100); in nv04_disp_intr()
99 pvideo = nvkm_rd32(device, 0x8100); in nv04_disp_intr()
Dg94.c71 data[0] = nvkm_rd32(device, 0x61c118 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
72 data[1] = nvkm_rd32(device, 0x61c120 + loff) & ~(0x000000ff << shift); in g94_sor_dp_drive()
73 data[2] = nvkm_rd32(device, 0x61c130 + loff); in g94_sor_dp_drive()
115 if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000)) in g94_sor_dp_power()
159 switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) { in g94_sor_war_needed()
183 clksor = nvkm_rd32(device, 0x614300 + nv50_ior_base(ior)); in g94_sor_war_update_sppll1()
210 sorpwr = nvkm_rd32(device, 0x61c004 + soff); in g94_sor_war_3()
212 u32 seqctl = nvkm_rd32(device, 0x61c030 + soff); in g94_sor_war_3()
219 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) in g94_sor_war_3()
224 if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000)) in g94_sor_war_3()
[all …]
/drivers/gpu/drm/nouveau/nvkm/engine/pm/
Dgf100.c152 case 0: ctr->ctr = nvkm_rd32(device, dom->addr + 0x08c); break; in gf100_perfctr_read()
153 case 1: ctr->ctr = nvkm_rd32(device, dom->addr + 0x088); break; in gf100_perfctr_read()
154 case 2: ctr->ctr = nvkm_rd32(device, dom->addr + 0x080); break; in gf100_perfctr_read()
155 case 3: ctr->ctr = nvkm_rd32(device, dom->addr + 0x090); break; in gf100_perfctr_read()
157 dom->clk = nvkm_rd32(device, dom->addr + 0x070); in gf100_perfctr_read()
210 mask = (1 << nvkm_rd32(device, 0x022430)) - 1; in gf100_pm_new_()
211 mask &= ~nvkm_rd32(device, 0x022504); in gf100_pm_new_()
212 mask &= ~nvkm_rd32(device, 0x022584); in gf100_pm_new_()
220 mask = (1 << nvkm_rd32(device, 0x022438)) - 1; in gf100_pm_new_()
221 mask &= ~nvkm_rd32(device, 0x022548); in gf100_pm_new_()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
Dnv50.c41 return nvkm_rd32(device, 0x004700); in read_div()
45 return nvkm_rd32(device, 0x004800); in read_div()
57 u32 rsel = nvkm_rd32(device, 0x00e18c); in read_pll_src()
73 coef = nvkm_rd32(device, 0x00e81c + (id * 0x0c)); in read_pll_src()
82 coef = nvkm_rd32(device, 0x00e81c); in read_pll_src()
90 rsel = nvkm_rd32(device, 0x00c050); in read_pll_src()
108 coef = nvkm_rd32(device, 0x00e81c + (id * 0x28)); in read_pll_src()
109 P = (nvkm_rd32(device, 0x00e824 + (id * 0x28)) >> 16) & 7; in read_pll_src()
129 u32 src, mast = nvkm_rd32(device, 0x00c040); in read_pll_ref()
161 u32 mast = nvkm_rd32(device, 0x00c040); in read_pll()
[all …]
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
Dshadowramin.c37 *(u32 *)&bios->data[i] = nvkm_rd32(device, 0x700000 + i); in pramin_read()
71 addr = nvkm_rd32(device, 0x021c04); in pramin_init()
74 addr = nvkm_rd32(device, 0x022500); in pramin_init()
85 addr = nvkm_rd32(device, 0x625f04); in pramin_init()
87 addr = nvkm_rd32(device, 0x619f04); in pramin_init()
100 addr = (u64)nvkm_rd32(device, 0x001700) << 16; in pramin_init()
111 priv->bar0 = nvkm_rd32(device, 0x001700); in pramin_init()
/drivers/gpu/drm/nouveau/nvkm/subdev/bus/
Dnv31.c35 u32 stat = nvkm_rd32(device, 0x001100) & nvkm_rd32(device, 0x001140); in nv31_bus_intr()
36 u32 gpio = nvkm_rd32(device, 0x001104) & nvkm_rd32(device, 0x001144); in nv31_bus_intr()
45 u32 addr = nvkm_rd32(device, 0x009084); in nv31_bus_intr()
46 u32 data = nvkm_rd32(device, 0x009088); in nv31_bus_intr()
/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
Dnv40.c63 return nvkm_rd32(device, 0x15b4) & 0x3fff; in nv40_sensor_setup()
67 return nvkm_rd32(device, 0x15b4) & 0xff; in nv40_sensor_setup()
82 core_temp = nvkm_rd32(device, 0x15b4) & 0x3fff; in nv40_temp_get()
85 core_temp = nvkm_rd32(device, 0x15b4) & 0xff; in nv40_temp_get()
126 u32 reg = nvkm_rd32(device, 0x0010f0); in nv40_fan_pwm_get()
134 u32 reg = nvkm_rd32(device, 0x0015f4); in nv40_fan_pwm_get()
136 *divs = nvkm_rd32(device, 0x0015f8); in nv40_fan_pwm_get()
172 uint32_t stat = nvkm_rd32(device, 0x1100); in nv40_therm_intr()
/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
Dg94.c30 u32 intr0 = nvkm_rd32(device, 0x00e054); in g94_gpio_intr_stat()
31 u32 intr1 = nvkm_rd32(device, 0x00e074); in g94_gpio_intr_stat()
32 u32 stat0 = nvkm_rd32(device, 0x00e050) & intr0; in g94_gpio_intr_stat()
33 u32 stat1 = nvkm_rd32(device, 0x00e070) & intr1; in g94_gpio_intr_stat()
44 u32 inte0 = nvkm_rd32(device, 0x00e050); in g94_gpio_intr_mask()
45 u32 inte1 = nvkm_rd32(device, 0x00e070); in g94_gpio_intr_mask()
Dgk104.c30 u32 intr0 = nvkm_rd32(device, 0x00dc00); in gk104_gpio_intr_stat()
31 u32 intr1 = nvkm_rd32(device, 0x00dc80); in gk104_gpio_intr_stat()
32 u32 stat0 = nvkm_rd32(device, 0x00dc08) & intr0; in gk104_gpio_intr_stat()
33 u32 stat1 = nvkm_rd32(device, 0x00dc88) & intr1; in gk104_gpio_intr_stat()
44 u32 inte0 = nvkm_rd32(device, 0x00dc08); in gk104_gpio_intr_mask()
45 u32 inte1 = nvkm_rd32(device, 0x00dc88); in gk104_gpio_intr_mask()
Dga102.c67 return !!(nvkm_rd32(device, 0x021200 + (line * 4)) & 0x00004000); in ga102_gpio_sense()
74 u32 intr0 = nvkm_rd32(device, 0x021640); in ga102_gpio_intr_stat()
75 u32 intr1 = nvkm_rd32(device, 0x02164c); in ga102_gpio_intr_stat()
76 u32 stat0 = nvkm_rd32(device, 0x021648) & intr0; in ga102_gpio_intr_stat()
77 u32 stat1 = nvkm_rd32(device, 0x021654) & intr1; in ga102_gpio_intr_stat()
88 u32 inte0 = nvkm_rd32(device, 0x021648); in ga102_gpio_intr_mask()
89 u32 inte1 = nvkm_rd32(device, 0x021654); in ga102_gpio_intr_mask()
/drivers/gpu/drm/nouveau/nvkm/engine/mpeg/
Dnv50.c65 u32 stat = nvkm_rd32(device, 0x00b100); in nv50_mpeg_intr()
66 u32 type = nvkm_rd32(device, 0x00b230); in nv50_mpeg_intr()
67 u32 mthd = nvkm_rd32(device, 0x00b234); in nv50_mpeg_intr()
68 u32 data = nvkm_rd32(device, 0x00b238); in nv50_mpeg_intr()
109 if (!(nvkm_rd32(device, 0x00b200) & 0x00000001)) in nv50_mpeg_init()
113 nvkm_rd32(device, 0x00b200)); in nv50_mpeg_init()

123456789