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Searched refs:pll_clock (Results 1 – 6 of 6) sorted by relevance

/drivers/ata/
Dpata_pdc2027x.c500 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx) in pdc_adjust_pll() argument
504 long pll_clock_khz = pll_clock / 1000; in pdc_adjust_pll()
589 long pll_clock, usec_elapsed; in pdc_detect_pll_input_clock() local
617 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 * in pdc_detect_pll_input_clock()
621 start_count, end_count, pll_clock); in pdc_detect_pll_input_clock()
623 return pll_clock; in pdc_detect_pll_input_clock()
633 long pll_clock; in pdc_hardware_init() local
641 pll_clock = pdc_detect_pll_input_clock(host); in pdc_hardware_init()
643 dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000); in pdc_hardware_init()
646 pdc_adjust_pll(host, pll_clock, board_idx); in pdc_hardware_init()
/drivers/clk/axs10x/
DMakefile3 obj-y += pll_clock.o
/drivers/gpu/drm/i915/display/
Dintel_dpll.h42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
/drivers/gpu/drm/vc4/
Dvc4_dsi.c842 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup() local
849 if (parent_rate / (divider + 1) < pll_clock) in vc4_dsi_encoder_mode_fixup()
856 pll_clock = parent_rate / divider; in vc4_dsi_encoder_mode_fixup()
857 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c824 u32 pll_clock = mode->clock; in amdgpu_atombios_crtc_set_pll() local
854 amdgpu_pll_compute(adev, pll, amdgpu_crtc->adjusted_clock, &pll_clock, in amdgpu_atombios_crtc_set_pll()
/drivers/gpu/drm/radeon/
Datombios_crtc.c1061 u32 pll_clock = mode->clock; in atombios_crtc_set_pll() local
1094 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1097 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()
1100 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock, in atombios_crtc_set_pll()