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Searched refs:pll_ref_div (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_legacy_crtc.c748 uint32_t pll_ref_div = 0; in radeon_set_pll() local
803 pll_ref_div = lvds->panel_ref_divider; in radeon_set_pll()
837 pll_ref_div = reference_div; in radeon_set_pll()
851 pll_ref_div & 0x3ff, in radeon_set_pll()
861 &pll_ref_div, &pll_fb_post_div, in radeon_set_pll()
878 pll_ref_div, in radeon_set_pll()
901 (unsigned)pll_ref_div, in radeon_set_pll()
906 (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK, in radeon_set_pll()
924 radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div, in radeon_set_pll()
935 if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) && in radeon_set_pll()
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/drivers/clk/tegra/
Dclk-tegra-fixed.c32 u32 val, pll_ref_div; in tegra_osc_clk_init() local
82 pll_ref_div = 1 << val; in tegra_osc_clk_init()
88 0, 1, pll_ref_div); in tegra_osc_clk_init()
92 *pll_ref_freq = *osc_freq / pll_ref_div; in tegra_osc_clk_init()
Dclk-tegra20.c577 u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK; in tegra20_clk_measure_input_freq() local
582 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
586 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
590 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
594 BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1); in tegra20_clk_measure_input_freq()
609 u32 pll_ref_div = readl_relaxed(clk_base + OSC_CTRL) & in tegra20_get_pll_ref_div() local
612 switch (pll_ref_div) { in tegra20_get_pll_ref_div()
620 pr_err("Invalid pll ref divider %d\n", pll_ref_div); in tegra20_get_pll_ref_div()
860 unsigned int pll_ref_div; in tegra20_osc_clk_init() local
870 pll_ref_div = tegra20_get_pll_ref_div(); in tegra20_osc_clk_init()
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/drivers/video/fbdev/aty/
Dmach64_ct.c214 q = par->ref_clk_per * pll->pll_ref_div * 4 / vclk_per; in aty_valid_pll_ct()
227 (par->ref_clk_per * pll->pll_ref_div); in aty_valid_pll_ct()
266 …ret = par->ref_clk_per * pll->ct.pll_ref_div * pll->ct.vclk_post_div_real / pll->ct.vclk_fb_div / … in aty_pll_to_var_ct()
298 pll->ct.pll_ref_div, pll->ct.vclk_post_div, pll->ct.vclk_post_div_real); in aty_set_pll_ct()
389 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_get_pll_ct()
515 pll->ct.pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init_pll_ct()
525 pll->ct.pll_ref_div = par->pll_per * 2 * 255 / par->ref_clk_per; in aty_init_pll_ct()
528 q = par->ref_clk_per * pll->ct.pll_ref_div * 8 / in aty_init_pll_ct()
552 (par->ref_clk_per * pll->ct.pll_ref_div); in aty_init_pll_ct()
579 q = par->ref_clk_per * pll->ct.pll_ref_div * 4 / par->mclk_per; in aty_init_pll_ct()
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Datyfb_base.c1806 u8 pll_ref_div; member
1864 clk.pll_ref_div = pll->ct.pll_ref_div; in atyfb_ioctl()
1890 pll->ct.pll_ref_div = clk.pll_ref_div; in atyfb_ioctl()
2476 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par); in aty_init() local
2478 if (pll_ref_div) { in aty_init()
2480 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max; in aty_init()
2481 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max; in aty_init()
Datyfb.h83 u8 pll_ref_div; member
/drivers/video/fbdev/
Dw100fb.h661 u32 pll_ref_div : 4; member
Dw100fb.c1175 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = pll->M; in w100_pll_set_clk()
1246 w100_pwr_state.pll_ref_fb_div.f.pll_ref_div = 0x0; /* M = 1 */ in w100_pwm_setup()