Searched refs:pll_regs (Results 1 – 7 of 7) sorted by relevance
141 const struct cpu_dfs_regs *pll_regs; member151 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_recalc_rate()152 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_recalc_rate()154 cpu_clkdiv_ratio &= clk->pll_regs->divider_mask; in ap_cpu_clk_recalc_rate()155 cpu_clkdiv_ratio >>= clk->pll_regs->divider_offset; in ap_cpu_clk_recalc_rate()167 cpu_clkdiv_reg = clk->pll_regs->divider_reg + in ap_cpu_clk_set_rate()168 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()169 cpu_force_reg = clk->pll_regs->force_reg + in ap_cpu_clk_set_rate()170 (clk->cluster * clk->pll_regs->cluster_offset); in ap_cpu_clk_set_rate()171 cpu_ratio_reg = clk->pll_regs->ratio_reg + in ap_cpu_clk_set_rate()[all …]
1065 static const u32 pll_regs[] = { variable1104 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h616_ccu_probe()1105 val = readl(reg + pll_regs[i]); in sun50i_h616_ccu_probe()1107 writel(val, reg + pll_regs[i]); in sun50i_h616_ccu_probe()
1160 static const u32 pll_regs[] = { variable1209 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun50i_h6_ccu_probe()1210 val = readl(reg + pll_regs[i]); in sun50i_h6_ccu_probe()1212 writel(val, reg + pll_regs[i]); in sun50i_h6_ccu_probe()
1305 static const u32 pll_regs[] = { variable1339 for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { in sun20i_d1_ccu_probe()1340 val = readl(reg + pll_regs[i]); in sun20i_d1_ccu_probe()1342 writel(val, reg + pll_regs[i]); in sun20i_d1_ccu_probe()
271 __be16 pll_regs[] = { in ar0521_write_mode() local292 ret = ar0521_write_regs(sensor, pll_regs, ARRAY_SIZE(pll_regs)); in ar0521_write_mode()
936 struct sensor_register pll_regs[] = { in ov2659_set_pixel_clock() local945 return ov2659_write_array(client, pll_regs); in ov2659_set_pixel_clock()
3077 u8 pll_regs[16]; in atyfb_setup_sparc() local3097 pll_regs[i] = aty_ld_pll_ct(i, par); in atyfb_setup_sparc()3102 M = pll_regs[PLL_REF_DIV]; in atyfb_setup_sparc()3107 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()3112 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()3113 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()