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Searched refs:pol (Results 1 – 25 of 49) sorted by relevance

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/drivers/net/ethernet/microchip/lan966x/
Dlan966x_police.c19 struct lan966x_tc_policer *pol, in lan966x_police_add() argument
25 pol->rate = DIV_ROUND_UP(pol->rate * 3, 100); in lan966x_police_add()
27 pol->burst = pol->burst ?: 1; in lan966x_police_add()
29 pol->burst = DIV_ROUND_UP(pol->burst, 4096); in lan966x_police_add()
31 if (pol->rate > GENMASK(15, 0) || in lan966x_police_add()
32 pol->burst > GENMASK(6, 0)) in lan966x_police_add()
45 lan_wr(ANA_POL_PIR_CFG_PIR_RATE_SET(pol->rate) | in lan966x_police_add()
46 ANA_POL_PIR_CFG_PIR_BURST_SET(pol->burst), in lan966x_police_add()
144 struct lan966x_tc_policer pol; in lan966x_police_port_add() local
153 memset(&pol, 0, sizeof(pol)); in lan966x_police_port_add()
[all …]
/drivers/cpufreq/
Dpowernow-k8.c923 struct cpufreq_policy *pol; member
930 struct cpufreq_policy *pol = pta->pol; in powernowk8_target_fn() local
932 struct powernow_k8_data *data = per_cpu(powernow_data, pol->cpu); in powernowk8_target_fn()
949 pol->cpu, data->powernow_table[newstate].frequency, pol->min, in powernowk8_target_fn()
950 pol->max); in powernowk8_target_fn()
969 ret = transition_frequency_fidvid(data, newstate, pol); in powernowk8_target_fn()
978 pol->cur = find_khz_freq_from_fid(data->currfid); in powernowk8_target_fn()
984 static int powernowk8_target(struct cpufreq_policy *pol, unsigned index) in powernowk8_target() argument
986 struct powernowk8_target_arg pta = { .pol = pol, .newstate = index }; in powernowk8_target()
988 return work_on_cpu(pol->cpu, powernowk8_target_fn, &pta); in powernowk8_target()
[all …]
/drivers/media/platform/sunxi/sun4i-csi/
Dsun4i_csi.h25 #define CSI_CFG_VREF_POL(pol) ((pol) << 2) argument
26 #define CSI_CFG_HREF_POL(pol) ((pol) << 1) argument
27 #define CSI_CFG_PCLK_POL(pol) ((pol) << 0) argument
/drivers/irqchip/
Dirq-tb10x.c45 uint32_t im, mod, pol; in tb10x_irq_set_type() local
52 pol = ab_irqctl_readreg(gc, AB_IRQCTL_SRC_POLARITY) | im; in tb10x_irq_set_type()
56 pol ^= im; in tb10x_irq_set_type()
66 pol ^= im; in tb10x_irq_set_type()
81 ab_irqctl_writereg(gc, AB_IRQCTL_SRC_POLARITY, pol); in tb10x_irq_set_type()
Dirq-mips-gic.c209 unsigned int irq, pol, trig, dual; in gic_set_type() local
217 pol = GIC_POL_FALLING_EDGE; in gic_set_type()
222 pol = GIC_POL_RISING_EDGE; in gic_set_type()
227 pol = 0; /* Doesn't matter */ in gic_set_type()
232 pol = GIC_POL_ACTIVE_LOW; in gic_set_type()
238 pol = GIC_POL_ACTIVE_HIGH; in gic_set_type()
244 change_gic_pol(irq, pol); in gic_set_type()
/drivers/gpu/drm/fsl-dcu/
Dfsl_dcu_drm_crtc.c88 unsigned int pol = 0; in fsl_dcu_drm_crtc_mode_set_nofb() local
97 pol |= DCU_SYN_POL_INV_PXCK; in fsl_dcu_drm_crtc_mode_set_nofb()
100 pol |= DCU_SYN_POL_INV_HS_LOW; in fsl_dcu_drm_crtc_mode_set_nofb()
103 pol |= DCU_SYN_POL_INV_VS_LOW; in fsl_dcu_drm_crtc_mode_set_nofb()
116 regmap_write(fsl_dev->regmap, DCU_SYN_POL, pol); in fsl_dcu_drm_crtc_mode_set_nofb()
/drivers/gpu/drm/omapdrm/dss/
Dhdmi_phy.c37 u8 lane, pol; in hdmi_phy_parse_lanes() local
52 pol = 1; in hdmi_phy_parse_lanes()
56 pol = 0; in hdmi_phy_parse_lanes()
62 phy->lane_polarity[lane] = pol; in hdmi_phy_parse_lanes()
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_phy.c46 u8 lane, pol; in hdmi_phy_parse_lanes() local
61 pol = 1; in hdmi_phy_parse_lanes()
65 pol = 0; in hdmi_phy_parse_lanes()
71 phy->lane_polarity[lane] = pol; in hdmi_phy_parse_lanes()
/drivers/gpio/
Dgpio-xlp.c134 int pol, irq_type; in xlp_gpio_set_irq_type() local
139 pol = XLP_GPIO_IRQ_POL_HIGH; in xlp_gpio_set_irq_type()
143 pol = XLP_GPIO_IRQ_POL_LOW; in xlp_gpio_set_irq_type()
147 pol = XLP_GPIO_IRQ_POL_HIGH; in xlp_gpio_set_irq_type()
151 pol = XLP_GPIO_IRQ_POL_LOW; in xlp_gpio_set_irq_type()
158 xlp_gpio_set_reg(priv->gpio_intr_pol, d->hwirq, pol); in xlp_gpio_set_irq_type()
Dgpio-grgpio.c124 u32 pol; in grgpio_irq_set_type() local
129 pol = 0; in grgpio_irq_set_type()
133 pol = mask; in grgpio_irq_set_type()
137 pol = 0; in grgpio_irq_set_type()
141 pol = mask; in grgpio_irq_set_type()
153 priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol); in grgpio_irq_set_type()
Dgpio-dwapb.c185 u32 pol; in dwapb_toggle_trigger() local
192 pol = dwapb_read(gpio, GPIO_INT_POLARITY); in dwapb_toggle_trigger()
196 pol &= ~BIT(offs); in dwapb_toggle_trigger()
198 pol |= BIT(offs); in dwapb_toggle_trigger()
200 dwapb_write(gpio, GPIO_INT_POLARITY, pol); in dwapb_toggle_trigger()
/drivers/mfd/
Dwm8350-gpio.c162 static int gpio_set_polarity(struct wm8350 *wm8350, int gpio, int pol) in gpio_set_polarity() argument
164 if (pol == WM8350_GPIO_ACTIVE_HIGH) in gpio_set_polarity()
184 int pol, int pull, int invert, int debounce) in wm8350_gpio_config() argument
206 if (gpio_set_polarity(wm8350, gpio, pol)) in wm8350_gpio_config()
/drivers/net/ethernet/mscc/
Docelot_police.c203 struct ocelot_policer *pol) in ocelot_port_policer_add() argument
208 if (!pol) in ocelot_port_policer_add()
212 pp.pir = pol->rate; in ocelot_port_policer_add()
213 pp.pbs = pol->burst; in ocelot_port_policer_add()
/drivers/media/pci/zoran/
Dzr36060.c484 struct vfe_settings *cap, struct vfe_polarity *pol) in zr36060_set_video() argument
508 reg = (!pol->vsync_pol ? ZR060_VPR_VS_POL : 0) in zr36060_set_video()
509 | (!pol->hsync_pol ? ZR060_VPR_HS_POL : 0) in zr36060_set_video()
510 | (pol->field_pol ? ZR060_VPR_FI_POL : 0) in zr36060_set_video()
511 | (pol->blank_pol ? ZR060_VPR_BL_POL : 0) in zr36060_set_video()
512 | (pol->subimg_pol ? ZR060_VPR_S_IMG_POL : 0) in zr36060_set_video()
513 | (pol->poe_pol ? ZR060_VPR_POE_POL : 0) in zr36060_set_video()
514 | (pol->pvalid_pol ? ZR060_VPR_P_VAL_POL : 0) in zr36060_set_video()
515 | (pol->vclk_pol ? ZR060_VPR_VCLK_POL : 0); in zr36060_set_video()
/drivers/staging/media/omap4iss/
Diss_csiphy.c36 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
44 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
178 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
189 if (lanes->clk.pol > 1 || in omap4iss_csiphy_config()
/drivers/media/platform/ti/omap3isp/
Dispcsiphy.c187 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
196 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
245 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
253 reg |= lanes->clk.pol << ISPCSI2_PHY_CFG_CLOCK_POL_SHIFT; in omap3isp_csiphy_config()
Domap3isp.h70 u8 pol; member
Disp.c2091 buscfg->bus.csi2.lanecfg.clk.pol = in isp_parse_of_csi2_endpoint()
2094 buscfg->bus.csi2.lanecfg.clk.pol, in isp_parse_of_csi2_endpoint()
2102 buscfg->bus.csi2.lanecfg.data[i].pol = in isp_parse_of_csi2_endpoint()
2106 buscfg->bus.csi2.lanecfg.data[i].pol, in isp_parse_of_csi2_endpoint()
2121 buscfg->bus.ccp2.lanecfg.clk.pol = vep->bus.mipi_csi1.lane_polarity[0]; in isp_parse_of_csi1_endpoint()
2123 buscfg->bus.ccp2.lanecfg.clk.pol, in isp_parse_of_csi1_endpoint()
2127 buscfg->bus.ccp2.lanecfg.data[0].pol = in isp_parse_of_csi1_endpoint()
2131 buscfg->bus.ccp2.lanecfg.data[0].pol, in isp_parse_of_csi1_endpoint()
/drivers/input/touchscreen/
Dwm97xx-core.c228 enum wm97xx_gpio_pol pol, enum wm97xx_gpio_sticky sticky, in wm97xx_config_gpio() argument
236 if (pol == WM97XX_GPIO_POL_HIGH) in wm97xx_config_gpio()
304 u16 status, pol; in wm97xx_pen_interrupt() local
307 pol = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); in wm97xx_pen_interrupt()
309 if (WM97XX_GPIO_13 & pol & status) { in wm97xx_pen_interrupt()
311 wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol & in wm97xx_pen_interrupt()
315 wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol | in wm97xx_pen_interrupt()
/drivers/ssb/
Ddriver_gpio.c127 u32 pol = chipco_read32(chipco, SSB_CHIPCO_GPIOPOL); in ssb_gpio_irq_chipco_handler() local
128 unsigned long irqs = (val ^ pol) & mask; in ssb_gpio_irq_chipco_handler()
326 u32 pol = ssb_read32(extif->dev, SSB_EXTIF_GPIO_INTPOL); in ssb_gpio_irq_extif_handler() local
327 unsigned long irqs = (val ^ pol) & mask; in ssb_gpio_irq_extif_handler()
/drivers/counter/
Dti-ecap-capture.c237 size_t idx, enum counter_signal_polarity *pol) in ecap_cnt_pol_read() argument
246 *pol = bitval ? COUNTER_SIGNAL_POLARITY_NEGATIVE : COUNTER_SIGNAL_POLARITY_POSITIVE; in ecap_cnt_pol_read()
253 size_t idx, enum counter_signal_polarity pol) in ecap_cnt_pol_write() argument
258 if (pol == COUNTER_SIGNAL_POLARITY_NEGATIVE) in ecap_cnt_pol_write()
/drivers/bcma/
Ddriver_gpio.c110 u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL); in bcma_gpio_irq_handler() local
111 unsigned long irqs = (val ^ pol) & mask; in bcma_gpio_irq_handler()
/drivers/acpi/
Dresource.c622 u8 pol = p ? ACPI_ACTIVE_LOW : ACPI_ACTIVE_HIGH; in acpi_dev_get_irqresource() local
624 if (triggering != trig || polarity != pol) { in acpi_dev_get_irqresource()
629 pol == polarity ? "" : "(!)"); in acpi_dev_get_irqresource()
631 polarity = pol; in acpi_dev_get_irqresource()
/drivers/pinctrl/mediatek/
Dmtk-eint.h26 unsigned int pol; member
/drivers/media/platform/qcom/camss/
Dcamss-csiphy.h26 u8 pol; member

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