1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */ 2 /* Copyright(c) 2014 - 2020 Intel Corporation */ 3 #ifndef _ICP_QAT_FW_INIT_ADMIN_H_ 4 #define _ICP_QAT_FW_INIT_ADMIN_H_ 5 6 #include "icp_qat_fw.h" 7 8 enum icp_qat_fw_init_admin_cmd_id { 9 ICP_QAT_FW_INIT_AE = 0, 10 ICP_QAT_FW_TRNG_ENABLE = 1, 11 ICP_QAT_FW_TRNG_DISABLE = 2, 12 ICP_QAT_FW_CONSTANTS_CFG = 3, 13 ICP_QAT_FW_STATUS_GET = 4, 14 ICP_QAT_FW_COUNTERS_GET = 5, 15 ICP_QAT_FW_LOOPBACK = 6, 16 ICP_QAT_FW_HEARTBEAT_SYNC = 7, 17 ICP_QAT_FW_HEARTBEAT_GET = 8, 18 ICP_QAT_FW_COMP_CAPABILITY_GET = 9, 19 ICP_QAT_FW_PM_STATE_CONFIG = 128, 20 }; 21 22 enum icp_qat_fw_init_admin_resp_status { 23 ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0, 24 ICP_QAT_FW_INIT_RESP_STATUS_FAIL 25 }; 26 27 struct icp_qat_fw_init_admin_req { 28 __u16 init_cfg_sz; 29 __u8 resrvd1; 30 __u8 cmd_id; 31 __u32 resrvd2; 32 __u64 opaque_data; 33 __u64 init_cfg_ptr; 34 35 union { 36 struct { 37 __u16 ibuf_size_in_kb; 38 __u16 resrvd3; 39 }; 40 __u32 idle_filter; 41 }; 42 43 __u32 resrvd4; 44 } __packed; 45 46 struct icp_qat_fw_init_admin_resp { 47 __u8 flags; 48 __u8 resrvd1; 49 __u8 status; 50 __u8 cmd_id; 51 union { 52 __u32 resrvd2; 53 struct { 54 __u16 version_minor_num; 55 __u16 version_major_num; 56 }; 57 __u32 extended_features; 58 }; 59 __u64 opaque_data; 60 union { 61 __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4]; 62 struct { 63 __u32 version_patch_num; 64 __u8 context_id; 65 __u8 ae_id; 66 __u16 resrvd4; 67 __u64 resrvd5; 68 }; 69 struct { 70 __u64 req_rec_count; 71 __u64 resp_sent_count; 72 }; 73 struct { 74 __u16 compression_algos; 75 __u16 checksum_algos; 76 __u32 deflate_capabilities; 77 __u32 resrvd6; 78 __u32 lzs_capabilities; 79 }; 80 struct { 81 __u32 cipher_algos; 82 __u32 hash_algos; 83 __u16 keygen_algos; 84 __u16 other; 85 __u16 public_key_algos; 86 __u16 prime_algos; 87 }; 88 struct { 89 __u64 timestamp; 90 __u64 resrvd7; 91 }; 92 struct { 93 __u32 successful_count; 94 __u32 unsuccessful_count; 95 __u64 resrvd8; 96 }; 97 }; 98 } __packed; 99 100 #define ICP_QAT_FW_COMN_HEARTBEAT_OK 0 101 #define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1 102 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0 103 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1 104 #define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE 105 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \ 106 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags) 107 108 #define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \ 109 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val) 110 111 #define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \ 112 QAT_FIELD_GET(flags, \ 113 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \ 114 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK) 115 #endif 116