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Searched refs:rFPGA0_XAB_RFInterfaceSW (Results 1 – 11 of 11) sorted by relevance

/drivers/staging/rtl8192u/
Dr819xU_phyreg.h28 #define rFPGA0_XAB_RFInterfaceSW 0x870 macro
Dr819xU_phy.c549 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
551 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in rtl8192_InitBBRFRegDef()
/drivers/staging/r8188eu/hal/
DHalPhyRf_8188e.c657 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, in phy_IQCalibrate_8188E()
686 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01); in phy_IQCalibrate_8188E()
687 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01); in phy_IQCalibrate_8188E()
Drtl8188e_phycfg.c355 pHalData->PHYRegDef.rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ in phy_InitBBRFRegisterDefinition()
/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c311 …pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
312 …pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from… in phy_InitBBRFRegisterDefinition()
DHalPhyRf_8723B.c1361 rFPGA0_XAB_RFInterfaceSW, in phy_IQCalibrate_8723B()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h73 #define rFPGA0_XAB_RFInterfaceSW 0x870 macro
Dr8192E_phy.c364 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
365 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; in _rtl92e_init_bb_rf_reg_def()
/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h115 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Ctrl */ macro
/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h127 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ macro
/drivers/staging/r8188eu/include/
DHal8188EPhyReg.h81 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Iface Software Control */ macro