Home
last modified time | relevance | path

Searched refs:rFPGA0_XA_RFInterfaceOE (Results 1 – 12 of 12) sorted by relevance

/drivers/staging/rtl8192u/
Dr819xU_phyreg.h24 #define rFPGA0_XA_RFInterfaceOE 0x860 macro
Dr819xU_phy.c569 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; in rtl8192_InitBBRFRegDef()
579 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; in rtl8192_InitBBRFRegDef()
1075 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), in rtl8192_SetRFPowerState()
1100 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), in rtl8192_SetRFPowerState()
/drivers/staging/r8188eu/hal/
Drtl8188e_phycfg.c361 pHalData->PHYRegDef.rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ in phy_InitBBRFRegisterDefinition()
364 …pHalData->PHYRegDef.rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-b… in phy_InitBBRFRegisterDefinition()
DHalPhyRf_8188e.c657 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, in phy_IQCalibrate_8188E()
688 rtl8188e_PHY_SetBBReg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00); in phy_IQCalibrate_8188E()
Dusb_halinit.c529 if (rtl8188e_PHY_QueryBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A) in _InitAntenna_Selection()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c374 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; in _rtl92e_init_bb_rf_reg_def()
379 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; in _rtl92e_init_bb_rf_reg_def()
1292 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); in rtl92e_set_rf_off()
1349 rtl92e_set_bb_reg(dev, rFPGA0_XA_RFInterfaceOE, in _rtl92e_set_rf_power_state()
Dr8192E_phyreg.h69 #define rFPGA0_XA_RFInterfaceOE 0x860 macro
/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c315 …pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()
319 …pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from … in phy_InitBBRFRegisterDefinition()
DHalPhyRf_8723B.c1362 rFPGA0_XA_RFInterfaceOE, in phy_IQCalibrate_8723B()
/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h111 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ macro
/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h122 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ macro
/drivers/staging/r8188eu/include/
DHal8188EPhyReg.h78 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ macro