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Searched refs:radeon_bo_size (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_cs.c444 if (offset > radeon_bo_size(track->cb_color_bo[id])) { in evergreen_cs_track_validate_cb()
457 bsize = radeon_bo_size(track->cb_color_bo[id]); in evergreen_cs_track_validate_cb()
482 radeon_bo_size(track->cb_color_bo[id]), slice); in evergreen_cs_track_validate_cb()
551 if (size > radeon_bo_size(track->htile_bo)) { in evergreen_cs_track_validate_htile()
553 __func__, __LINE__, radeon_bo_size(track->htile_bo), in evergreen_cs_track_validate_htile()
618 if (offset > radeon_bo_size(track->db_s_read_bo)) { in evergreen_cs_track_validate_stencil()
623 radeon_bo_size(track->db_s_read_bo)); in evergreen_cs_track_validate_stencil()
637 if (offset > radeon_bo_size(track->db_s_write_bo)) { in evergreen_cs_track_validate_stencil()
642 radeon_bo_size(track->db_s_write_bo)); in evergreen_cs_track_validate_stencil()
716 if (offset > radeon_bo_size(track->db_z_read_bo)) { in evergreen_cs_track_validate_depth()
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Dr600_cs.c441 if ((tmp + track->cb_color_bo_offset[i]) > radeon_bo_size(track->cb_color_bo[i])) { in r600_cs_track_validate_cb()
453 radeon_bo_size(track->cb_color_bo[i]), in r600_cs_track_validate_cb()
480 radeon_bo_size(track->cb_color_frag_bo[i])) { in r600_cs_track_validate_cb()
485 radeon_bo_size(track->cb_color_frag_bo[i])); in r600_cs_track_validate_cb()
498 radeon_bo_size(track->cb_color_tile_bo[i])) { in r600_cs_track_validate_cb()
503 radeon_bo_size(track->cb_color_tile_bo[i])); in r600_cs_track_validate_cb()
555 tmp = radeon_bo_size(track->db_bo) - track->db_offset; in r600_cs_track_validate_db()
560 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
620 if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { in r600_cs_track_validate_db()
624 radeon_bo_size(track->db_bo)); in r600_cs_track_validate_db()
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Dradeon_fb.c266 memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); in radeonfb_create()
272 info->fix.smem_len = radeon_bo_size(rbo); in radeonfb_create()
274 info->screen_size = radeon_bo_size(rbo); in radeonfb_create()
291 DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); in radeonfb_create()
Dradeon_object.c326 bo->rdev->vram_pin_size += radeon_bo_size(bo); in radeon_bo_pin_restricted()
328 bo->rdev->gart_pin_size += radeon_bo_size(bo); in radeon_bo_pin_restricted()
345 bo->rdev->vram_pin_size -= radeon_bo_size(bo); in radeon_bo_unpin()
347 bo->rdev->gart_pin_size -= radeon_bo_size(bo); in radeon_bo_unpin()
Dradeon_mn.c101 radeon_bo_size(bo), &radeon_mn_ops); in radeon_mn_register()
Dradeon_uvd.c293 size = radeon_bo_size(rdev->uvd.vcpu_bo); in radeon_uvd_resume()
583 end = start + radeon_bo_size(reloc->robj); in radeon_uvd_cs_reloc()
771 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_create_msg()
807 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_destroy_msg()
Dr100.c1908 if ((value + 1) > radeon_bo_size(robj)) { in r100_cs_track_check_pkt3_indx_buffer()
1912 radeon_bo_size(robj)); in r100_cs_track_check_pkt3_indx_buffer()
2153 if (size > radeon_bo_size(cube_robj)) { in r100_cs_track_cube()
2155 size, radeon_bo_size(cube_robj)); in r100_cs_track_cube()
2235 if (size > radeon_bo_size(robj)) { in r100_cs_track_texture_check()
2237 "%lu\n", u, size, radeon_bo_size(robj)); in r100_cs_track_texture_check()
2264 if (size > radeon_bo_size(track->cb[i].robj)) { in r100_cs_track_check()
2267 radeon_bo_size(track->cb[i].robj)); in r100_cs_track_check()
2283 if (size > radeon_bo_size(track->zb.robj)) { in r100_cs_track_check()
2286 radeon_bo_size(track->zb.robj)); in r100_cs_track_check()
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Dradeon_object.h110 static inline unsigned long radeon_bo_size(struct radeon_bo *bo) in radeon_bo_size() function
Dradeon_vce.c241 memset(cpu_addr, 0, radeon_bo_size(rdev->vce.vcpu_bo)); in radeon_vce_resume()
489 end = start + radeon_bo_size(reloc->robj); in radeon_vce_cs_reloc()
Dradeon_gem.c879 i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, in radeon_debugfs_gem_info_show()
Dradeon_legacy_crtc.c454 osize = radeon_bo_size(old_rbo); in radeon_crtc_do_set_base()
455 nsize = radeon_bo_size(rbo); in radeon_crtc_do_set_base()
Dradeon_vm.c406 entries = radeon_bo_size(bo) / 8; in radeon_vm_clear_bo()
452 uint64_t size = radeon_bo_size(bo_va->bo); in radeon_vm_bo_set_addr()