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Searched refs:refin (Results 1 – 3 of 3) sorted by relevance

/drivers/clk/sprd/
Dpll.c72 const unsigned long refin[4] = { 2, 4, 13, 26 }; in pll_get_refin() local
83 return refin[refin_id]; in pll_get_refin()
104 u64 refin; in _sprd_pll_recalc_rate() local
114 refin = pll_get_refin(pll); in _sprd_pll_recalc_rate()
117 refin = refin * 2; in _sprd_pll_recalc_rate()
122 refin = refin / 2; in _sprd_pll_recalc_rate()
125 rate = refin * pinternal_val(pll, cfg, PLL_N) * CLK_PLL_10M; in _sprd_pll_recalc_rate()
135 rate = DIV_ROUND_CLOSEST_ULL(refin * kint * k1, in _sprd_pll_recalc_rate()
137 k2 + refin * nint * CLK_PLL_1M; in _sprd_pll_recalc_rate()
156 u64 tmp, refin, fvco = rate; in _sprd_pll_set_rate() local
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/drivers/gpu/drm/sprd/
Dsprd_dsi.h68 u8 refin; /* Pre-divider control signal */ member
Dmegacores_pll.c72 pll->refin = 3; /* pre-divider bypass */ in dphy_calc_pll_param()
94 reg_val[3] = pll->vco_band | (pll->sdm_en << 1) | (pll->refin << 2); in dphy_set_pll_reg()