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Searched refs:regCP_RB0_BASE_HI (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h565 #define regCP_RB0_BASE_HI … macro
Dgc_11_0_0_offset.h4312 #define regCP_RB0_BASE_HI … macro
Dgc_11_0_3_offset.h4528 #define regCP_RB0_BASE_HI … macro
/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c3220 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr)); in gfx_v11_0_cp_gfx_resume()