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Searched refs:regCP_RB1_CNTL (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dgfx_v11_0.c3236 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
3253 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp); in gfx_v11_0_cp_gfx_resume()
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h419 #define regCP_RB1_CNTL … macro
Dgc_11_0_0_offset.h4190 #define regCP_RB1_CNTL … macro
Dgc_11_0_3_offset.h4400 #define regCP_RB1_CNTL … macro