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Searched refs:regGRBM_STATUS_SE0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsoc21.c235 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h3320 #define regGRBM_STATUS_SE0 … macro
Dgc_11_0_0_offset.h1848 #define regGRBM_STATUS_SE0 … macro
Dgc_11_0_3_offset.h1912 #define regGRBM_STATUS_SE0 … macro