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Searched refs:regMP0_SMN_IH_SW_INT_CTRL (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_13_0_8_offset.h180 #define regMP0_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_2_offset.h227 #define regMP0_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_4_offset.h227 #define regMP0_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_0_offset.h177 #define regMP0_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_5_offset.h179 #define regMP0_SMN_IH_SW_INT_CTRL … macro