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Searched refs:reg_num (Results 1 – 25 of 130) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/irq/dcn201/
Dirq_service_dcn201.c154 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
155 .enable_reg = SRI(reg1, block, reg_num),\
157 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
159 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
160 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
162 .ack_reg = SRI(reg2, block, reg_num),\
164 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
166 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
168 #define hpd_int_entry(reg_num)\ argument
169 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce120/
Dirq_service_dce120.c103 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
104 .enable_reg = SRI(reg1, block, reg_num),\
106 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
108 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
109 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
111 .ack_reg = SRI(reg2, block, reg_num),\
113 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
115 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
117 #define hpd_int_entry(reg_num)\ argument
118 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn303/
Dirq_service_dcn303.c119 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
120 .enable_reg = SRI(reg1, block, reg_num),\
121 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
123 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
124 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
126 .ack_reg = SRI(reg2, block, reg_num),\
127 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
128 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
132 #define hpd_int_entry(reg_num)\ argument
133 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dce80/
Dirq_service_dce80.c92 #define hpd_int_entry(reg_num)\ argument
93 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
94 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
100 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
103 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
107 #define hpd_rx_int_entry(reg_num)\ argument
108 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
109 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
114 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
117 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
Dirq_service_dcn10.c200 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
201 .enable_reg = SRI(reg1, block, reg_num),\
203 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
205 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
206 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
208 .ack_reg = SRI(reg2, block, reg_num),\
210 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
212 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
214 #define hpd_int_entry(reg_num)\ argument
215 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn20/
Dirq_service_dcn20.c205 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
206 .enable_reg = SRI(reg1, block, reg_num),\
208 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
210 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
211 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
213 .ack_reg = SRI(reg2, block, reg_num),\
215 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
217 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
221 #define hpd_int_entry(reg_num)\ argument
222 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dce60/
Dirq_service_dce60.c101 #define hpd_int_entry(reg_num)\ argument
102 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
103 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
109 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
112 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
116 #define hpd_rx_int_entry(reg_num)\ argument
117 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
118 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
123 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
126 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
Dirq_service_dcn32.c209 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
210 .enable_reg = SRI(reg1, block, reg_num),\
212 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
215 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
217 .ack_reg = SRI(reg2, block, reg_num),\
219 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
237 #define hpd_int_entry(reg_num)\ argument
238 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn31/
Dirq_service_dcn31.c208 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
209 .enable_reg = SRI(reg1, block, reg_num),\
211 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
213 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
214 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
216 .ack_reg = SRI(reg2, block, reg_num),\
218 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
220 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
236 #define hpd_int_entry(reg_num)\ argument
237 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn315/
Dirq_service_dcn315.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 .ack_reg = SRI(reg2, block, reg_num),\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
243 #define hpd_int_entry(reg_num)\ argument
244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn302/
Dirq_service_dcn302.c195 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .enable_reg = SRI(reg1, block, reg_num),\
197 .enable_mask = block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
200 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
202 .ack_reg = SRI(reg2, block, reg_num),\
203 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
227 #define hpd_int_entry(reg_num)\ argument
228 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
Dirq_service_dcn30.c220 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
221 .enable_reg = SRI(reg1, block, reg_num),\
223 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
225 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
226 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
228 .ack_reg = SRI(reg2, block, reg_num),\
230 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
232 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
248 #define hpd_int_entry(reg_num)\ argument
249 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn314/
Dirq_service_dcn314.c211 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
212 .enable_reg = SRI(reg1, block, reg_num),\
214 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
216 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
217 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
219 .ack_reg = SRI(reg2, block, reg_num),\
221 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
223 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
239 #define hpd_int_entry(reg_num)\ argument
240 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/drivers/gpu/drm/amd/display/dc/irq/dcn21/
Dirq_service_dcn21.c215 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
216 .enable_reg = SRI(reg1, block, reg_num),\
218 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
221 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 .ack_reg = SRI(reg2, block, reg_num),\
225 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
243 #define hpd_int_entry(reg_num)\ argument
244 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce110/
Dirq_service_dce110.c89 #define hpd_int_entry(reg_num)\ argument
90 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
91 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
97 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
100 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
104 #define hpd_rx_int_entry(reg_num)\ argument
105 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
106 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
111 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
114 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
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/drivers/video/fbdev/via/
Dhw.h355 int reg_num; member
361 int reg_num; member
367 int reg_num; member
373 int reg_num; member
379 int reg_num; member
385 int reg_num; member
391 int reg_num; member
397 int reg_num; member
403 int reg_num; member
409 int reg_num; member
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/drivers/irqchip/
Dirq-imx-irqsteer.c34 int reg_num; member
43 return (data->reg_num - irqnum / 32 - 1); in imx_irqsteer_get_reg_index()
54 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
56 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_unmask()
68 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
70 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num)); in imx_irqsteer_irq_mask()
128 if (hwirq >= data->reg_num * 32) in imx_irqsteer_irq_handler()
132 CHANSTATUS(idx, data->reg_num)); in imx_irqsteer_irq_handler()
177 data->reg_num = irqs_num / 32; in imx_irqsteer_probe()
181 sizeof(u32) * data->reg_num, in imx_irqsteer_probe()
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/drivers/net/ethernet/arc/
Demac_mdio.c56 static int arc_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num) in arc_mdio_read() argument
63 0x60020000 | (phy_addr << 23) | (reg_num << 18)); in arc_mdio_read()
72 phy_addr, reg_num, value); in arc_mdio_read()
89 int reg_num, u16 value) in arc_mdio_write() argument
95 phy_addr, reg_num, value); in arc_mdio_write()
98 0x50020000 | (phy_addr << 23) | (reg_num << 18) | value); in arc_mdio_write()
/drivers/input/keyboard/
Dbcm-keypad.c93 static void bcm_kp_report_keys(struct bcm_kp *kp, int reg_num, int pull_mode) in bcm_kp_report_keys() argument
102 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys()
104 state = readl(kp->base + KPSSRN_OFFSET(reg_num)); in bcm_kp_report_keys()
105 change = kp->last_state[reg_num] ^ state; in bcm_kp_report_keys()
106 kp->last_state[reg_num] = state; in bcm_kp_report_keys()
112 row = BIT_TO_ROW_SSRN(bit_nr, reg_num); in bcm_kp_report_keys()
123 int reg_num; in bcm_kp_isr_thread() local
125 for (reg_num = 0; reg_num <= 1; reg_num++) in bcm_kp_isr_thread()
126 bcm_kp_report_keys(kp, reg_num, pull_mode); in bcm_kp_isr_thread()
/drivers/crypto/qat/qat_common/
Dqat_hal.c248 unsigned short reg_num) in qat_hal_get_reg_addr() argument
255 reg_addr = 0x80 | (reg_num & 0x7f); in qat_hal_get_reg_addr()
259 reg_addr = reg_num & 0x1f; in qat_hal_get_reg_addr()
264 reg_addr = 0x180 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
267 reg_addr = 0x140 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
272 reg_addr = 0x1c0 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
275 reg_addr = 0x100 | ((reg_num & 0x3) << 1); in qat_hal_get_reg_addr()
278 reg_addr = 0x280 | (reg_num & 0x1f); in qat_hal_get_reg_addr()
293 reg_addr = 0x300 | (reg_num & 0xff); in qat_hal_get_reg_addr()
1112 unsigned short reg_num, unsigned int *data) in qat_hal_rd_rel_reg() argument
[all …]
/drivers/w1/
Dw1.c102 ssize_t count = sizeof(sl->reg_num); in id_show()
104 memcpy(buf, (u8 *)&sl->reg_num, count); in id_show()
448 if (sl->reg_num.family == rn->family && in w1_slave_search_device()
449 sl->reg_num.id == rn->id && in w1_slave_search_device()
450 sl->reg_num.crc == rn->crc) { in w1_slave_search_device()
606 err = add_uevent_var(env, "W1_FID=%02X", sl->reg_num.family); in w1_uevent()
611 (unsigned long long)sl->reg_num.id); in w1_uevent()
687 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
688 (unsigned long long) sl->reg_num.id); in __w1_attach_slave_device()
691 (unsigned int) sl->reg_num.family, in __w1_attach_slave_device()
[all …]
/drivers/gpu/drm/amd/display/dc/
Ddm_services.h164 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
167 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
168 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
170 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
174 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
175 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
/drivers/soc/fsl/qe/
Ducc.c89 unsigned int *reg_num, unsigned int *shift) in get_cmxucr_reg() argument
93 *reg_num = cmx + 1; in get_cmxucr_reg()
101 unsigned int reg_num; in ucc_mux_set_grant_tsa_bkpt() local
108 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_mux_set_grant_tsa_bkpt()
122 unsigned int reg_num; in ucc_set_qe_mux_rxtx() local
134 get_cmxucr_reg(ucc_num, &cmxucr, &reg_num, &shift); in ucc_set_qe_mux_rxtx()
136 switch (reg_num) { in ucc_set_qe_mux_rxtx()
/drivers/media/platform/verisilicon/
Dhantro_g1_h264_dec.c131 int reg_num; in set_ref() local
158 reg_num = 0; in set_ref()
166 vdpu_write_relaxed(vpu, reg, G1_REG_BD_REF_PIC(reg_num++)); in set_ref()
186 reg_num = 0; in set_ref()
194 vdpu_write_relaxed(vpu, reg, G1_REG_FWD_PIC(reg_num++)); in set_ref()
/drivers/mfd/
Dezx-pcap.c77 int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value) in ezx_pcap_write() argument
85 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_write()
93 int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value) in ezx_pcap_read() argument
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_read()
109 int ezx_pcap_set_bits(struct pcap_chip *pcap, u8 reg_num, u32 mask, u32 val) in ezx_pcap_set_bits() argument
114 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_set_bits()
123 (reg_num << PCAP_REGISTER_ADDRESS_SHIFT); in ezx_pcap_set_bits()

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