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Searched refs:res_cap (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/dcn302/
Ddcn302_resource.c722 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_dwbc_create()
757 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn302_mmhubbub_create()
1025 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn302_resource_destruct()
1055 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn302_resource_destruct()
1068 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn302_resource_destruct()
1073 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn302_resource_destruct()
1080 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn302_resource_destruct()
1104 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn302_resource_destruct()
1219 pool->res_cap = &res_cap_dcn302; in dcn302_resource_construct()
1227 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn302_resource_construct()
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/drivers/gpu/drm/amd/display/dc/dcn303/
Ddcn303_resource.c666 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_dwbc_create()
701 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn303_mmhubbub_create()
952 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn303_resource_destruct()
982 for (i = 0; i < pool->res_cap->num_ddc; i++) { in dcn303_resource_destruct()
995 for (i = 0; i < pool->res_cap->num_opp; i++) { in dcn303_resource_destruct()
1000 for (i = 0; i < pool->res_cap->num_timing_generator; i++) { in dcn303_resource_destruct()
1007 for (i = 0; i < pool->res_cap->num_dwb; i++) { in dcn303_resource_destruct()
1031 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn303_resource_destruct()
1147 pool->res_cap = &res_cap_dcn303; in dcn303_resource_construct()
1155 pool->pipe_count = pool->res_cap->num_timing_generator; in dcn303_resource_construct()
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/drivers/gpu/drm/amd/display/dc/dcn301/
Ddcn301_resource.c1077 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn301_destruct()
1107 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn301_destruct()
1120 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn301_destruct()
1125 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1132 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn301_destruct()
1155 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn301_destruct()
1171 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn301_destruct()
1200 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_dwbc_create()
1225 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn301_mmhubbub_create()
1323 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator; in init_soc_bounding_box()
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/drivers/gpu/drm/amd/display/dc/dcn316/
Ddcn316_resource.c1129 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1413 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn316_resource_destruct()
1443 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn316_resource_destruct()
1456 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn316_resource_destruct()
1461 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1468 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn316_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn316_resource_destruct()
1507 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn316_resource_destruct()
1541 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1566 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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/drivers/gpu/drm/amd/display/dc/dcn314/
Ddcn314_resource.c1181 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1462 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn314_resource_destruct()
1491 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn314_resource_destruct()
1504 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn314_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1516 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn314_resource_destruct()
1539 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn314_resource_destruct()
1555 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn314_resource_destruct()
1589 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1614 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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/drivers/gpu/drm/amd/display/dc/dcn315/
Ddcn315_resource.c1133 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1415 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn315_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn315_resource_destruct()
1458 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn315_resource_destruct()
1463 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1470 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn315_resource_destruct()
1493 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn315_resource_destruct()
1509 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn315_resource_destruct()
1543 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1568 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_resource.c1134 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc) in dcn31_link_enc_create_minimal()
1414 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn31_resource_destruct()
1444 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn31_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn31_resource_destruct()
1462 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1469 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn31_resource_destruct()
1492 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn31_resource_destruct()
1508 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn31_resource_destruct()
1542 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_dwbc_create()
1567 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn31_mmhubbub_create()
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/drivers/gpu/drm/amd/display/dc/dcn321/
Ddcn321_resource.c1388 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn321_resource_destruct()
1417 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn321_resource_destruct()
1430 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn321_resource_destruct()
1435 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1442 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn321_resource_destruct()
1465 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn321_resource_destruct()
1481 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn321_resource_destruct()
1500 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_dwbc_create()
1529 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn321_mmhubbub_create()
1672 pool->base.res_cap = &res_cap_dcn321; in dcn321_resource_construct()
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/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_resource.c1104 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1134 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1147 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1152 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1159 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1182 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1235 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1260 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1462 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1492 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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Ddcn30_hwseq.c391 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
421 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
539 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_resource.c372 static const struct resource_caps res_cap = { variable
822 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
952 pool->base.res_cap = &res_cap; in dce60_construct()
960 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
961 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1073 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1147 pool->base.res_cap = &res_cap_61; in dce61_construct()
1271 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1345 pool->base.res_cap = &res_cap_64; in dce64_construct()
1465 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_resource.c375 static const struct resource_caps res_cap = { variable
825 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
955 pool->base.res_cap = &res_cap; in dce80_construct()
963 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
964 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1082 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1156 pool->base.res_cap = &res_cap_81; in dce81_construct()
1282 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1356 pool->base.res_cap = &res_cap_83; in dce83_construct()
1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
/drivers/gpu/drm/amd/display/dc/dcn32/
Ddcn32_resource.c1402 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn32_resource_destruct()
1432 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn32_resource_destruct()
1445 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn32_resource_destruct()
1450 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1457 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn32_resource_destruct()
1480 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn32_resource_destruct()
1496 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn32_resource_destruct()
1515 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_dwbc_create()
1544 uint32_t dwb_count = pool->res_cap->num_dwb; in dcn32_mmhubbub_create()
1637 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn32_release_post_bldn_3dlut()
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/drivers/gpu/drm/amd/display/dc/dce100/
Ddce100_resource.c374 static const struct resource_caps res_cap = { variable
777 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
989 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1064 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1065 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1120 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1113 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1143 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1156 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1161 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1168 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1336 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1350 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1364 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
2232 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_dwbc_create()
2255 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn20_mmhubbub_create()
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/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c708 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
738 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
751 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
756 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
763 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1440 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1444 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1455 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
1673 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
1709 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_construct()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_link_enc_cfg.c40 for (i = 0; i < stream->ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in is_dig_link_enc_stream()
177 for (i = 0; i < ctx->dc->res_pool->res_cap->num_dig_link_enc; i++) { in find_first_avail_link_enc()
260 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in clear_enc_assignments()
523 for (i = 0; i < dc->res_pool->res_cap->num_dig_link_enc; i++) { in link_enc_cfg_get_next_avail_link_enc()
690 for (j = 0; j < dc->res_pool->res_cap->num_dig_link_enc; j++) { in link_enc_cfg_validate()
/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_resource.c497 static const struct resource_caps res_cap = { variable
624 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1066 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1216 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_resource.c953 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_destruct()
958 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_destruct()
1095 pool->base.res_cap = &res_cap_dnc201; in dcn201_resource_construct()
1193 dcn201_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in dcn201_resource_construct()
1228 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn201_resource_construct()
1237 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn201_resource_construct()
1253 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn201_resource_construct()
Ddcn201_hwseq.c183 ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); in dcn201_init_blank()
307 for (i = 0; i < res_pool->res_cap->num_opp; i++) { in dcn201_init_hw()
340 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn201_init_hw()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_resource.c485 static const struct resource_caps res_cap = { variable
959 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1370 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1372 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1386 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1653 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce112/
Ddce112_resource.c798 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1228 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1235 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1236 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1369 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_resource.c836 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1357 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1364 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1366 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1481 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
/drivers/gpu/drm/amd/display/dc/dml/dcn31/
Ddcn31_fpu.c595 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn31_update_bw_bounding_box()
671 dcn3_15_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn315_update_bw_bounding_box()
743 dcn3_16_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator; in dcn316_update_bw_bounding_box()
/drivers/gpu/drm/amd/display/dc/inc/
Dcore_types.h336 const struct resource_caps *res_cap; member

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