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Searched refs:reset_lock (Results 1 – 24 of 24) sorted by relevance

/drivers/clk/mmp/
Dclk-of-pxa1928.c93 static DEFINE_SPINLOCK(reset_lock);
105 … "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
106 … "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
107 … "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI2 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
108 … "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI3 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
109 … "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI4 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
110 … "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_TWSI5 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
111 …O, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_GPIO * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
114 …0, "pwm0_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM0 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
115 …1, "pwm1_clk", "vctcxo", CLK_SET_RATE_PARENT, PXA1928_CLK_PWM1 * 4, 0x3, 0x3, 0x0, 0, &reset_lock},
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Dclk-of-mmp2.c234 static DEFINE_SPINLOCK(reset_lock);
249 …_CLK_TWSI0, "twsi0_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 0x3, 0x0, 0, &reset_lock},
250 …_CLK_TWSI1, "twsi1_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 0x3, 0x0, 0, &reset_lock},
251 …_CLK_TWSI2, "twsi2_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI2, 0x7, 0x3, 0x0, 0, &reset_lock},
252 …_CLK_TWSI3, "twsi3_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 0x3, 0x0, 0, &reset_lock},
253 …_CLK_TWSI4, "twsi4_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI4, 0x7, 0x3, 0x0, 0, &reset_lock},
254 …_CLK_TWSI5, "twsi5_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_TWSI5, 0x7, 0x3, 0x0, 0, &reset_lock},
255 …MP2_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 0x3, 0x0, 0, &reset_lock},
256 …clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 0x3, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
257 …k", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},
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Dclk-of-pxa910.c123 static DEFINE_SPINLOCK(reset_lock);
139 …TWSI0, "twsi0_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 0x3, 0x0, 0, &reset_lock},
140 …910_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 0x3, 0x0, 0, &reset_lock},
143 …10_CLK_PWM0, "pwm0_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM0, 0x3, 0x3, 0x0, 0, &reset_lock},
144 …10_CLK_PWM1, "pwm1_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM1, 0x3, 0x3, 0x0, 0, &reset_lock},
145 …10_CLK_PWM2, "pwm2_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM2, 0x3, 0x3, 0x0, 0, &reset_lock},
146 …10_CLK_PWM3, "pwm3_clk", "pll1_48", CLK_SET_RATE_PARENT, APBC_PWM3, 0x3, 0x3, 0x0, 0, &reset_lock},
157 …WSI1, "twsi1_clk", "pll1_13_1_5", CLK_SET_RATE_PARENT, APBCP_TWSI1, 0x3, 0x3, 0x0, 0, &reset_lock},
Dclk-of-pxa168.c158 static DEFINE_SPINLOCK(reset_lock);
182 …168_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x1, 0x1, 0x0, 0, &reset_lock},
/drivers/pci/hotplug/
Dpciehp_pci.c71 up_read(&ctrl->reset_lock); in pciehp_configure_device()
73 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_configure_device()
119 up_read(&ctrl->reset_lock); in pciehp_unconfigure_device()
121 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_unconfigure_device()
Dpciehp_hpc.c582 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ignore_dpc_link_change()
585 up_read(&ctrl->reset_lock); in pciehp_ignore_dpc_link_change()
746 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_ist()
751 up_read(&ctrl->reset_lock); in pciehp_ist()
906 down_write_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_reset_slot()
926 up_write(&ctrl->reset_lock); in pciehp_reset_slot()
1005 init_rwsem(&ctrl->reset_lock); in pcie_init()
Dpciehp_core.c169 down_read_nested(&ctrl->reset_lock, ctrl->depth); in pciehp_check_presence()
180 up_read(&ctrl->reset_lock); in pciehp_check_presence()
Dpciehp.h110 struct rw_semaphore reset_lock; member
/drivers/vfio/pci/mlx5/
Dmain.c471 spin_lock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
474 spin_unlock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
480 spin_unlock(&mvdev->reset_lock); in mlx5vf_state_mutex_unlock()
541 spin_lock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
544 spin_unlock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
547 spin_unlock(&mvdev->reset_lock); in mlx5vf_pci_aer_reset_done()
Dcmd.h107 spinlock_t reset_lock; member
Dcmd.c158 spin_lock_init(&mvdev->reset_lock); in mlx5vf_cmd_set_migratable()
/drivers/net/ethernet/xilinx/
Dxilinx_emaclite.c128 spinlock_t reset_lock; /* serialize xmit and tx_timeout execution */ member
530 spin_lock_irqsave(&lp->reset_lock, flags); in xemaclite_tx_timeout()
549 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_tx_timeout()
1007 spin_lock_irqsave(&lp->reset_lock, flags); in xemaclite_send()
1017 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_send()
1020 spin_unlock_irqrestore(&lp->reset_lock, flags); in xemaclite_send()
1127 spin_lock_init(&lp->reset_lock); in xemaclite_of_probe()
/drivers/net/ethernet/qualcomm/emac/
Demac.c85 mutex_lock(&adpt->reset_lock); in emac_reinit_locked()
91 mutex_unlock(&adpt->reset_lock); in emac_reinit_locked()
272 mutex_lock(&adpt->reset_lock); in emac_close()
280 mutex_unlock(&adpt->reset_lock); in emac_close()
627 mutex_init(&adpt->reset_lock); in emac_probe()
Demac.h377 struct mutex reset_lock; member
/drivers/hid/i2c-hid/
Di2c-hid-core.c116 struct mutex reset_lock; member
484 mutex_lock(&ihid->reset_lock); in i2c_hid_hwreset()
503 mutex_unlock(&ihid->reset_lock); in i2c_hid_hwreset()
687 mutex_lock(&ihid->reset_lock); in i2c_hid_output_raw_report()
703 mutex_unlock(&ihid->reset_lock); in i2c_hid_output_raw_report()
992 mutex_init(&ihid->reset_lock); in i2c_hid_core_probe()
/drivers/vfio/pci/hisilicon/
Dhisi_acc_vfio_pci.c644 spin_lock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_state_mutex_unlock()
647 spin_unlock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_state_mutex_unlock()
654 spin_unlock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_state_mutex_unlock()
988 spin_lock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_pci_aer_reset_done()
991 spin_unlock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_pci_aer_reset_done()
994 spin_unlock(&hisi_acc_vdev->reset_lock); in hisi_acc_vf_pci_aer_reset_done()
Dhisi_acc_vfio_pci.h111 spinlock_t reset_lock; member
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_reset.h65 struct mutex reset_lock; member
Daldebaran.c167 mutex_lock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
203 mutex_unlock(&tmp_adev->reset_cntl->reset_lock); in aldebaran_mode2_perform_reset()
/drivers/gpu/drm/v3d/
Dv3d_sched.c260 mutex_lock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
280 mutex_unlock(&v3d->reset_lock); in v3d_gpu_reset_for_timeout()
Dv3d_drv.h127 struct mutex reset_lock; member
Dv3d_gem.c1079 mutex_init(&v3d->reset_lock); in v3d_gem_init()
/drivers/scsi/
Dhpsa.h313 spinlock_t reset_lock; member
Dhpsa.c1937 spin_lock_irqsave(&h->reset_lock, flags); in adjust_hpsa_scsi_table()
1940 spin_unlock_irqrestore(&h->reset_lock, flags); in adjust_hpsa_scsi_table()
1943 spin_unlock_irqrestore(&h->reset_lock, flags); in adjust_hpsa_scsi_table()
5807 spin_lock_irqsave(&h->reset_lock, flags); in hpsa_scan_start()
5810 spin_unlock_irqrestore(&h->reset_lock, flags); in hpsa_scan_start()
5814 spin_unlock_irqrestore(&h->reset_lock, flags); in hpsa_scan_start()
6039 spin_lock_irqsave(&h->reset_lock, flags); in hpsa_eh_device_reset_handler()
6041 spin_unlock_irqrestore(&h->reset_lock, flags); in hpsa_eh_device_reset_handler()
6119 spin_lock_irqsave(&h->reset_lock, flags); in hpsa_eh_device_reset_handler()
6123 spin_unlock_irqrestore(&h->reset_lock, flags); in hpsa_eh_device_reset_handler()
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