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Searched refs:rtsx_add_cmd (Results 1 – 9 of 9) sorted by relevance

/drivers/staging/rts5208/
Dspi.c89 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); in sf_polling_status()
90 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_polling_status()
92 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, in sf_polling_status()
115 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_enable_write()
116 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, in sf_enable_write()
118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_enable_write()
120 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, in sf_enable_write()
143 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); in sf_disable_write()
144 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, in sf_disable_write()
146 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, in sf_disable_write()
[all …]
Dxd.c81 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); in xd_read_id()
82 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, in xd_read_id()
84 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, in xd_read_id()
88 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); in xd_read_id()
110 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); in xd_assign_phy_addr()
111 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); in xd_assign_phy_addr()
112 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, in xd_assign_phy_addr()
114 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, in xd_assign_phy_addr()
116 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, in xd_assign_phy_addr()
123 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); in xd_assign_phy_addr()
[all …]
Dsd.c134 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
135 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
136 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
137 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
140 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
141 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
143 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
145 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
152 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
[all …]
Dms.c50 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_tpc()
51 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); in ms_transfer_tpc()
52 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); in ms_transfer_tpc()
53 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, in ms_transfer_tpc()
56 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, in ms_transfer_tpc()
58 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, in ms_transfer_tpc()
61 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); in ms_transfer_tpc()
118 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); in ms_transfer_data()
119 rtsx_add_cmd(chip, WRITE_REG_CMD, in ms_transfer_data()
121 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); in ms_transfer_data()
[all …]
Drtsx_card.c665 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); in switch_ssc_clock()
666 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); in switch_ssc_clock()
667 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); in switch_ssc_clock()
668 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); in switch_ssc_clock()
669 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, n); in switch_ssc_clock()
670 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); in switch_ssc_clock()
672 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
674 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
826 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); in trans_dma_enable()
828 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24)); in trans_dma_enable()
[all …]
Drtsx_transport.h34 void rtsx_add_cmd(struct rtsx_chip *chip, u8 cmd_type, u16 reg_addr, u8 mask,
Drtsx_chip.c2032 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); in rtsx_read_ppbuf()
2046 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0); in rtsx_read_ppbuf()
2074 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, in rtsx_write_ppbuf()
2088 rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, in rtsx_write_ppbuf()
Drtsx_transport.c193 void rtsx_add_cmd(struct rtsx_chip *chip, in rtsx_add_cmd() function
Drtsx_scsi.c1749 rtsx_add_cmd(chip, cmd_type, addr, mask, value); in rw_mem_cmd_buf()