1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Microchip switch driver main logic
4 *
5 * Copyright (C) 2017-2019 Microchip Technology Inc.
6 */
7
8 #include <linux/delay.h>
9 #include <linux/export.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_data/microchip-ksz.h>
14 #include <linux/phy.h>
15 #include <linux/etherdevice.h>
16 #include <linux/if_bridge.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/of_mdio.h>
20 #include <linux/of_device.h>
21 #include <linux/of_net.h>
22 #include <linux/micrel_phy.h>
23 #include <net/dsa.h>
24 #include <net/switchdev.h>
25
26 #include "ksz_common.h"
27 #include "ksz8.h"
28 #include "ksz9477.h"
29 #include "lan937x.h"
30
31 #define MIB_COUNTER_NUM 0x20
32
33 struct ksz_stats_raw {
34 u64 rx_hi;
35 u64 rx_undersize;
36 u64 rx_fragments;
37 u64 rx_oversize;
38 u64 rx_jabbers;
39 u64 rx_symbol_err;
40 u64 rx_crc_err;
41 u64 rx_align_err;
42 u64 rx_mac_ctrl;
43 u64 rx_pause;
44 u64 rx_bcast;
45 u64 rx_mcast;
46 u64 rx_ucast;
47 u64 rx_64_or_less;
48 u64 rx_65_127;
49 u64 rx_128_255;
50 u64 rx_256_511;
51 u64 rx_512_1023;
52 u64 rx_1024_1522;
53 u64 rx_1523_2000;
54 u64 rx_2001;
55 u64 tx_hi;
56 u64 tx_late_col;
57 u64 tx_pause;
58 u64 tx_bcast;
59 u64 tx_mcast;
60 u64 tx_ucast;
61 u64 tx_deferred;
62 u64 tx_total_col;
63 u64 tx_exc_col;
64 u64 tx_single_col;
65 u64 tx_mult_col;
66 u64 rx_total;
67 u64 tx_total;
68 u64 rx_discards;
69 u64 tx_discards;
70 };
71
72 static const struct ksz_mib_names ksz88xx_mib_names[] = {
73 { 0x00, "rx" },
74 { 0x01, "rx_hi" },
75 { 0x02, "rx_undersize" },
76 { 0x03, "rx_fragments" },
77 { 0x04, "rx_oversize" },
78 { 0x05, "rx_jabbers" },
79 { 0x06, "rx_symbol_err" },
80 { 0x07, "rx_crc_err" },
81 { 0x08, "rx_align_err" },
82 { 0x09, "rx_mac_ctrl" },
83 { 0x0a, "rx_pause" },
84 { 0x0b, "rx_bcast" },
85 { 0x0c, "rx_mcast" },
86 { 0x0d, "rx_ucast" },
87 { 0x0e, "rx_64_or_less" },
88 { 0x0f, "rx_65_127" },
89 { 0x10, "rx_128_255" },
90 { 0x11, "rx_256_511" },
91 { 0x12, "rx_512_1023" },
92 { 0x13, "rx_1024_1522" },
93 { 0x14, "tx" },
94 { 0x15, "tx_hi" },
95 { 0x16, "tx_late_col" },
96 { 0x17, "tx_pause" },
97 { 0x18, "tx_bcast" },
98 { 0x19, "tx_mcast" },
99 { 0x1a, "tx_ucast" },
100 { 0x1b, "tx_deferred" },
101 { 0x1c, "tx_total_col" },
102 { 0x1d, "tx_exc_col" },
103 { 0x1e, "tx_single_col" },
104 { 0x1f, "tx_mult_col" },
105 { 0x100, "rx_discards" },
106 { 0x101, "tx_discards" },
107 };
108
109 static const struct ksz_mib_names ksz9477_mib_names[] = {
110 { 0x00, "rx_hi" },
111 { 0x01, "rx_undersize" },
112 { 0x02, "rx_fragments" },
113 { 0x03, "rx_oversize" },
114 { 0x04, "rx_jabbers" },
115 { 0x05, "rx_symbol_err" },
116 { 0x06, "rx_crc_err" },
117 { 0x07, "rx_align_err" },
118 { 0x08, "rx_mac_ctrl" },
119 { 0x09, "rx_pause" },
120 { 0x0A, "rx_bcast" },
121 { 0x0B, "rx_mcast" },
122 { 0x0C, "rx_ucast" },
123 { 0x0D, "rx_64_or_less" },
124 { 0x0E, "rx_65_127" },
125 { 0x0F, "rx_128_255" },
126 { 0x10, "rx_256_511" },
127 { 0x11, "rx_512_1023" },
128 { 0x12, "rx_1024_1522" },
129 { 0x13, "rx_1523_2000" },
130 { 0x14, "rx_2001" },
131 { 0x15, "tx_hi" },
132 { 0x16, "tx_late_col" },
133 { 0x17, "tx_pause" },
134 { 0x18, "tx_bcast" },
135 { 0x19, "tx_mcast" },
136 { 0x1A, "tx_ucast" },
137 { 0x1B, "tx_deferred" },
138 { 0x1C, "tx_total_col" },
139 { 0x1D, "tx_exc_col" },
140 { 0x1E, "tx_single_col" },
141 { 0x1F, "tx_mult_col" },
142 { 0x80, "rx_total" },
143 { 0x81, "tx_total" },
144 { 0x82, "rx_discards" },
145 { 0x83, "tx_discards" },
146 };
147
148 static const struct ksz_dev_ops ksz8_dev_ops = {
149 .setup = ksz8_setup,
150 .get_port_addr = ksz8_get_port_addr,
151 .cfg_port_member = ksz8_cfg_port_member,
152 .flush_dyn_mac_table = ksz8_flush_dyn_mac_table,
153 .port_setup = ksz8_port_setup,
154 .r_phy = ksz8_r_phy,
155 .w_phy = ksz8_w_phy,
156 .r_mib_cnt = ksz8_r_mib_cnt,
157 .r_mib_pkt = ksz8_r_mib_pkt,
158 .freeze_mib = ksz8_freeze_mib,
159 .port_init_cnt = ksz8_port_init_cnt,
160 .fdb_dump = ksz8_fdb_dump,
161 .mdb_add = ksz8_mdb_add,
162 .mdb_del = ksz8_mdb_del,
163 .vlan_filtering = ksz8_port_vlan_filtering,
164 .vlan_add = ksz8_port_vlan_add,
165 .vlan_del = ksz8_port_vlan_del,
166 .mirror_add = ksz8_port_mirror_add,
167 .mirror_del = ksz8_port_mirror_del,
168 .get_caps = ksz8_get_caps,
169 .config_cpu_port = ksz8_config_cpu_port,
170 .enable_stp_addr = ksz8_enable_stp_addr,
171 .reset = ksz8_reset_switch,
172 .init = ksz8_switch_init,
173 .exit = ksz8_switch_exit,
174 };
175
176 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
177 unsigned int mode,
178 phy_interface_t interface,
179 struct phy_device *phydev, int speed,
180 int duplex, bool tx_pause,
181 bool rx_pause);
182
183 static const struct ksz_dev_ops ksz9477_dev_ops = {
184 .setup = ksz9477_setup,
185 .get_port_addr = ksz9477_get_port_addr,
186 .cfg_port_member = ksz9477_cfg_port_member,
187 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
188 .port_setup = ksz9477_port_setup,
189 .set_ageing_time = ksz9477_set_ageing_time,
190 .r_phy = ksz9477_r_phy,
191 .w_phy = ksz9477_w_phy,
192 .r_mib_cnt = ksz9477_r_mib_cnt,
193 .r_mib_pkt = ksz9477_r_mib_pkt,
194 .r_mib_stat64 = ksz_r_mib_stats64,
195 .freeze_mib = ksz9477_freeze_mib,
196 .port_init_cnt = ksz9477_port_init_cnt,
197 .vlan_filtering = ksz9477_port_vlan_filtering,
198 .vlan_add = ksz9477_port_vlan_add,
199 .vlan_del = ksz9477_port_vlan_del,
200 .mirror_add = ksz9477_port_mirror_add,
201 .mirror_del = ksz9477_port_mirror_del,
202 .get_caps = ksz9477_get_caps,
203 .fdb_dump = ksz9477_fdb_dump,
204 .fdb_add = ksz9477_fdb_add,
205 .fdb_del = ksz9477_fdb_del,
206 .mdb_add = ksz9477_mdb_add,
207 .mdb_del = ksz9477_mdb_del,
208 .change_mtu = ksz9477_change_mtu,
209 .max_mtu = ksz9477_max_mtu,
210 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
211 .config_cpu_port = ksz9477_config_cpu_port,
212 .enable_stp_addr = ksz9477_enable_stp_addr,
213 .reset = ksz9477_reset_switch,
214 .init = ksz9477_switch_init,
215 .exit = ksz9477_switch_exit,
216 };
217
218 static const struct ksz_dev_ops lan937x_dev_ops = {
219 .setup = lan937x_setup,
220 .teardown = lan937x_teardown,
221 .get_port_addr = ksz9477_get_port_addr,
222 .cfg_port_member = ksz9477_cfg_port_member,
223 .flush_dyn_mac_table = ksz9477_flush_dyn_mac_table,
224 .port_setup = lan937x_port_setup,
225 .set_ageing_time = lan937x_set_ageing_time,
226 .r_phy = lan937x_r_phy,
227 .w_phy = lan937x_w_phy,
228 .r_mib_cnt = ksz9477_r_mib_cnt,
229 .r_mib_pkt = ksz9477_r_mib_pkt,
230 .r_mib_stat64 = ksz_r_mib_stats64,
231 .freeze_mib = ksz9477_freeze_mib,
232 .port_init_cnt = ksz9477_port_init_cnt,
233 .vlan_filtering = ksz9477_port_vlan_filtering,
234 .vlan_add = ksz9477_port_vlan_add,
235 .vlan_del = ksz9477_port_vlan_del,
236 .mirror_add = ksz9477_port_mirror_add,
237 .mirror_del = ksz9477_port_mirror_del,
238 .get_caps = lan937x_phylink_get_caps,
239 .setup_rgmii_delay = lan937x_setup_rgmii_delay,
240 .fdb_dump = ksz9477_fdb_dump,
241 .fdb_add = ksz9477_fdb_add,
242 .fdb_del = ksz9477_fdb_del,
243 .mdb_add = ksz9477_mdb_add,
244 .mdb_del = ksz9477_mdb_del,
245 .change_mtu = lan937x_change_mtu,
246 .max_mtu = ksz9477_max_mtu,
247 .phylink_mac_link_up = ksz9477_phylink_mac_link_up,
248 .config_cpu_port = lan937x_config_cpu_port,
249 .enable_stp_addr = ksz9477_enable_stp_addr,
250 .reset = lan937x_reset_switch,
251 .init = lan937x_switch_init,
252 .exit = lan937x_switch_exit,
253 };
254
255 static const u16 ksz8795_regs[] = {
256 [REG_IND_CTRL_0] = 0x6E,
257 [REG_IND_DATA_8] = 0x70,
258 [REG_IND_DATA_CHECK] = 0x72,
259 [REG_IND_DATA_HI] = 0x71,
260 [REG_IND_DATA_LO] = 0x75,
261 [REG_IND_MIB_CHECK] = 0x74,
262 [REG_IND_BYTE] = 0xA0,
263 [P_FORCE_CTRL] = 0x0C,
264 [P_LINK_STATUS] = 0x0E,
265 [P_LOCAL_CTRL] = 0x07,
266 [P_NEG_RESTART_CTRL] = 0x0D,
267 [P_REMOTE_STATUS] = 0x08,
268 [P_SPEED_STATUS] = 0x09,
269 [S_TAIL_TAG_CTRL] = 0x0C,
270 [P_STP_CTRL] = 0x02,
271 [S_START_CTRL] = 0x01,
272 [S_BROADCAST_CTRL] = 0x06,
273 [S_MULTICAST_CTRL] = 0x04,
274 [P_XMII_CTRL_0] = 0x06,
275 [P_XMII_CTRL_1] = 0x06,
276 };
277
278 static const u32 ksz8795_masks[] = {
279 [PORT_802_1P_REMAPPING] = BIT(7),
280 [SW_TAIL_TAG_ENABLE] = BIT(1),
281 [MIB_COUNTER_OVERFLOW] = BIT(6),
282 [MIB_COUNTER_VALID] = BIT(5),
283 [VLAN_TABLE_FID] = GENMASK(6, 0),
284 [VLAN_TABLE_MEMBERSHIP] = GENMASK(11, 7),
285 [VLAN_TABLE_VALID] = BIT(12),
286 [STATIC_MAC_TABLE_VALID] = BIT(21),
287 [STATIC_MAC_TABLE_USE_FID] = BIT(23),
288 [STATIC_MAC_TABLE_FID] = GENMASK(30, 24),
289 [STATIC_MAC_TABLE_OVERRIDE] = BIT(22),
290 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(20, 16),
291 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(6, 0),
292 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(7),
293 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
294 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 29),
295 [DYNAMIC_MAC_TABLE_FID] = GENMASK(22, 16),
296 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(26, 24),
297 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(28, 27),
298 [P_MII_TX_FLOW_CTRL] = BIT(5),
299 [P_MII_RX_FLOW_CTRL] = BIT(5),
300 };
301
302 static const u8 ksz8795_xmii_ctrl0[] = {
303 [P_MII_100MBIT] = 0,
304 [P_MII_10MBIT] = 1,
305 [P_MII_FULL_DUPLEX] = 0,
306 [P_MII_HALF_DUPLEX] = 1,
307 };
308
309 static const u8 ksz8795_xmii_ctrl1[] = {
310 [P_RGMII_SEL] = 3,
311 [P_GMII_SEL] = 2,
312 [P_RMII_SEL] = 1,
313 [P_MII_SEL] = 0,
314 [P_GMII_1GBIT] = 1,
315 [P_GMII_NOT_1GBIT] = 0,
316 };
317
318 static const u8 ksz8795_shifts[] = {
319 [VLAN_TABLE_MEMBERSHIP_S] = 7,
320 [VLAN_TABLE] = 16,
321 [STATIC_MAC_FWD_PORTS] = 16,
322 [STATIC_MAC_FID] = 24,
323 [DYNAMIC_MAC_ENTRIES_H] = 3,
324 [DYNAMIC_MAC_ENTRIES] = 29,
325 [DYNAMIC_MAC_FID] = 16,
326 [DYNAMIC_MAC_TIMESTAMP] = 27,
327 [DYNAMIC_MAC_SRC_PORT] = 24,
328 };
329
330 static const u16 ksz8863_regs[] = {
331 [REG_IND_CTRL_0] = 0x79,
332 [REG_IND_DATA_8] = 0x7B,
333 [REG_IND_DATA_CHECK] = 0x7B,
334 [REG_IND_DATA_HI] = 0x7C,
335 [REG_IND_DATA_LO] = 0x80,
336 [REG_IND_MIB_CHECK] = 0x80,
337 [P_FORCE_CTRL] = 0x0C,
338 [P_LINK_STATUS] = 0x0E,
339 [P_LOCAL_CTRL] = 0x0C,
340 [P_NEG_RESTART_CTRL] = 0x0D,
341 [P_REMOTE_STATUS] = 0x0E,
342 [P_SPEED_STATUS] = 0x0F,
343 [S_TAIL_TAG_CTRL] = 0x03,
344 [P_STP_CTRL] = 0x02,
345 [S_START_CTRL] = 0x01,
346 [S_BROADCAST_CTRL] = 0x06,
347 [S_MULTICAST_CTRL] = 0x04,
348 };
349
350 static const u32 ksz8863_masks[] = {
351 [PORT_802_1P_REMAPPING] = BIT(3),
352 [SW_TAIL_TAG_ENABLE] = BIT(6),
353 [MIB_COUNTER_OVERFLOW] = BIT(7),
354 [MIB_COUNTER_VALID] = BIT(6),
355 [VLAN_TABLE_FID] = GENMASK(15, 12),
356 [VLAN_TABLE_MEMBERSHIP] = GENMASK(18, 16),
357 [VLAN_TABLE_VALID] = BIT(19),
358 [STATIC_MAC_TABLE_VALID] = BIT(19),
359 [STATIC_MAC_TABLE_USE_FID] = BIT(21),
360 [STATIC_MAC_TABLE_FID] = GENMASK(25, 22),
361 [STATIC_MAC_TABLE_OVERRIDE] = BIT(20),
362 [STATIC_MAC_TABLE_FWD_PORTS] = GENMASK(18, 16),
363 [DYNAMIC_MAC_TABLE_ENTRIES_H] = GENMASK(1, 0),
364 [DYNAMIC_MAC_TABLE_MAC_EMPTY] = BIT(2),
365 [DYNAMIC_MAC_TABLE_NOT_READY] = BIT(7),
366 [DYNAMIC_MAC_TABLE_ENTRIES] = GENMASK(31, 24),
367 [DYNAMIC_MAC_TABLE_FID] = GENMASK(19, 16),
368 [DYNAMIC_MAC_TABLE_SRC_PORT] = GENMASK(21, 20),
369 [DYNAMIC_MAC_TABLE_TIMESTAMP] = GENMASK(23, 22),
370 };
371
372 static u8 ksz8863_shifts[] = {
373 [VLAN_TABLE_MEMBERSHIP_S] = 16,
374 [STATIC_MAC_FWD_PORTS] = 16,
375 [STATIC_MAC_FID] = 22,
376 [DYNAMIC_MAC_ENTRIES_H] = 8,
377 [DYNAMIC_MAC_ENTRIES] = 24,
378 [DYNAMIC_MAC_FID] = 16,
379 [DYNAMIC_MAC_TIMESTAMP] = 22,
380 [DYNAMIC_MAC_SRC_PORT] = 20,
381 };
382
383 static const u16 ksz9477_regs[] = {
384 [P_STP_CTRL] = 0x0B04,
385 [S_START_CTRL] = 0x0300,
386 [S_BROADCAST_CTRL] = 0x0332,
387 [S_MULTICAST_CTRL] = 0x0331,
388 [P_XMII_CTRL_0] = 0x0300,
389 [P_XMII_CTRL_1] = 0x0301,
390 };
391
392 static const u32 ksz9477_masks[] = {
393 [ALU_STAT_WRITE] = 0,
394 [ALU_STAT_READ] = 1,
395 [P_MII_TX_FLOW_CTRL] = BIT(5),
396 [P_MII_RX_FLOW_CTRL] = BIT(3),
397 };
398
399 static const u8 ksz9477_shifts[] = {
400 [ALU_STAT_INDEX] = 16,
401 };
402
403 static const u8 ksz9477_xmii_ctrl0[] = {
404 [P_MII_100MBIT] = 1,
405 [P_MII_10MBIT] = 0,
406 [P_MII_FULL_DUPLEX] = 1,
407 [P_MII_HALF_DUPLEX] = 0,
408 };
409
410 static const u8 ksz9477_xmii_ctrl1[] = {
411 [P_RGMII_SEL] = 0,
412 [P_RMII_SEL] = 1,
413 [P_GMII_SEL] = 2,
414 [P_MII_SEL] = 3,
415 [P_GMII_1GBIT] = 0,
416 [P_GMII_NOT_1GBIT] = 1,
417 };
418
419 static const u32 lan937x_masks[] = {
420 [ALU_STAT_WRITE] = 1,
421 [ALU_STAT_READ] = 2,
422 [P_MII_TX_FLOW_CTRL] = BIT(5),
423 [P_MII_RX_FLOW_CTRL] = BIT(3),
424 };
425
426 static const u8 lan937x_shifts[] = {
427 [ALU_STAT_INDEX] = 8,
428 };
429
430 static const struct regmap_range ksz8563_valid_regs[] = {
431 regmap_reg_range(0x0000, 0x0003),
432 regmap_reg_range(0x0006, 0x0006),
433 regmap_reg_range(0x000f, 0x001f),
434 regmap_reg_range(0x0100, 0x0100),
435 regmap_reg_range(0x0104, 0x0107),
436 regmap_reg_range(0x010d, 0x010d),
437 regmap_reg_range(0x0110, 0x0113),
438 regmap_reg_range(0x0120, 0x012b),
439 regmap_reg_range(0x0201, 0x0201),
440 regmap_reg_range(0x0210, 0x0213),
441 regmap_reg_range(0x0300, 0x0300),
442 regmap_reg_range(0x0302, 0x031b),
443 regmap_reg_range(0x0320, 0x032b),
444 regmap_reg_range(0x0330, 0x0336),
445 regmap_reg_range(0x0338, 0x033e),
446 regmap_reg_range(0x0340, 0x035f),
447 regmap_reg_range(0x0370, 0x0370),
448 regmap_reg_range(0x0378, 0x0378),
449 regmap_reg_range(0x037c, 0x037d),
450 regmap_reg_range(0x0390, 0x0393),
451 regmap_reg_range(0x0400, 0x040e),
452 regmap_reg_range(0x0410, 0x042f),
453 regmap_reg_range(0x0500, 0x0519),
454 regmap_reg_range(0x0520, 0x054b),
455 regmap_reg_range(0x0550, 0x05b3),
456
457 /* port 1 */
458 regmap_reg_range(0x1000, 0x1001),
459 regmap_reg_range(0x1004, 0x100b),
460 regmap_reg_range(0x1013, 0x1013),
461 regmap_reg_range(0x1017, 0x1017),
462 regmap_reg_range(0x101b, 0x101b),
463 regmap_reg_range(0x101f, 0x1021),
464 regmap_reg_range(0x1030, 0x1030),
465 regmap_reg_range(0x1100, 0x1111),
466 regmap_reg_range(0x111a, 0x111d),
467 regmap_reg_range(0x1122, 0x1127),
468 regmap_reg_range(0x112a, 0x112b),
469 regmap_reg_range(0x1136, 0x1139),
470 regmap_reg_range(0x113e, 0x113f),
471 regmap_reg_range(0x1400, 0x1401),
472 regmap_reg_range(0x1403, 0x1403),
473 regmap_reg_range(0x1410, 0x1417),
474 regmap_reg_range(0x1420, 0x1423),
475 regmap_reg_range(0x1500, 0x1507),
476 regmap_reg_range(0x1600, 0x1612),
477 regmap_reg_range(0x1800, 0x180f),
478 regmap_reg_range(0x1900, 0x1907),
479 regmap_reg_range(0x1914, 0x191b),
480 regmap_reg_range(0x1a00, 0x1a03),
481 regmap_reg_range(0x1a04, 0x1a08),
482 regmap_reg_range(0x1b00, 0x1b01),
483 regmap_reg_range(0x1b04, 0x1b04),
484 regmap_reg_range(0x1c00, 0x1c05),
485 regmap_reg_range(0x1c08, 0x1c1b),
486
487 /* port 2 */
488 regmap_reg_range(0x2000, 0x2001),
489 regmap_reg_range(0x2004, 0x200b),
490 regmap_reg_range(0x2013, 0x2013),
491 regmap_reg_range(0x2017, 0x2017),
492 regmap_reg_range(0x201b, 0x201b),
493 regmap_reg_range(0x201f, 0x2021),
494 regmap_reg_range(0x2030, 0x2030),
495 regmap_reg_range(0x2100, 0x2111),
496 regmap_reg_range(0x211a, 0x211d),
497 regmap_reg_range(0x2122, 0x2127),
498 regmap_reg_range(0x212a, 0x212b),
499 regmap_reg_range(0x2136, 0x2139),
500 regmap_reg_range(0x213e, 0x213f),
501 regmap_reg_range(0x2400, 0x2401),
502 regmap_reg_range(0x2403, 0x2403),
503 regmap_reg_range(0x2410, 0x2417),
504 regmap_reg_range(0x2420, 0x2423),
505 regmap_reg_range(0x2500, 0x2507),
506 regmap_reg_range(0x2600, 0x2612),
507 regmap_reg_range(0x2800, 0x280f),
508 regmap_reg_range(0x2900, 0x2907),
509 regmap_reg_range(0x2914, 0x291b),
510 regmap_reg_range(0x2a00, 0x2a03),
511 regmap_reg_range(0x2a04, 0x2a08),
512 regmap_reg_range(0x2b00, 0x2b01),
513 regmap_reg_range(0x2b04, 0x2b04),
514 regmap_reg_range(0x2c00, 0x2c05),
515 regmap_reg_range(0x2c08, 0x2c1b),
516
517 /* port 3 */
518 regmap_reg_range(0x3000, 0x3001),
519 regmap_reg_range(0x3004, 0x300b),
520 regmap_reg_range(0x3013, 0x3013),
521 regmap_reg_range(0x3017, 0x3017),
522 regmap_reg_range(0x301b, 0x301b),
523 regmap_reg_range(0x301f, 0x3021),
524 regmap_reg_range(0x3030, 0x3030),
525 regmap_reg_range(0x3300, 0x3301),
526 regmap_reg_range(0x3303, 0x3303),
527 regmap_reg_range(0x3400, 0x3401),
528 regmap_reg_range(0x3403, 0x3403),
529 regmap_reg_range(0x3410, 0x3417),
530 regmap_reg_range(0x3420, 0x3423),
531 regmap_reg_range(0x3500, 0x3507),
532 regmap_reg_range(0x3600, 0x3612),
533 regmap_reg_range(0x3800, 0x380f),
534 regmap_reg_range(0x3900, 0x3907),
535 regmap_reg_range(0x3914, 0x391b),
536 regmap_reg_range(0x3a00, 0x3a03),
537 regmap_reg_range(0x3a04, 0x3a08),
538 regmap_reg_range(0x3b00, 0x3b01),
539 regmap_reg_range(0x3b04, 0x3b04),
540 regmap_reg_range(0x3c00, 0x3c05),
541 regmap_reg_range(0x3c08, 0x3c1b),
542 };
543
544 static const struct regmap_access_table ksz8563_register_set = {
545 .yes_ranges = ksz8563_valid_regs,
546 .n_yes_ranges = ARRAY_SIZE(ksz8563_valid_regs),
547 };
548
549 static const struct regmap_range ksz9477_valid_regs[] = {
550 regmap_reg_range(0x0000, 0x0003),
551 regmap_reg_range(0x0006, 0x0006),
552 regmap_reg_range(0x0010, 0x001f),
553 regmap_reg_range(0x0100, 0x0100),
554 regmap_reg_range(0x0103, 0x0107),
555 regmap_reg_range(0x010d, 0x010d),
556 regmap_reg_range(0x0110, 0x0113),
557 regmap_reg_range(0x0120, 0x012b),
558 regmap_reg_range(0x0201, 0x0201),
559 regmap_reg_range(0x0210, 0x0213),
560 regmap_reg_range(0x0300, 0x0300),
561 regmap_reg_range(0x0302, 0x031b),
562 regmap_reg_range(0x0320, 0x032b),
563 regmap_reg_range(0x0330, 0x0336),
564 regmap_reg_range(0x0338, 0x033b),
565 regmap_reg_range(0x033e, 0x033e),
566 regmap_reg_range(0x0340, 0x035f),
567 regmap_reg_range(0x0370, 0x0370),
568 regmap_reg_range(0x0378, 0x0378),
569 regmap_reg_range(0x037c, 0x037d),
570 regmap_reg_range(0x0390, 0x0393),
571 regmap_reg_range(0x0400, 0x040e),
572 regmap_reg_range(0x0410, 0x042f),
573 regmap_reg_range(0x0444, 0x044b),
574 regmap_reg_range(0x0450, 0x046f),
575 regmap_reg_range(0x0500, 0x0519),
576 regmap_reg_range(0x0520, 0x054b),
577 regmap_reg_range(0x0550, 0x05b3),
578 regmap_reg_range(0x0604, 0x060b),
579 regmap_reg_range(0x0610, 0x0612),
580 regmap_reg_range(0x0614, 0x062c),
581 regmap_reg_range(0x0640, 0x0645),
582 regmap_reg_range(0x0648, 0x064d),
583
584 /* port 1 */
585 regmap_reg_range(0x1000, 0x1001),
586 regmap_reg_range(0x1013, 0x1013),
587 regmap_reg_range(0x1017, 0x1017),
588 regmap_reg_range(0x101b, 0x101b),
589 regmap_reg_range(0x101f, 0x1020),
590 regmap_reg_range(0x1030, 0x1030),
591 regmap_reg_range(0x1100, 0x1115),
592 regmap_reg_range(0x111a, 0x111f),
593 regmap_reg_range(0x1120, 0x112b),
594 regmap_reg_range(0x1134, 0x113b),
595 regmap_reg_range(0x113c, 0x113f),
596 regmap_reg_range(0x1400, 0x1401),
597 regmap_reg_range(0x1403, 0x1403),
598 regmap_reg_range(0x1410, 0x1417),
599 regmap_reg_range(0x1420, 0x1423),
600 regmap_reg_range(0x1500, 0x1507),
601 regmap_reg_range(0x1600, 0x1613),
602 regmap_reg_range(0x1800, 0x180f),
603 regmap_reg_range(0x1820, 0x1827),
604 regmap_reg_range(0x1830, 0x1837),
605 regmap_reg_range(0x1840, 0x184b),
606 regmap_reg_range(0x1900, 0x1907),
607 regmap_reg_range(0x1914, 0x191b),
608 regmap_reg_range(0x1920, 0x1920),
609 regmap_reg_range(0x1923, 0x1927),
610 regmap_reg_range(0x1a00, 0x1a03),
611 regmap_reg_range(0x1a04, 0x1a07),
612 regmap_reg_range(0x1b00, 0x1b01),
613 regmap_reg_range(0x1b04, 0x1b04),
614 regmap_reg_range(0x1c00, 0x1c05),
615 regmap_reg_range(0x1c08, 0x1c1b),
616
617 /* port 2 */
618 regmap_reg_range(0x2000, 0x2001),
619 regmap_reg_range(0x2013, 0x2013),
620 regmap_reg_range(0x2017, 0x2017),
621 regmap_reg_range(0x201b, 0x201b),
622 regmap_reg_range(0x201f, 0x2020),
623 regmap_reg_range(0x2030, 0x2030),
624 regmap_reg_range(0x2100, 0x2115),
625 regmap_reg_range(0x211a, 0x211f),
626 regmap_reg_range(0x2120, 0x212b),
627 regmap_reg_range(0x2134, 0x213b),
628 regmap_reg_range(0x213c, 0x213f),
629 regmap_reg_range(0x2400, 0x2401),
630 regmap_reg_range(0x2403, 0x2403),
631 regmap_reg_range(0x2410, 0x2417),
632 regmap_reg_range(0x2420, 0x2423),
633 regmap_reg_range(0x2500, 0x2507),
634 regmap_reg_range(0x2600, 0x2613),
635 regmap_reg_range(0x2800, 0x280f),
636 regmap_reg_range(0x2820, 0x2827),
637 regmap_reg_range(0x2830, 0x2837),
638 regmap_reg_range(0x2840, 0x284b),
639 regmap_reg_range(0x2900, 0x2907),
640 regmap_reg_range(0x2914, 0x291b),
641 regmap_reg_range(0x2920, 0x2920),
642 regmap_reg_range(0x2923, 0x2927),
643 regmap_reg_range(0x2a00, 0x2a03),
644 regmap_reg_range(0x2a04, 0x2a07),
645 regmap_reg_range(0x2b00, 0x2b01),
646 regmap_reg_range(0x2b04, 0x2b04),
647 regmap_reg_range(0x2c00, 0x2c05),
648 regmap_reg_range(0x2c08, 0x2c1b),
649
650 /* port 3 */
651 regmap_reg_range(0x3000, 0x3001),
652 regmap_reg_range(0x3013, 0x3013),
653 regmap_reg_range(0x3017, 0x3017),
654 regmap_reg_range(0x301b, 0x301b),
655 regmap_reg_range(0x301f, 0x3020),
656 regmap_reg_range(0x3030, 0x3030),
657 regmap_reg_range(0x3100, 0x3115),
658 regmap_reg_range(0x311a, 0x311f),
659 regmap_reg_range(0x3120, 0x312b),
660 regmap_reg_range(0x3134, 0x313b),
661 regmap_reg_range(0x313c, 0x313f),
662 regmap_reg_range(0x3400, 0x3401),
663 regmap_reg_range(0x3403, 0x3403),
664 regmap_reg_range(0x3410, 0x3417),
665 regmap_reg_range(0x3420, 0x3423),
666 regmap_reg_range(0x3500, 0x3507),
667 regmap_reg_range(0x3600, 0x3613),
668 regmap_reg_range(0x3800, 0x380f),
669 regmap_reg_range(0x3820, 0x3827),
670 regmap_reg_range(0x3830, 0x3837),
671 regmap_reg_range(0x3840, 0x384b),
672 regmap_reg_range(0x3900, 0x3907),
673 regmap_reg_range(0x3914, 0x391b),
674 regmap_reg_range(0x3920, 0x3920),
675 regmap_reg_range(0x3923, 0x3927),
676 regmap_reg_range(0x3a00, 0x3a03),
677 regmap_reg_range(0x3a04, 0x3a07),
678 regmap_reg_range(0x3b00, 0x3b01),
679 regmap_reg_range(0x3b04, 0x3b04),
680 regmap_reg_range(0x3c00, 0x3c05),
681 regmap_reg_range(0x3c08, 0x3c1b),
682
683 /* port 4 */
684 regmap_reg_range(0x4000, 0x4001),
685 regmap_reg_range(0x4013, 0x4013),
686 regmap_reg_range(0x4017, 0x4017),
687 regmap_reg_range(0x401b, 0x401b),
688 regmap_reg_range(0x401f, 0x4020),
689 regmap_reg_range(0x4030, 0x4030),
690 regmap_reg_range(0x4100, 0x4115),
691 regmap_reg_range(0x411a, 0x411f),
692 regmap_reg_range(0x4120, 0x412b),
693 regmap_reg_range(0x4134, 0x413b),
694 regmap_reg_range(0x413c, 0x413f),
695 regmap_reg_range(0x4400, 0x4401),
696 regmap_reg_range(0x4403, 0x4403),
697 regmap_reg_range(0x4410, 0x4417),
698 regmap_reg_range(0x4420, 0x4423),
699 regmap_reg_range(0x4500, 0x4507),
700 regmap_reg_range(0x4600, 0x4613),
701 regmap_reg_range(0x4800, 0x480f),
702 regmap_reg_range(0x4820, 0x4827),
703 regmap_reg_range(0x4830, 0x4837),
704 regmap_reg_range(0x4840, 0x484b),
705 regmap_reg_range(0x4900, 0x4907),
706 regmap_reg_range(0x4914, 0x491b),
707 regmap_reg_range(0x4920, 0x4920),
708 regmap_reg_range(0x4923, 0x4927),
709 regmap_reg_range(0x4a00, 0x4a03),
710 regmap_reg_range(0x4a04, 0x4a07),
711 regmap_reg_range(0x4b00, 0x4b01),
712 regmap_reg_range(0x4b04, 0x4b04),
713 regmap_reg_range(0x4c00, 0x4c05),
714 regmap_reg_range(0x4c08, 0x4c1b),
715
716 /* port 5 */
717 regmap_reg_range(0x5000, 0x5001),
718 regmap_reg_range(0x5013, 0x5013),
719 regmap_reg_range(0x5017, 0x5017),
720 regmap_reg_range(0x501b, 0x501b),
721 regmap_reg_range(0x501f, 0x5020),
722 regmap_reg_range(0x5030, 0x5030),
723 regmap_reg_range(0x5100, 0x5115),
724 regmap_reg_range(0x511a, 0x511f),
725 regmap_reg_range(0x5120, 0x512b),
726 regmap_reg_range(0x5134, 0x513b),
727 regmap_reg_range(0x513c, 0x513f),
728 regmap_reg_range(0x5400, 0x5401),
729 regmap_reg_range(0x5403, 0x5403),
730 regmap_reg_range(0x5410, 0x5417),
731 regmap_reg_range(0x5420, 0x5423),
732 regmap_reg_range(0x5500, 0x5507),
733 regmap_reg_range(0x5600, 0x5613),
734 regmap_reg_range(0x5800, 0x580f),
735 regmap_reg_range(0x5820, 0x5827),
736 regmap_reg_range(0x5830, 0x5837),
737 regmap_reg_range(0x5840, 0x584b),
738 regmap_reg_range(0x5900, 0x5907),
739 regmap_reg_range(0x5914, 0x591b),
740 regmap_reg_range(0x5920, 0x5920),
741 regmap_reg_range(0x5923, 0x5927),
742 regmap_reg_range(0x5a00, 0x5a03),
743 regmap_reg_range(0x5a04, 0x5a07),
744 regmap_reg_range(0x5b00, 0x5b01),
745 regmap_reg_range(0x5b04, 0x5b04),
746 regmap_reg_range(0x5c00, 0x5c05),
747 regmap_reg_range(0x5c08, 0x5c1b),
748
749 /* port 6 */
750 regmap_reg_range(0x6000, 0x6001),
751 regmap_reg_range(0x6013, 0x6013),
752 regmap_reg_range(0x6017, 0x6017),
753 regmap_reg_range(0x601b, 0x601b),
754 regmap_reg_range(0x601f, 0x6020),
755 regmap_reg_range(0x6030, 0x6030),
756 regmap_reg_range(0x6300, 0x6301),
757 regmap_reg_range(0x6400, 0x6401),
758 regmap_reg_range(0x6403, 0x6403),
759 regmap_reg_range(0x6410, 0x6417),
760 regmap_reg_range(0x6420, 0x6423),
761 regmap_reg_range(0x6500, 0x6507),
762 regmap_reg_range(0x6600, 0x6613),
763 regmap_reg_range(0x6800, 0x680f),
764 regmap_reg_range(0x6820, 0x6827),
765 regmap_reg_range(0x6830, 0x6837),
766 regmap_reg_range(0x6840, 0x684b),
767 regmap_reg_range(0x6900, 0x6907),
768 regmap_reg_range(0x6914, 0x691b),
769 regmap_reg_range(0x6920, 0x6920),
770 regmap_reg_range(0x6923, 0x6927),
771 regmap_reg_range(0x6a00, 0x6a03),
772 regmap_reg_range(0x6a04, 0x6a07),
773 regmap_reg_range(0x6b00, 0x6b01),
774 regmap_reg_range(0x6b04, 0x6b04),
775 regmap_reg_range(0x6c00, 0x6c05),
776 regmap_reg_range(0x6c08, 0x6c1b),
777
778 /* port 7 */
779 regmap_reg_range(0x7000, 0x7001),
780 regmap_reg_range(0x7013, 0x7013),
781 regmap_reg_range(0x7017, 0x7017),
782 regmap_reg_range(0x701b, 0x701b),
783 regmap_reg_range(0x701f, 0x7020),
784 regmap_reg_range(0x7030, 0x7030),
785 regmap_reg_range(0x7200, 0x7203),
786 regmap_reg_range(0x7206, 0x7207),
787 regmap_reg_range(0x7300, 0x7301),
788 regmap_reg_range(0x7400, 0x7401),
789 regmap_reg_range(0x7403, 0x7403),
790 regmap_reg_range(0x7410, 0x7417),
791 regmap_reg_range(0x7420, 0x7423),
792 regmap_reg_range(0x7500, 0x7507),
793 regmap_reg_range(0x7600, 0x7613),
794 regmap_reg_range(0x7800, 0x780f),
795 regmap_reg_range(0x7820, 0x7827),
796 regmap_reg_range(0x7830, 0x7837),
797 regmap_reg_range(0x7840, 0x784b),
798 regmap_reg_range(0x7900, 0x7907),
799 regmap_reg_range(0x7914, 0x791b),
800 regmap_reg_range(0x7920, 0x7920),
801 regmap_reg_range(0x7923, 0x7927),
802 regmap_reg_range(0x7a00, 0x7a03),
803 regmap_reg_range(0x7a04, 0x7a07),
804 regmap_reg_range(0x7b00, 0x7b01),
805 regmap_reg_range(0x7b04, 0x7b04),
806 regmap_reg_range(0x7c00, 0x7c05),
807 regmap_reg_range(0x7c08, 0x7c1b),
808 };
809
810 static const struct regmap_access_table ksz9477_register_set = {
811 .yes_ranges = ksz9477_valid_regs,
812 .n_yes_ranges = ARRAY_SIZE(ksz9477_valid_regs),
813 };
814
815 static const struct regmap_range ksz9896_valid_regs[] = {
816 regmap_reg_range(0x0000, 0x0003),
817 regmap_reg_range(0x0006, 0x0006),
818 regmap_reg_range(0x0010, 0x001f),
819 regmap_reg_range(0x0100, 0x0100),
820 regmap_reg_range(0x0103, 0x0107),
821 regmap_reg_range(0x010d, 0x010d),
822 regmap_reg_range(0x0110, 0x0113),
823 regmap_reg_range(0x0120, 0x0127),
824 regmap_reg_range(0x0201, 0x0201),
825 regmap_reg_range(0x0210, 0x0213),
826 regmap_reg_range(0x0300, 0x0300),
827 regmap_reg_range(0x0302, 0x030b),
828 regmap_reg_range(0x0310, 0x031b),
829 regmap_reg_range(0x0320, 0x032b),
830 regmap_reg_range(0x0330, 0x0336),
831 regmap_reg_range(0x0338, 0x033b),
832 regmap_reg_range(0x033e, 0x033e),
833 regmap_reg_range(0x0340, 0x035f),
834 regmap_reg_range(0x0370, 0x0370),
835 regmap_reg_range(0x0378, 0x0378),
836 regmap_reg_range(0x037c, 0x037d),
837 regmap_reg_range(0x0390, 0x0393),
838 regmap_reg_range(0x0400, 0x040e),
839 regmap_reg_range(0x0410, 0x042f),
840
841 /* port 1 */
842 regmap_reg_range(0x1000, 0x1001),
843 regmap_reg_range(0x1013, 0x1013),
844 regmap_reg_range(0x1017, 0x1017),
845 regmap_reg_range(0x101b, 0x101b),
846 regmap_reg_range(0x101f, 0x1020),
847 regmap_reg_range(0x1030, 0x1030),
848 regmap_reg_range(0x1100, 0x1115),
849 regmap_reg_range(0x111a, 0x111f),
850 regmap_reg_range(0x1122, 0x1127),
851 regmap_reg_range(0x112a, 0x112b),
852 regmap_reg_range(0x1136, 0x1139),
853 regmap_reg_range(0x113e, 0x113f),
854 regmap_reg_range(0x1400, 0x1401),
855 regmap_reg_range(0x1403, 0x1403),
856 regmap_reg_range(0x1410, 0x1417),
857 regmap_reg_range(0x1420, 0x1423),
858 regmap_reg_range(0x1500, 0x1507),
859 regmap_reg_range(0x1600, 0x1612),
860 regmap_reg_range(0x1800, 0x180f),
861 regmap_reg_range(0x1820, 0x1827),
862 regmap_reg_range(0x1830, 0x1837),
863 regmap_reg_range(0x1840, 0x184b),
864 regmap_reg_range(0x1900, 0x1907),
865 regmap_reg_range(0x1914, 0x1915),
866 regmap_reg_range(0x1a00, 0x1a03),
867 regmap_reg_range(0x1a04, 0x1a07),
868 regmap_reg_range(0x1b00, 0x1b01),
869 regmap_reg_range(0x1b04, 0x1b04),
870
871 /* port 2 */
872 regmap_reg_range(0x2000, 0x2001),
873 regmap_reg_range(0x2013, 0x2013),
874 regmap_reg_range(0x2017, 0x2017),
875 regmap_reg_range(0x201b, 0x201b),
876 regmap_reg_range(0x201f, 0x2020),
877 regmap_reg_range(0x2030, 0x2030),
878 regmap_reg_range(0x2100, 0x2115),
879 regmap_reg_range(0x211a, 0x211f),
880 regmap_reg_range(0x2122, 0x2127),
881 regmap_reg_range(0x212a, 0x212b),
882 regmap_reg_range(0x2136, 0x2139),
883 regmap_reg_range(0x213e, 0x213f),
884 regmap_reg_range(0x2400, 0x2401),
885 regmap_reg_range(0x2403, 0x2403),
886 regmap_reg_range(0x2410, 0x2417),
887 regmap_reg_range(0x2420, 0x2423),
888 regmap_reg_range(0x2500, 0x2507),
889 regmap_reg_range(0x2600, 0x2612),
890 regmap_reg_range(0x2800, 0x280f),
891 regmap_reg_range(0x2820, 0x2827),
892 regmap_reg_range(0x2830, 0x2837),
893 regmap_reg_range(0x2840, 0x284b),
894 regmap_reg_range(0x2900, 0x2907),
895 regmap_reg_range(0x2914, 0x2915),
896 regmap_reg_range(0x2a00, 0x2a03),
897 regmap_reg_range(0x2a04, 0x2a07),
898 regmap_reg_range(0x2b00, 0x2b01),
899 regmap_reg_range(0x2b04, 0x2b04),
900
901 /* port 3 */
902 regmap_reg_range(0x3000, 0x3001),
903 regmap_reg_range(0x3013, 0x3013),
904 regmap_reg_range(0x3017, 0x3017),
905 regmap_reg_range(0x301b, 0x301b),
906 regmap_reg_range(0x301f, 0x3020),
907 regmap_reg_range(0x3030, 0x3030),
908 regmap_reg_range(0x3100, 0x3115),
909 regmap_reg_range(0x311a, 0x311f),
910 regmap_reg_range(0x3122, 0x3127),
911 regmap_reg_range(0x312a, 0x312b),
912 regmap_reg_range(0x3136, 0x3139),
913 regmap_reg_range(0x313e, 0x313f),
914 regmap_reg_range(0x3400, 0x3401),
915 regmap_reg_range(0x3403, 0x3403),
916 regmap_reg_range(0x3410, 0x3417),
917 regmap_reg_range(0x3420, 0x3423),
918 regmap_reg_range(0x3500, 0x3507),
919 regmap_reg_range(0x3600, 0x3612),
920 regmap_reg_range(0x3800, 0x380f),
921 regmap_reg_range(0x3820, 0x3827),
922 regmap_reg_range(0x3830, 0x3837),
923 regmap_reg_range(0x3840, 0x384b),
924 regmap_reg_range(0x3900, 0x3907),
925 regmap_reg_range(0x3914, 0x3915),
926 regmap_reg_range(0x3a00, 0x3a03),
927 regmap_reg_range(0x3a04, 0x3a07),
928 regmap_reg_range(0x3b00, 0x3b01),
929 regmap_reg_range(0x3b04, 0x3b04),
930
931 /* port 4 */
932 regmap_reg_range(0x4000, 0x4001),
933 regmap_reg_range(0x4013, 0x4013),
934 regmap_reg_range(0x4017, 0x4017),
935 regmap_reg_range(0x401b, 0x401b),
936 regmap_reg_range(0x401f, 0x4020),
937 regmap_reg_range(0x4030, 0x4030),
938 regmap_reg_range(0x4100, 0x4115),
939 regmap_reg_range(0x411a, 0x411f),
940 regmap_reg_range(0x4122, 0x4127),
941 regmap_reg_range(0x412a, 0x412b),
942 regmap_reg_range(0x4136, 0x4139),
943 regmap_reg_range(0x413e, 0x413f),
944 regmap_reg_range(0x4400, 0x4401),
945 regmap_reg_range(0x4403, 0x4403),
946 regmap_reg_range(0x4410, 0x4417),
947 regmap_reg_range(0x4420, 0x4423),
948 regmap_reg_range(0x4500, 0x4507),
949 regmap_reg_range(0x4600, 0x4612),
950 regmap_reg_range(0x4800, 0x480f),
951 regmap_reg_range(0x4820, 0x4827),
952 regmap_reg_range(0x4830, 0x4837),
953 regmap_reg_range(0x4840, 0x484b),
954 regmap_reg_range(0x4900, 0x4907),
955 regmap_reg_range(0x4914, 0x4915),
956 regmap_reg_range(0x4a00, 0x4a03),
957 regmap_reg_range(0x4a04, 0x4a07),
958 regmap_reg_range(0x4b00, 0x4b01),
959 regmap_reg_range(0x4b04, 0x4b04),
960
961 /* port 5 */
962 regmap_reg_range(0x5000, 0x5001),
963 regmap_reg_range(0x5013, 0x5013),
964 regmap_reg_range(0x5017, 0x5017),
965 regmap_reg_range(0x501b, 0x501b),
966 regmap_reg_range(0x501f, 0x5020),
967 regmap_reg_range(0x5030, 0x5030),
968 regmap_reg_range(0x5100, 0x5115),
969 regmap_reg_range(0x511a, 0x511f),
970 regmap_reg_range(0x5122, 0x5127),
971 regmap_reg_range(0x512a, 0x512b),
972 regmap_reg_range(0x5136, 0x5139),
973 regmap_reg_range(0x513e, 0x513f),
974 regmap_reg_range(0x5400, 0x5401),
975 regmap_reg_range(0x5403, 0x5403),
976 regmap_reg_range(0x5410, 0x5417),
977 regmap_reg_range(0x5420, 0x5423),
978 regmap_reg_range(0x5500, 0x5507),
979 regmap_reg_range(0x5600, 0x5612),
980 regmap_reg_range(0x5800, 0x580f),
981 regmap_reg_range(0x5820, 0x5827),
982 regmap_reg_range(0x5830, 0x5837),
983 regmap_reg_range(0x5840, 0x584b),
984 regmap_reg_range(0x5900, 0x5907),
985 regmap_reg_range(0x5914, 0x5915),
986 regmap_reg_range(0x5a00, 0x5a03),
987 regmap_reg_range(0x5a04, 0x5a07),
988 regmap_reg_range(0x5b00, 0x5b01),
989 regmap_reg_range(0x5b04, 0x5b04),
990
991 /* port 6 */
992 regmap_reg_range(0x6000, 0x6001),
993 regmap_reg_range(0x6013, 0x6013),
994 regmap_reg_range(0x6017, 0x6017),
995 regmap_reg_range(0x601b, 0x601b),
996 regmap_reg_range(0x601f, 0x6020),
997 regmap_reg_range(0x6030, 0x6030),
998 regmap_reg_range(0x6100, 0x6115),
999 regmap_reg_range(0x611a, 0x611f),
1000 regmap_reg_range(0x6122, 0x6127),
1001 regmap_reg_range(0x612a, 0x612b),
1002 regmap_reg_range(0x6136, 0x6139),
1003 regmap_reg_range(0x613e, 0x613f),
1004 regmap_reg_range(0x6300, 0x6301),
1005 regmap_reg_range(0x6400, 0x6401),
1006 regmap_reg_range(0x6403, 0x6403),
1007 regmap_reg_range(0x6410, 0x6417),
1008 regmap_reg_range(0x6420, 0x6423),
1009 regmap_reg_range(0x6500, 0x6507),
1010 regmap_reg_range(0x6600, 0x6612),
1011 regmap_reg_range(0x6800, 0x680f),
1012 regmap_reg_range(0x6820, 0x6827),
1013 regmap_reg_range(0x6830, 0x6837),
1014 regmap_reg_range(0x6840, 0x684b),
1015 regmap_reg_range(0x6900, 0x6907),
1016 regmap_reg_range(0x6914, 0x6915),
1017 regmap_reg_range(0x6a00, 0x6a03),
1018 regmap_reg_range(0x6a04, 0x6a07),
1019 regmap_reg_range(0x6b00, 0x6b01),
1020 regmap_reg_range(0x6b04, 0x6b04),
1021 };
1022
1023 static const struct regmap_access_table ksz9896_register_set = {
1024 .yes_ranges = ksz9896_valid_regs,
1025 .n_yes_ranges = ARRAY_SIZE(ksz9896_valid_regs),
1026 };
1027
1028 const struct ksz_chip_data ksz_switch_chips[] = {
1029 [KSZ8563] = {
1030 .chip_id = KSZ8563_CHIP_ID,
1031 .dev_name = "KSZ8563",
1032 .num_vlans = 4096,
1033 .num_alus = 4096,
1034 .num_statics = 16,
1035 .cpu_ports = 0x07, /* can be configured as cpu port */
1036 .port_cnt = 3, /* total port count */
1037 .ops = &ksz9477_dev_ops,
1038 .mib_names = ksz9477_mib_names,
1039 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1040 .reg_mib_cnt = MIB_COUNTER_NUM,
1041 .regs = ksz9477_regs,
1042 .masks = ksz9477_masks,
1043 .shifts = ksz9477_shifts,
1044 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1045 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1046 .supports_mii = {false, false, true},
1047 .supports_rmii = {false, false, true},
1048 .supports_rgmii = {false, false, true},
1049 .internal_phy = {true, true, false},
1050 .gbit_capable = {false, false, true},
1051 .wr_table = &ksz8563_register_set,
1052 .rd_table = &ksz8563_register_set,
1053 },
1054
1055 [KSZ8795] = {
1056 .chip_id = KSZ8795_CHIP_ID,
1057 .dev_name = "KSZ8795",
1058 .num_vlans = 4096,
1059 .num_alus = 0,
1060 .num_statics = 8,
1061 .cpu_ports = 0x10, /* can be configured as cpu port */
1062 .port_cnt = 5, /* total cpu and user ports */
1063 .ops = &ksz8_dev_ops,
1064 .ksz87xx_eee_link_erratum = true,
1065 .mib_names = ksz9477_mib_names,
1066 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1067 .reg_mib_cnt = MIB_COUNTER_NUM,
1068 .regs = ksz8795_regs,
1069 .masks = ksz8795_masks,
1070 .shifts = ksz8795_shifts,
1071 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1072 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1073 .supports_mii = {false, false, false, false, true},
1074 .supports_rmii = {false, false, false, false, true},
1075 .supports_rgmii = {false, false, false, false, true},
1076 .internal_phy = {true, true, true, true, false},
1077 },
1078
1079 [KSZ8794] = {
1080 /* WARNING
1081 * =======
1082 * KSZ8794 is similar to KSZ8795, except the port map
1083 * contains a gap between external and CPU ports, the
1084 * port map is NOT continuous. The per-port register
1085 * map is shifted accordingly too, i.e. registers at
1086 * offset 0x40 are NOT used on KSZ8794 and they ARE
1087 * used on KSZ8795 for external port 3.
1088 * external cpu
1089 * KSZ8794 0,1,2 4
1090 * KSZ8795 0,1,2,3 4
1091 * KSZ8765 0,1,2,3 4
1092 * port_cnt is configured as 5, even though it is 4
1093 */
1094 .chip_id = KSZ8794_CHIP_ID,
1095 .dev_name = "KSZ8794",
1096 .num_vlans = 4096,
1097 .num_alus = 0,
1098 .num_statics = 8,
1099 .cpu_ports = 0x10, /* can be configured as cpu port */
1100 .port_cnt = 5, /* total cpu and user ports */
1101 .ops = &ksz8_dev_ops,
1102 .ksz87xx_eee_link_erratum = true,
1103 .mib_names = ksz9477_mib_names,
1104 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1105 .reg_mib_cnt = MIB_COUNTER_NUM,
1106 .regs = ksz8795_regs,
1107 .masks = ksz8795_masks,
1108 .shifts = ksz8795_shifts,
1109 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1110 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1111 .supports_mii = {false, false, false, false, true},
1112 .supports_rmii = {false, false, false, false, true},
1113 .supports_rgmii = {false, false, false, false, true},
1114 .internal_phy = {true, true, true, false, false},
1115 },
1116
1117 [KSZ8765] = {
1118 .chip_id = KSZ8765_CHIP_ID,
1119 .dev_name = "KSZ8765",
1120 .num_vlans = 4096,
1121 .num_alus = 0,
1122 .num_statics = 8,
1123 .cpu_ports = 0x10, /* can be configured as cpu port */
1124 .port_cnt = 5, /* total cpu and user ports */
1125 .ops = &ksz8_dev_ops,
1126 .ksz87xx_eee_link_erratum = true,
1127 .mib_names = ksz9477_mib_names,
1128 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1129 .reg_mib_cnt = MIB_COUNTER_NUM,
1130 .regs = ksz8795_regs,
1131 .masks = ksz8795_masks,
1132 .shifts = ksz8795_shifts,
1133 .xmii_ctrl0 = ksz8795_xmii_ctrl0,
1134 .xmii_ctrl1 = ksz8795_xmii_ctrl1,
1135 .supports_mii = {false, false, false, false, true},
1136 .supports_rmii = {false, false, false, false, true},
1137 .supports_rgmii = {false, false, false, false, true},
1138 .internal_phy = {true, true, true, true, false},
1139 },
1140
1141 [KSZ8830] = {
1142 .chip_id = KSZ8830_CHIP_ID,
1143 .dev_name = "KSZ8863/KSZ8873",
1144 .num_vlans = 16,
1145 .num_alus = 0,
1146 .num_statics = 8,
1147 .cpu_ports = 0x4, /* can be configured as cpu port */
1148 .port_cnt = 3,
1149 .ops = &ksz8_dev_ops,
1150 .mib_names = ksz88xx_mib_names,
1151 .mib_cnt = ARRAY_SIZE(ksz88xx_mib_names),
1152 .reg_mib_cnt = MIB_COUNTER_NUM,
1153 .regs = ksz8863_regs,
1154 .masks = ksz8863_masks,
1155 .shifts = ksz8863_shifts,
1156 .supports_mii = {false, false, true},
1157 .supports_rmii = {false, false, true},
1158 .internal_phy = {true, true, false},
1159 },
1160
1161 [KSZ9477] = {
1162 .chip_id = KSZ9477_CHIP_ID,
1163 .dev_name = "KSZ9477",
1164 .num_vlans = 4096,
1165 .num_alus = 4096,
1166 .num_statics = 16,
1167 .cpu_ports = 0x7F, /* can be configured as cpu port */
1168 .port_cnt = 7, /* total physical port count */
1169 .port_nirqs = 4,
1170 .ops = &ksz9477_dev_ops,
1171 .phy_errata_9477 = true,
1172 .mib_names = ksz9477_mib_names,
1173 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1174 .reg_mib_cnt = MIB_COUNTER_NUM,
1175 .regs = ksz9477_regs,
1176 .masks = ksz9477_masks,
1177 .shifts = ksz9477_shifts,
1178 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1179 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1180 .supports_mii = {false, false, false, false,
1181 false, true, false},
1182 .supports_rmii = {false, false, false, false,
1183 false, true, false},
1184 .supports_rgmii = {false, false, false, false,
1185 false, true, false},
1186 .internal_phy = {true, true, true, true,
1187 true, false, false},
1188 .gbit_capable = {true, true, true, true, true, true, true},
1189 .wr_table = &ksz9477_register_set,
1190 .rd_table = &ksz9477_register_set,
1191 },
1192
1193 [KSZ9896] = {
1194 .chip_id = KSZ9896_CHIP_ID,
1195 .dev_name = "KSZ9896",
1196 .num_vlans = 4096,
1197 .num_alus = 4096,
1198 .num_statics = 16,
1199 .cpu_ports = 0x3F, /* can be configured as cpu port */
1200 .port_cnt = 6, /* total physical port count */
1201 .port_nirqs = 2,
1202 .ops = &ksz9477_dev_ops,
1203 .phy_errata_9477 = true,
1204 .mib_names = ksz9477_mib_names,
1205 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1206 .reg_mib_cnt = MIB_COUNTER_NUM,
1207 .regs = ksz9477_regs,
1208 .masks = ksz9477_masks,
1209 .shifts = ksz9477_shifts,
1210 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1211 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1212 .supports_mii = {false, false, false, false,
1213 false, true},
1214 .supports_rmii = {false, false, false, false,
1215 false, true},
1216 .supports_rgmii = {false, false, false, false,
1217 false, true},
1218 .internal_phy = {true, true, true, true,
1219 true, false},
1220 .gbit_capable = {true, true, true, true, true, true},
1221 .wr_table = &ksz9896_register_set,
1222 .rd_table = &ksz9896_register_set,
1223 },
1224
1225 [KSZ9897] = {
1226 .chip_id = KSZ9897_CHIP_ID,
1227 .dev_name = "KSZ9897",
1228 .num_vlans = 4096,
1229 .num_alus = 4096,
1230 .num_statics = 16,
1231 .cpu_ports = 0x7F, /* can be configured as cpu port */
1232 .port_cnt = 7, /* total physical port count */
1233 .port_nirqs = 2,
1234 .ops = &ksz9477_dev_ops,
1235 .phy_errata_9477 = true,
1236 .mib_names = ksz9477_mib_names,
1237 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1238 .reg_mib_cnt = MIB_COUNTER_NUM,
1239 .regs = ksz9477_regs,
1240 .masks = ksz9477_masks,
1241 .shifts = ksz9477_shifts,
1242 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1243 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1244 .supports_mii = {false, false, false, false,
1245 false, true, true},
1246 .supports_rmii = {false, false, false, false,
1247 false, true, true},
1248 .supports_rgmii = {false, false, false, false,
1249 false, true, true},
1250 .internal_phy = {true, true, true, true,
1251 true, false, false},
1252 .gbit_capable = {true, true, true, true, true, true, true},
1253 },
1254
1255 [KSZ9893] = {
1256 .chip_id = KSZ9893_CHIP_ID,
1257 .dev_name = "KSZ9893",
1258 .num_vlans = 4096,
1259 .num_alus = 4096,
1260 .num_statics = 16,
1261 .cpu_ports = 0x07, /* can be configured as cpu port */
1262 .port_cnt = 3, /* total port count */
1263 .port_nirqs = 2,
1264 .ops = &ksz9477_dev_ops,
1265 .mib_names = ksz9477_mib_names,
1266 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1267 .reg_mib_cnt = MIB_COUNTER_NUM,
1268 .regs = ksz9477_regs,
1269 .masks = ksz9477_masks,
1270 .shifts = ksz9477_shifts,
1271 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1272 .xmii_ctrl1 = ksz8795_xmii_ctrl1, /* Same as ksz8795 */
1273 .supports_mii = {false, false, true},
1274 .supports_rmii = {false, false, true},
1275 .supports_rgmii = {false, false, true},
1276 .internal_phy = {true, true, false},
1277 .gbit_capable = {true, true, true},
1278 },
1279
1280 [KSZ9567] = {
1281 .chip_id = KSZ9567_CHIP_ID,
1282 .dev_name = "KSZ9567",
1283 .num_vlans = 4096,
1284 .num_alus = 4096,
1285 .num_statics = 16,
1286 .cpu_ports = 0x7F, /* can be configured as cpu port */
1287 .port_cnt = 7, /* total physical port count */
1288 .port_nirqs = 3,
1289 .ops = &ksz9477_dev_ops,
1290 .phy_errata_9477 = true,
1291 .mib_names = ksz9477_mib_names,
1292 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1293 .reg_mib_cnt = MIB_COUNTER_NUM,
1294 .regs = ksz9477_regs,
1295 .masks = ksz9477_masks,
1296 .shifts = ksz9477_shifts,
1297 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1298 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1299 .supports_mii = {false, false, false, false,
1300 false, true, true},
1301 .supports_rmii = {false, false, false, false,
1302 false, true, true},
1303 .supports_rgmii = {false, false, false, false,
1304 false, true, true},
1305 .internal_phy = {true, true, true, true,
1306 true, false, false},
1307 .gbit_capable = {true, true, true, true, true, true, true},
1308 },
1309
1310 [LAN9370] = {
1311 .chip_id = LAN9370_CHIP_ID,
1312 .dev_name = "LAN9370",
1313 .num_vlans = 4096,
1314 .num_alus = 1024,
1315 .num_statics = 256,
1316 .cpu_ports = 0x10, /* can be configured as cpu port */
1317 .port_cnt = 5, /* total physical port count */
1318 .port_nirqs = 6,
1319 .ops = &lan937x_dev_ops,
1320 .mib_names = ksz9477_mib_names,
1321 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1322 .reg_mib_cnt = MIB_COUNTER_NUM,
1323 .regs = ksz9477_regs,
1324 .masks = lan937x_masks,
1325 .shifts = lan937x_shifts,
1326 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1327 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1328 .supports_mii = {false, false, false, false, true},
1329 .supports_rmii = {false, false, false, false, true},
1330 .supports_rgmii = {false, false, false, false, true},
1331 .internal_phy = {true, true, true, true, false},
1332 },
1333
1334 [LAN9371] = {
1335 .chip_id = LAN9371_CHIP_ID,
1336 .dev_name = "LAN9371",
1337 .num_vlans = 4096,
1338 .num_alus = 1024,
1339 .num_statics = 256,
1340 .cpu_ports = 0x30, /* can be configured as cpu port */
1341 .port_cnt = 6, /* total physical port count */
1342 .port_nirqs = 6,
1343 .ops = &lan937x_dev_ops,
1344 .mib_names = ksz9477_mib_names,
1345 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1346 .reg_mib_cnt = MIB_COUNTER_NUM,
1347 .regs = ksz9477_regs,
1348 .masks = lan937x_masks,
1349 .shifts = lan937x_shifts,
1350 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1351 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1352 .supports_mii = {false, false, false, false, true, true},
1353 .supports_rmii = {false, false, false, false, true, true},
1354 .supports_rgmii = {false, false, false, false, true, true},
1355 .internal_phy = {true, true, true, true, false, false},
1356 },
1357
1358 [LAN9372] = {
1359 .chip_id = LAN9372_CHIP_ID,
1360 .dev_name = "LAN9372",
1361 .num_vlans = 4096,
1362 .num_alus = 1024,
1363 .num_statics = 256,
1364 .cpu_ports = 0x30, /* can be configured as cpu port */
1365 .port_cnt = 8, /* total physical port count */
1366 .port_nirqs = 6,
1367 .ops = &lan937x_dev_ops,
1368 .mib_names = ksz9477_mib_names,
1369 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1370 .reg_mib_cnt = MIB_COUNTER_NUM,
1371 .regs = ksz9477_regs,
1372 .masks = lan937x_masks,
1373 .shifts = lan937x_shifts,
1374 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1375 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1376 .supports_mii = {false, false, false, false,
1377 true, true, false, false},
1378 .supports_rmii = {false, false, false, false,
1379 true, true, false, false},
1380 .supports_rgmii = {false, false, false, false,
1381 true, true, false, false},
1382 .internal_phy = {true, true, true, true,
1383 false, false, true, true},
1384 },
1385
1386 [LAN9373] = {
1387 .chip_id = LAN9373_CHIP_ID,
1388 .dev_name = "LAN9373",
1389 .num_vlans = 4096,
1390 .num_alus = 1024,
1391 .num_statics = 256,
1392 .cpu_ports = 0x38, /* can be configured as cpu port */
1393 .port_cnt = 5, /* total physical port count */
1394 .port_nirqs = 6,
1395 .ops = &lan937x_dev_ops,
1396 .mib_names = ksz9477_mib_names,
1397 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1398 .reg_mib_cnt = MIB_COUNTER_NUM,
1399 .regs = ksz9477_regs,
1400 .masks = lan937x_masks,
1401 .shifts = lan937x_shifts,
1402 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1403 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1404 .supports_mii = {false, false, false, false,
1405 true, true, false, false},
1406 .supports_rmii = {false, false, false, false,
1407 true, true, false, false},
1408 .supports_rgmii = {false, false, false, false,
1409 true, true, false, false},
1410 .internal_phy = {true, true, true, false,
1411 false, false, true, true},
1412 },
1413
1414 [LAN9374] = {
1415 .chip_id = LAN9374_CHIP_ID,
1416 .dev_name = "LAN9374",
1417 .num_vlans = 4096,
1418 .num_alus = 1024,
1419 .num_statics = 256,
1420 .cpu_ports = 0x30, /* can be configured as cpu port */
1421 .port_cnt = 8, /* total physical port count */
1422 .port_nirqs = 6,
1423 .ops = &lan937x_dev_ops,
1424 .mib_names = ksz9477_mib_names,
1425 .mib_cnt = ARRAY_SIZE(ksz9477_mib_names),
1426 .reg_mib_cnt = MIB_COUNTER_NUM,
1427 .regs = ksz9477_regs,
1428 .masks = lan937x_masks,
1429 .shifts = lan937x_shifts,
1430 .xmii_ctrl0 = ksz9477_xmii_ctrl0,
1431 .xmii_ctrl1 = ksz9477_xmii_ctrl1,
1432 .supports_mii = {false, false, false, false,
1433 true, true, false, false},
1434 .supports_rmii = {false, false, false, false,
1435 true, true, false, false},
1436 .supports_rgmii = {false, false, false, false,
1437 true, true, false, false},
1438 .internal_phy = {true, true, true, true,
1439 false, false, true, true},
1440 },
1441 };
1442 EXPORT_SYMBOL_GPL(ksz_switch_chips);
1443
ksz_lookup_info(unsigned int prod_num)1444 static const struct ksz_chip_data *ksz_lookup_info(unsigned int prod_num)
1445 {
1446 int i;
1447
1448 for (i = 0; i < ARRAY_SIZE(ksz_switch_chips); i++) {
1449 const struct ksz_chip_data *chip = &ksz_switch_chips[i];
1450
1451 if (chip->chip_id == prod_num)
1452 return chip;
1453 }
1454
1455 return NULL;
1456 }
1457
ksz_check_device_id(struct ksz_device * dev)1458 static int ksz_check_device_id(struct ksz_device *dev)
1459 {
1460 const struct ksz_chip_data *dt_chip_data;
1461
1462 dt_chip_data = of_device_get_match_data(dev->dev);
1463
1464 /* Check for Device Tree and Chip ID */
1465 if (dt_chip_data->chip_id != dev->chip_id) {
1466 dev_err(dev->dev,
1467 "Device tree specifies chip %s but found %s, please fix it!\n",
1468 dt_chip_data->dev_name, dev->info->dev_name);
1469 return -ENODEV;
1470 }
1471
1472 return 0;
1473 }
1474
ksz_phylink_get_caps(struct dsa_switch * ds,int port,struct phylink_config * config)1475 static void ksz_phylink_get_caps(struct dsa_switch *ds, int port,
1476 struct phylink_config *config)
1477 {
1478 struct ksz_device *dev = ds->priv;
1479
1480 config->legacy_pre_march2020 = false;
1481
1482 if (dev->info->supports_mii[port])
1483 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1484
1485 if (dev->info->supports_rmii[port])
1486 __set_bit(PHY_INTERFACE_MODE_RMII,
1487 config->supported_interfaces);
1488
1489 if (dev->info->supports_rgmii[port])
1490 phy_interface_set_rgmii(config->supported_interfaces);
1491
1492 if (dev->info->internal_phy[port]) {
1493 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
1494 config->supported_interfaces);
1495 /* Compatibility for phylib's default interface type when the
1496 * phy-mode property is absent
1497 */
1498 __set_bit(PHY_INTERFACE_MODE_GMII,
1499 config->supported_interfaces);
1500 }
1501
1502 if (dev->dev_ops->get_caps)
1503 dev->dev_ops->get_caps(dev, port, config);
1504 }
1505
ksz_r_mib_stats64(struct ksz_device * dev,int port)1506 void ksz_r_mib_stats64(struct ksz_device *dev, int port)
1507 {
1508 struct ethtool_pause_stats *pstats;
1509 struct rtnl_link_stats64 *stats;
1510 struct ksz_stats_raw *raw;
1511 struct ksz_port_mib *mib;
1512
1513 mib = &dev->ports[port].mib;
1514 stats = &mib->stats64;
1515 pstats = &mib->pause_stats;
1516 raw = (struct ksz_stats_raw *)mib->counters;
1517
1518 spin_lock(&mib->stats64_lock);
1519
1520 stats->rx_packets = raw->rx_bcast + raw->rx_mcast + raw->rx_ucast +
1521 raw->rx_pause;
1522 stats->tx_packets = raw->tx_bcast + raw->tx_mcast + raw->tx_ucast +
1523 raw->tx_pause;
1524
1525 /* HW counters are counting bytes + FCS which is not acceptable
1526 * for rtnl_link_stats64 interface
1527 */
1528 stats->rx_bytes = raw->rx_total - stats->rx_packets * ETH_FCS_LEN;
1529 stats->tx_bytes = raw->tx_total - stats->tx_packets * ETH_FCS_LEN;
1530
1531 stats->rx_length_errors = raw->rx_undersize + raw->rx_fragments +
1532 raw->rx_oversize;
1533
1534 stats->rx_crc_errors = raw->rx_crc_err;
1535 stats->rx_frame_errors = raw->rx_align_err;
1536 stats->rx_dropped = raw->rx_discards;
1537 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
1538 stats->rx_frame_errors + stats->rx_dropped;
1539
1540 stats->tx_window_errors = raw->tx_late_col;
1541 stats->tx_fifo_errors = raw->tx_discards;
1542 stats->tx_aborted_errors = raw->tx_exc_col;
1543 stats->tx_errors = stats->tx_window_errors + stats->tx_fifo_errors +
1544 stats->tx_aborted_errors;
1545
1546 stats->multicast = raw->rx_mcast;
1547 stats->collisions = raw->tx_total_col;
1548
1549 pstats->tx_pause_frames = raw->tx_pause;
1550 pstats->rx_pause_frames = raw->rx_pause;
1551
1552 spin_unlock(&mib->stats64_lock);
1553 }
1554
ksz_get_stats64(struct dsa_switch * ds,int port,struct rtnl_link_stats64 * s)1555 static void ksz_get_stats64(struct dsa_switch *ds, int port,
1556 struct rtnl_link_stats64 *s)
1557 {
1558 struct ksz_device *dev = ds->priv;
1559 struct ksz_port_mib *mib;
1560
1561 mib = &dev->ports[port].mib;
1562
1563 spin_lock(&mib->stats64_lock);
1564 memcpy(s, &mib->stats64, sizeof(*s));
1565 spin_unlock(&mib->stats64_lock);
1566 }
1567
ksz_get_pause_stats(struct dsa_switch * ds,int port,struct ethtool_pause_stats * pause_stats)1568 static void ksz_get_pause_stats(struct dsa_switch *ds, int port,
1569 struct ethtool_pause_stats *pause_stats)
1570 {
1571 struct ksz_device *dev = ds->priv;
1572 struct ksz_port_mib *mib;
1573
1574 mib = &dev->ports[port].mib;
1575
1576 spin_lock(&mib->stats64_lock);
1577 memcpy(pause_stats, &mib->pause_stats, sizeof(*pause_stats));
1578 spin_unlock(&mib->stats64_lock);
1579 }
1580
ksz_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * buf)1581 static void ksz_get_strings(struct dsa_switch *ds, int port,
1582 u32 stringset, uint8_t *buf)
1583 {
1584 struct ksz_device *dev = ds->priv;
1585 int i;
1586
1587 if (stringset != ETH_SS_STATS)
1588 return;
1589
1590 for (i = 0; i < dev->info->mib_cnt; i++) {
1591 memcpy(buf + i * ETH_GSTRING_LEN,
1592 dev->info->mib_names[i].string, ETH_GSTRING_LEN);
1593 }
1594 }
1595
ksz_update_port_member(struct ksz_device * dev,int port)1596 static void ksz_update_port_member(struct ksz_device *dev, int port)
1597 {
1598 struct ksz_port *p = &dev->ports[port];
1599 struct dsa_switch *ds = dev->ds;
1600 u8 port_member = 0, cpu_port;
1601 const struct dsa_port *dp;
1602 int i, j;
1603
1604 if (!dsa_is_user_port(ds, port))
1605 return;
1606
1607 dp = dsa_to_port(ds, port);
1608 cpu_port = BIT(dsa_upstream_port(ds, port));
1609
1610 for (i = 0; i < ds->num_ports; i++) {
1611 const struct dsa_port *other_dp = dsa_to_port(ds, i);
1612 struct ksz_port *other_p = &dev->ports[i];
1613 u8 val = 0;
1614
1615 if (!dsa_is_user_port(ds, i))
1616 continue;
1617 if (port == i)
1618 continue;
1619 if (!dsa_port_bridge_same(dp, other_dp))
1620 continue;
1621 if (other_p->stp_state != BR_STATE_FORWARDING)
1622 continue;
1623
1624 if (p->stp_state == BR_STATE_FORWARDING) {
1625 val |= BIT(port);
1626 port_member |= BIT(i);
1627 }
1628
1629 /* Retain port [i]'s relationship to other ports than [port] */
1630 for (j = 0; j < ds->num_ports; j++) {
1631 const struct dsa_port *third_dp;
1632 struct ksz_port *third_p;
1633
1634 if (j == i)
1635 continue;
1636 if (j == port)
1637 continue;
1638 if (!dsa_is_user_port(ds, j))
1639 continue;
1640 third_p = &dev->ports[j];
1641 if (third_p->stp_state != BR_STATE_FORWARDING)
1642 continue;
1643 third_dp = dsa_to_port(ds, j);
1644 if (dsa_port_bridge_same(other_dp, third_dp))
1645 val |= BIT(j);
1646 }
1647
1648 dev->dev_ops->cfg_port_member(dev, i, val | cpu_port);
1649 }
1650
1651 dev->dev_ops->cfg_port_member(dev, port, port_member | cpu_port);
1652 }
1653
ksz_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)1654 static int ksz_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
1655 {
1656 struct ksz_device *dev = bus->priv;
1657 u16 val;
1658 int ret;
1659
1660 if (regnum & MII_ADDR_C45)
1661 return -EOPNOTSUPP;
1662
1663 ret = dev->dev_ops->r_phy(dev, addr, regnum, &val);
1664 if (ret < 0)
1665 return ret;
1666
1667 return val;
1668 }
1669
ksz_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)1670 static int ksz_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
1671 u16 val)
1672 {
1673 struct ksz_device *dev = bus->priv;
1674
1675 if (regnum & MII_ADDR_C45)
1676 return -EOPNOTSUPP;
1677
1678 return dev->dev_ops->w_phy(dev, addr, regnum, val);
1679 }
1680
ksz_irq_phy_setup(struct ksz_device * dev)1681 static int ksz_irq_phy_setup(struct ksz_device *dev)
1682 {
1683 struct dsa_switch *ds = dev->ds;
1684 int phy;
1685 int irq;
1686 int ret;
1687
1688 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++) {
1689 if (BIT(phy) & ds->phys_mii_mask) {
1690 irq = irq_find_mapping(dev->ports[phy].pirq.domain,
1691 PORT_SRC_PHY_INT);
1692 if (irq < 0) {
1693 ret = irq;
1694 goto out;
1695 }
1696 ds->slave_mii_bus->irq[phy] = irq;
1697 }
1698 }
1699 return 0;
1700 out:
1701 while (phy--)
1702 if (BIT(phy) & ds->phys_mii_mask)
1703 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1704
1705 return ret;
1706 }
1707
ksz_irq_phy_free(struct ksz_device * dev)1708 static void ksz_irq_phy_free(struct ksz_device *dev)
1709 {
1710 struct dsa_switch *ds = dev->ds;
1711 int phy;
1712
1713 for (phy = 0; phy < KSZ_MAX_NUM_PORTS; phy++)
1714 if (BIT(phy) & ds->phys_mii_mask)
1715 irq_dispose_mapping(ds->slave_mii_bus->irq[phy]);
1716 }
1717
ksz_mdio_register(struct ksz_device * dev)1718 static int ksz_mdio_register(struct ksz_device *dev)
1719 {
1720 struct dsa_switch *ds = dev->ds;
1721 struct device_node *mdio_np;
1722 struct mii_bus *bus;
1723 int ret;
1724
1725 mdio_np = of_get_child_by_name(dev->dev->of_node, "mdio");
1726 if (!mdio_np)
1727 return 0;
1728
1729 bus = devm_mdiobus_alloc(ds->dev);
1730 if (!bus) {
1731 of_node_put(mdio_np);
1732 return -ENOMEM;
1733 }
1734
1735 bus->priv = dev;
1736 bus->read = ksz_sw_mdio_read;
1737 bus->write = ksz_sw_mdio_write;
1738 bus->name = "ksz slave smi";
1739 snprintf(bus->id, MII_BUS_ID_SIZE, "SMI-%d", ds->index);
1740 bus->parent = ds->dev;
1741 bus->phy_mask = ~ds->phys_mii_mask;
1742
1743 ds->slave_mii_bus = bus;
1744
1745 if (dev->irq > 0) {
1746 ret = ksz_irq_phy_setup(dev);
1747 if (ret) {
1748 of_node_put(mdio_np);
1749 return ret;
1750 }
1751 }
1752
1753 ret = devm_of_mdiobus_register(ds->dev, bus, mdio_np);
1754 if (ret) {
1755 dev_err(ds->dev, "unable to register MDIO bus %s\n",
1756 bus->id);
1757 if (dev->irq > 0)
1758 ksz_irq_phy_free(dev);
1759 }
1760
1761 of_node_put(mdio_np);
1762
1763 return ret;
1764 }
1765
ksz_irq_mask(struct irq_data * d)1766 static void ksz_irq_mask(struct irq_data *d)
1767 {
1768 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1769
1770 kirq->masked |= BIT(d->hwirq);
1771 }
1772
ksz_irq_unmask(struct irq_data * d)1773 static void ksz_irq_unmask(struct irq_data *d)
1774 {
1775 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1776
1777 kirq->masked &= ~BIT(d->hwirq);
1778 }
1779
ksz_irq_bus_lock(struct irq_data * d)1780 static void ksz_irq_bus_lock(struct irq_data *d)
1781 {
1782 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1783
1784 mutex_lock(&kirq->dev->lock_irq);
1785 }
1786
ksz_irq_bus_sync_unlock(struct irq_data * d)1787 static void ksz_irq_bus_sync_unlock(struct irq_data *d)
1788 {
1789 struct ksz_irq *kirq = irq_data_get_irq_chip_data(d);
1790 struct ksz_device *dev = kirq->dev;
1791 int ret;
1792
1793 ret = ksz_write32(dev, kirq->reg_mask, kirq->masked);
1794 if (ret)
1795 dev_err(dev->dev, "failed to change IRQ mask\n");
1796
1797 mutex_unlock(&dev->lock_irq);
1798 }
1799
1800 static const struct irq_chip ksz_irq_chip = {
1801 .name = "ksz-irq",
1802 .irq_mask = ksz_irq_mask,
1803 .irq_unmask = ksz_irq_unmask,
1804 .irq_bus_lock = ksz_irq_bus_lock,
1805 .irq_bus_sync_unlock = ksz_irq_bus_sync_unlock,
1806 };
1807
ksz_irq_domain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)1808 static int ksz_irq_domain_map(struct irq_domain *d,
1809 unsigned int irq, irq_hw_number_t hwirq)
1810 {
1811 irq_set_chip_data(irq, d->host_data);
1812 irq_set_chip_and_handler(irq, &ksz_irq_chip, handle_level_irq);
1813 irq_set_noprobe(irq);
1814
1815 return 0;
1816 }
1817
1818 static const struct irq_domain_ops ksz_irq_domain_ops = {
1819 .map = ksz_irq_domain_map,
1820 .xlate = irq_domain_xlate_twocell,
1821 };
1822
ksz_irq_free(struct ksz_irq * kirq)1823 static void ksz_irq_free(struct ksz_irq *kirq)
1824 {
1825 int irq, virq;
1826
1827 free_irq(kirq->irq_num, kirq);
1828
1829 for (irq = 0; irq < kirq->nirqs; irq++) {
1830 virq = irq_find_mapping(kirq->domain, irq);
1831 irq_dispose_mapping(virq);
1832 }
1833
1834 irq_domain_remove(kirq->domain);
1835 }
1836
ksz_irq_thread_fn(int irq,void * dev_id)1837 static irqreturn_t ksz_irq_thread_fn(int irq, void *dev_id)
1838 {
1839 struct ksz_irq *kirq = dev_id;
1840 unsigned int nhandled = 0;
1841 struct ksz_device *dev;
1842 unsigned int sub_irq;
1843 u8 data;
1844 int ret;
1845 u8 n;
1846
1847 dev = kirq->dev;
1848
1849 /* Read interrupt status register */
1850 ret = ksz_read8(dev, kirq->reg_status, &data);
1851 if (ret)
1852 goto out;
1853
1854 for (n = 0; n < kirq->nirqs; ++n) {
1855 if (data & BIT(n)) {
1856 sub_irq = irq_find_mapping(kirq->domain, n);
1857 handle_nested_irq(sub_irq);
1858 ++nhandled;
1859 }
1860 }
1861 out:
1862 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
1863 }
1864
ksz_irq_common_setup(struct ksz_device * dev,struct ksz_irq * kirq)1865 static int ksz_irq_common_setup(struct ksz_device *dev, struct ksz_irq *kirq)
1866 {
1867 int ret, n;
1868
1869 kirq->dev = dev;
1870 kirq->masked = ~0;
1871
1872 kirq->domain = irq_domain_add_simple(dev->dev->of_node, kirq->nirqs, 0,
1873 &ksz_irq_domain_ops, kirq);
1874 if (!kirq->domain)
1875 return -ENOMEM;
1876
1877 for (n = 0; n < kirq->nirqs; n++)
1878 irq_create_mapping(kirq->domain, n);
1879
1880 ret = request_threaded_irq(kirq->irq_num, NULL, ksz_irq_thread_fn,
1881 IRQF_ONESHOT, kirq->name, kirq);
1882 if (ret)
1883 goto out;
1884
1885 return 0;
1886
1887 out:
1888 ksz_irq_free(kirq);
1889
1890 return ret;
1891 }
1892
ksz_girq_setup(struct ksz_device * dev)1893 static int ksz_girq_setup(struct ksz_device *dev)
1894 {
1895 struct ksz_irq *girq = &dev->girq;
1896
1897 girq->nirqs = dev->info->port_cnt;
1898 girq->reg_mask = REG_SW_PORT_INT_MASK__1;
1899 girq->reg_status = REG_SW_PORT_INT_STATUS__1;
1900 snprintf(girq->name, sizeof(girq->name), "global_port_irq");
1901
1902 girq->irq_num = dev->irq;
1903
1904 return ksz_irq_common_setup(dev, girq);
1905 }
1906
ksz_pirq_setup(struct ksz_device * dev,u8 p)1907 static int ksz_pirq_setup(struct ksz_device *dev, u8 p)
1908 {
1909 struct ksz_irq *pirq = &dev->ports[p].pirq;
1910
1911 pirq->nirqs = dev->info->port_nirqs;
1912 pirq->reg_mask = dev->dev_ops->get_port_addr(p, REG_PORT_INT_MASK);
1913 pirq->reg_status = dev->dev_ops->get_port_addr(p, REG_PORT_INT_STATUS);
1914 snprintf(pirq->name, sizeof(pirq->name), "port_irq-%d", p);
1915
1916 pirq->irq_num = irq_find_mapping(dev->girq.domain, p);
1917 if (pirq->irq_num < 0)
1918 return pirq->irq_num;
1919
1920 return ksz_irq_common_setup(dev, pirq);
1921 }
1922
ksz_setup(struct dsa_switch * ds)1923 static int ksz_setup(struct dsa_switch *ds)
1924 {
1925 struct ksz_device *dev = ds->priv;
1926 struct dsa_port *dp;
1927 struct ksz_port *p;
1928 const u16 *regs;
1929 int ret;
1930
1931 regs = dev->info->regs;
1932
1933 dev->vlan_cache = devm_kcalloc(dev->dev, sizeof(struct vlan_table),
1934 dev->info->num_vlans, GFP_KERNEL);
1935 if (!dev->vlan_cache)
1936 return -ENOMEM;
1937
1938 ret = dev->dev_ops->reset(dev);
1939 if (ret) {
1940 dev_err(ds->dev, "failed to reset switch\n");
1941 return ret;
1942 }
1943
1944 /* set broadcast storm protection 10% rate */
1945 regmap_update_bits(dev->regmap[1], regs[S_BROADCAST_CTRL],
1946 BROADCAST_STORM_RATE,
1947 (BROADCAST_STORM_VALUE *
1948 BROADCAST_STORM_PROT_RATE) / 100);
1949
1950 dev->dev_ops->config_cpu_port(ds);
1951
1952 dev->dev_ops->enable_stp_addr(dev);
1953
1954 regmap_update_bits(dev->regmap[0], regs[S_MULTICAST_CTRL],
1955 MULTICAST_STORM_DISABLE, MULTICAST_STORM_DISABLE);
1956
1957 ksz_init_mib_timer(dev);
1958
1959 ds->configure_vlan_while_not_filtering = false;
1960
1961 if (dev->dev_ops->setup) {
1962 ret = dev->dev_ops->setup(ds);
1963 if (ret)
1964 return ret;
1965 }
1966
1967 /* Start with learning disabled on standalone user ports, and enabled
1968 * on the CPU port. In lack of other finer mechanisms, learning on the
1969 * CPU port will avoid flooding bridge local addresses on the network
1970 * in some cases.
1971 */
1972 p = &dev->ports[dev->cpu_port];
1973 p->learning = true;
1974
1975 if (dev->irq > 0) {
1976 ret = ksz_girq_setup(dev);
1977 if (ret)
1978 return ret;
1979
1980 dsa_switch_for_each_user_port(dp, dev->ds) {
1981 ret = ksz_pirq_setup(dev, dp->index);
1982 if (ret)
1983 goto out_girq;
1984 }
1985 }
1986
1987 ret = ksz_mdio_register(dev);
1988 if (ret < 0) {
1989 dev_err(dev->dev, "failed to register the mdio");
1990 goto out_pirq;
1991 }
1992
1993 /* start switch */
1994 regmap_update_bits(dev->regmap[0], regs[S_START_CTRL],
1995 SW_START, SW_START);
1996
1997 return 0;
1998
1999 out_pirq:
2000 if (dev->irq > 0)
2001 dsa_switch_for_each_user_port(dp, dev->ds)
2002 ksz_irq_free(&dev->ports[dp->index].pirq);
2003 out_girq:
2004 if (dev->irq > 0)
2005 ksz_irq_free(&dev->girq);
2006
2007 return ret;
2008 }
2009
ksz_teardown(struct dsa_switch * ds)2010 static void ksz_teardown(struct dsa_switch *ds)
2011 {
2012 struct ksz_device *dev = ds->priv;
2013 struct dsa_port *dp;
2014
2015 if (dev->irq > 0) {
2016 dsa_switch_for_each_user_port(dp, dev->ds)
2017 ksz_irq_free(&dev->ports[dp->index].pirq);
2018
2019 ksz_irq_free(&dev->girq);
2020 }
2021
2022 if (dev->dev_ops->teardown)
2023 dev->dev_ops->teardown(ds);
2024 }
2025
port_r_cnt(struct ksz_device * dev,int port)2026 static void port_r_cnt(struct ksz_device *dev, int port)
2027 {
2028 struct ksz_port_mib *mib = &dev->ports[port].mib;
2029 u64 *dropped;
2030
2031 /* Some ports may not have MIB counters before SWITCH_COUNTER_NUM. */
2032 while (mib->cnt_ptr < dev->info->reg_mib_cnt) {
2033 dev->dev_ops->r_mib_cnt(dev, port, mib->cnt_ptr,
2034 &mib->counters[mib->cnt_ptr]);
2035 ++mib->cnt_ptr;
2036 }
2037
2038 /* last one in storage */
2039 dropped = &mib->counters[dev->info->mib_cnt];
2040
2041 /* Some ports may not have MIB counters after SWITCH_COUNTER_NUM. */
2042 while (mib->cnt_ptr < dev->info->mib_cnt) {
2043 dev->dev_ops->r_mib_pkt(dev, port, mib->cnt_ptr,
2044 dropped, &mib->counters[mib->cnt_ptr]);
2045 ++mib->cnt_ptr;
2046 }
2047 mib->cnt_ptr = 0;
2048 }
2049
ksz_mib_read_work(struct work_struct * work)2050 static void ksz_mib_read_work(struct work_struct *work)
2051 {
2052 struct ksz_device *dev = container_of(work, struct ksz_device,
2053 mib_read.work);
2054 struct ksz_port_mib *mib;
2055 struct ksz_port *p;
2056 int i;
2057
2058 for (i = 0; i < dev->info->port_cnt; i++) {
2059 if (dsa_is_unused_port(dev->ds, i))
2060 continue;
2061
2062 p = &dev->ports[i];
2063 mib = &p->mib;
2064 mutex_lock(&mib->cnt_mutex);
2065
2066 /* Only read MIB counters when the port is told to do.
2067 * If not, read only dropped counters when link is not up.
2068 */
2069 if (!p->read) {
2070 const struct dsa_port *dp = dsa_to_port(dev->ds, i);
2071
2072 if (!netif_carrier_ok(dp->slave))
2073 mib->cnt_ptr = dev->info->reg_mib_cnt;
2074 }
2075 port_r_cnt(dev, i);
2076 p->read = false;
2077
2078 if (dev->dev_ops->r_mib_stat64)
2079 dev->dev_ops->r_mib_stat64(dev, i);
2080
2081 mutex_unlock(&mib->cnt_mutex);
2082 }
2083
2084 schedule_delayed_work(&dev->mib_read, dev->mib_read_interval);
2085 }
2086
ksz_init_mib_timer(struct ksz_device * dev)2087 void ksz_init_mib_timer(struct ksz_device *dev)
2088 {
2089 int i;
2090
2091 INIT_DELAYED_WORK(&dev->mib_read, ksz_mib_read_work);
2092
2093 for (i = 0; i < dev->info->port_cnt; i++) {
2094 struct ksz_port_mib *mib = &dev->ports[i].mib;
2095
2096 dev->dev_ops->port_init_cnt(dev, i);
2097
2098 mib->cnt_ptr = 0;
2099 memset(mib->counters, 0, dev->info->mib_cnt * sizeof(u64));
2100 }
2101 }
2102
ksz_phy_read16(struct dsa_switch * ds,int addr,int reg)2103 static int ksz_phy_read16(struct dsa_switch *ds, int addr, int reg)
2104 {
2105 struct ksz_device *dev = ds->priv;
2106 u16 val = 0xffff;
2107 int ret;
2108
2109 ret = dev->dev_ops->r_phy(dev, addr, reg, &val);
2110 if (ret)
2111 return ret;
2112
2113 return val;
2114 }
2115
ksz_phy_write16(struct dsa_switch * ds,int addr,int reg,u16 val)2116 static int ksz_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
2117 {
2118 struct ksz_device *dev = ds->priv;
2119 int ret;
2120
2121 ret = dev->dev_ops->w_phy(dev, addr, reg, val);
2122 if (ret)
2123 return ret;
2124
2125 return 0;
2126 }
2127
ksz_get_phy_flags(struct dsa_switch * ds,int port)2128 static u32 ksz_get_phy_flags(struct dsa_switch *ds, int port)
2129 {
2130 struct ksz_device *dev = ds->priv;
2131
2132 if (dev->chip_id == KSZ8830_CHIP_ID) {
2133 /* Silicon Errata Sheet (DS80000830A):
2134 * Port 1 does not work with LinkMD Cable-Testing.
2135 * Port 1 does not respond to received PAUSE control frames.
2136 */
2137 if (!port)
2138 return MICREL_KSZ8_P1_ERRATA;
2139 }
2140
2141 return 0;
2142 }
2143
ksz_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)2144 static void ksz_mac_link_down(struct dsa_switch *ds, int port,
2145 unsigned int mode, phy_interface_t interface)
2146 {
2147 struct ksz_device *dev = ds->priv;
2148 struct ksz_port *p = &dev->ports[port];
2149
2150 /* Read all MIB counters when the link is going down. */
2151 p->read = true;
2152 /* timer started */
2153 if (dev->mib_read_interval)
2154 schedule_delayed_work(&dev->mib_read, 0);
2155 }
2156
ksz_sset_count(struct dsa_switch * ds,int port,int sset)2157 static int ksz_sset_count(struct dsa_switch *ds, int port, int sset)
2158 {
2159 struct ksz_device *dev = ds->priv;
2160
2161 if (sset != ETH_SS_STATS)
2162 return 0;
2163
2164 return dev->info->mib_cnt;
2165 }
2166
ksz_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * buf)2167 static void ksz_get_ethtool_stats(struct dsa_switch *ds, int port,
2168 uint64_t *buf)
2169 {
2170 const struct dsa_port *dp = dsa_to_port(ds, port);
2171 struct ksz_device *dev = ds->priv;
2172 struct ksz_port_mib *mib;
2173
2174 mib = &dev->ports[port].mib;
2175 mutex_lock(&mib->cnt_mutex);
2176
2177 /* Only read dropped counters if no link. */
2178 if (!netif_carrier_ok(dp->slave))
2179 mib->cnt_ptr = dev->info->reg_mib_cnt;
2180 port_r_cnt(dev, port);
2181 memcpy(buf, mib->counters, dev->info->mib_cnt * sizeof(u64));
2182 mutex_unlock(&mib->cnt_mutex);
2183 }
2184
ksz_port_bridge_join(struct dsa_switch * ds,int port,struct dsa_bridge bridge,bool * tx_fwd_offload,struct netlink_ext_ack * extack)2185 static int ksz_port_bridge_join(struct dsa_switch *ds, int port,
2186 struct dsa_bridge bridge,
2187 bool *tx_fwd_offload,
2188 struct netlink_ext_ack *extack)
2189 {
2190 /* port_stp_state_set() will be called after to put the port in
2191 * appropriate state so there is no need to do anything.
2192 */
2193
2194 return 0;
2195 }
2196
ksz_port_bridge_leave(struct dsa_switch * ds,int port,struct dsa_bridge bridge)2197 static void ksz_port_bridge_leave(struct dsa_switch *ds, int port,
2198 struct dsa_bridge bridge)
2199 {
2200 /* port_stp_state_set() will be called after to put the port in
2201 * forwarding state so there is no need to do anything.
2202 */
2203 }
2204
ksz_port_fast_age(struct dsa_switch * ds,int port)2205 static void ksz_port_fast_age(struct dsa_switch *ds, int port)
2206 {
2207 struct ksz_device *dev = ds->priv;
2208
2209 dev->dev_ops->flush_dyn_mac_table(dev, port);
2210 }
2211
ksz_set_ageing_time(struct dsa_switch * ds,unsigned int msecs)2212 static int ksz_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
2213 {
2214 struct ksz_device *dev = ds->priv;
2215
2216 if (!dev->dev_ops->set_ageing_time)
2217 return -EOPNOTSUPP;
2218
2219 return dev->dev_ops->set_ageing_time(dev, msecs);
2220 }
2221
ksz_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2222 static int ksz_port_fdb_add(struct dsa_switch *ds, int port,
2223 const unsigned char *addr, u16 vid,
2224 struct dsa_db db)
2225 {
2226 struct ksz_device *dev = ds->priv;
2227
2228 if (!dev->dev_ops->fdb_add)
2229 return -EOPNOTSUPP;
2230
2231 return dev->dev_ops->fdb_add(dev, port, addr, vid, db);
2232 }
2233
ksz_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid,struct dsa_db db)2234 static int ksz_port_fdb_del(struct dsa_switch *ds, int port,
2235 const unsigned char *addr,
2236 u16 vid, struct dsa_db db)
2237 {
2238 struct ksz_device *dev = ds->priv;
2239
2240 if (!dev->dev_ops->fdb_del)
2241 return -EOPNOTSUPP;
2242
2243 return dev->dev_ops->fdb_del(dev, port, addr, vid, db);
2244 }
2245
ksz_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)2246 static int ksz_port_fdb_dump(struct dsa_switch *ds, int port,
2247 dsa_fdb_dump_cb_t *cb, void *data)
2248 {
2249 struct ksz_device *dev = ds->priv;
2250
2251 if (!dev->dev_ops->fdb_dump)
2252 return -EOPNOTSUPP;
2253
2254 return dev->dev_ops->fdb_dump(dev, port, cb, data);
2255 }
2256
ksz_port_mdb_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2257 static int ksz_port_mdb_add(struct dsa_switch *ds, int port,
2258 const struct switchdev_obj_port_mdb *mdb,
2259 struct dsa_db db)
2260 {
2261 struct ksz_device *dev = ds->priv;
2262
2263 if (!dev->dev_ops->mdb_add)
2264 return -EOPNOTSUPP;
2265
2266 return dev->dev_ops->mdb_add(dev, port, mdb, db);
2267 }
2268
ksz_port_mdb_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_mdb * mdb,struct dsa_db db)2269 static int ksz_port_mdb_del(struct dsa_switch *ds, int port,
2270 const struct switchdev_obj_port_mdb *mdb,
2271 struct dsa_db db)
2272 {
2273 struct ksz_device *dev = ds->priv;
2274
2275 if (!dev->dev_ops->mdb_del)
2276 return -EOPNOTSUPP;
2277
2278 return dev->dev_ops->mdb_del(dev, port, mdb, db);
2279 }
2280
ksz_enable_port(struct dsa_switch * ds,int port,struct phy_device * phy)2281 static int ksz_enable_port(struct dsa_switch *ds, int port,
2282 struct phy_device *phy)
2283 {
2284 struct ksz_device *dev = ds->priv;
2285
2286 if (!dsa_is_user_port(ds, port))
2287 return 0;
2288
2289 /* setup slave port */
2290 dev->dev_ops->port_setup(dev, port, false);
2291
2292 /* port_stp_state_set() will be called after to enable the port so
2293 * there is no need to do anything.
2294 */
2295
2296 return 0;
2297 }
2298
ksz_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)2299 void ksz_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
2300 {
2301 struct ksz_device *dev = ds->priv;
2302 struct ksz_port *p;
2303 const u16 *regs;
2304 u8 data;
2305
2306 regs = dev->info->regs;
2307
2308 ksz_pread8(dev, port, regs[P_STP_CTRL], &data);
2309 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2310
2311 p = &dev->ports[port];
2312
2313 switch (state) {
2314 case BR_STATE_DISABLED:
2315 data |= PORT_LEARN_DISABLE;
2316 break;
2317 case BR_STATE_LISTENING:
2318 data |= (PORT_RX_ENABLE | PORT_LEARN_DISABLE);
2319 break;
2320 case BR_STATE_LEARNING:
2321 data |= PORT_RX_ENABLE;
2322 if (!p->learning)
2323 data |= PORT_LEARN_DISABLE;
2324 break;
2325 case BR_STATE_FORWARDING:
2326 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2327 if (!p->learning)
2328 data |= PORT_LEARN_DISABLE;
2329 break;
2330 case BR_STATE_BLOCKING:
2331 data |= PORT_LEARN_DISABLE;
2332 break;
2333 default:
2334 dev_err(ds->dev, "invalid STP state: %d\n", state);
2335 return;
2336 }
2337
2338 ksz_pwrite8(dev, port, regs[P_STP_CTRL], data);
2339
2340 p->stp_state = state;
2341
2342 ksz_update_port_member(dev, port);
2343 }
2344
ksz_port_pre_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2345 static int ksz_port_pre_bridge_flags(struct dsa_switch *ds, int port,
2346 struct switchdev_brport_flags flags,
2347 struct netlink_ext_ack *extack)
2348 {
2349 if (flags.mask & ~BR_LEARNING)
2350 return -EINVAL;
2351
2352 return 0;
2353 }
2354
ksz_port_bridge_flags(struct dsa_switch * ds,int port,struct switchdev_brport_flags flags,struct netlink_ext_ack * extack)2355 static int ksz_port_bridge_flags(struct dsa_switch *ds, int port,
2356 struct switchdev_brport_flags flags,
2357 struct netlink_ext_ack *extack)
2358 {
2359 struct ksz_device *dev = ds->priv;
2360 struct ksz_port *p = &dev->ports[port];
2361
2362 if (flags.mask & BR_LEARNING) {
2363 p->learning = !!(flags.val & BR_LEARNING);
2364
2365 /* Make the change take effect immediately */
2366 ksz_port_stp_state_set(ds, port, p->stp_state);
2367 }
2368
2369 return 0;
2370 }
2371
ksz_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)2372 static enum dsa_tag_protocol ksz_get_tag_protocol(struct dsa_switch *ds,
2373 int port,
2374 enum dsa_tag_protocol mp)
2375 {
2376 struct ksz_device *dev = ds->priv;
2377 enum dsa_tag_protocol proto = DSA_TAG_PROTO_NONE;
2378
2379 if (dev->chip_id == KSZ8795_CHIP_ID ||
2380 dev->chip_id == KSZ8794_CHIP_ID ||
2381 dev->chip_id == KSZ8765_CHIP_ID)
2382 proto = DSA_TAG_PROTO_KSZ8795;
2383
2384 if (dev->chip_id == KSZ8830_CHIP_ID ||
2385 dev->chip_id == KSZ8563_CHIP_ID ||
2386 dev->chip_id == KSZ9893_CHIP_ID)
2387 proto = DSA_TAG_PROTO_KSZ9893;
2388
2389 if (dev->chip_id == KSZ9477_CHIP_ID ||
2390 dev->chip_id == KSZ9896_CHIP_ID ||
2391 dev->chip_id == KSZ9897_CHIP_ID ||
2392 dev->chip_id == KSZ9567_CHIP_ID)
2393 proto = DSA_TAG_PROTO_KSZ9477;
2394
2395 if (is_lan937x(dev))
2396 proto = DSA_TAG_PROTO_LAN937X_VALUE;
2397
2398 return proto;
2399 }
2400
ksz_port_vlan_filtering(struct dsa_switch * ds,int port,bool flag,struct netlink_ext_ack * extack)2401 static int ksz_port_vlan_filtering(struct dsa_switch *ds, int port,
2402 bool flag, struct netlink_ext_ack *extack)
2403 {
2404 struct ksz_device *dev = ds->priv;
2405
2406 if (!dev->dev_ops->vlan_filtering)
2407 return -EOPNOTSUPP;
2408
2409 return dev->dev_ops->vlan_filtering(dev, port, flag, extack);
2410 }
2411
ksz_port_vlan_add(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan,struct netlink_ext_ack * extack)2412 static int ksz_port_vlan_add(struct dsa_switch *ds, int port,
2413 const struct switchdev_obj_port_vlan *vlan,
2414 struct netlink_ext_ack *extack)
2415 {
2416 struct ksz_device *dev = ds->priv;
2417
2418 if (!dev->dev_ops->vlan_add)
2419 return -EOPNOTSUPP;
2420
2421 return dev->dev_ops->vlan_add(dev, port, vlan, extack);
2422 }
2423
ksz_port_vlan_del(struct dsa_switch * ds,int port,const struct switchdev_obj_port_vlan * vlan)2424 static int ksz_port_vlan_del(struct dsa_switch *ds, int port,
2425 const struct switchdev_obj_port_vlan *vlan)
2426 {
2427 struct ksz_device *dev = ds->priv;
2428
2429 if (!dev->dev_ops->vlan_del)
2430 return -EOPNOTSUPP;
2431
2432 return dev->dev_ops->vlan_del(dev, port, vlan);
2433 }
2434
ksz_port_mirror_add(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror,bool ingress,struct netlink_ext_ack * extack)2435 static int ksz_port_mirror_add(struct dsa_switch *ds, int port,
2436 struct dsa_mall_mirror_tc_entry *mirror,
2437 bool ingress, struct netlink_ext_ack *extack)
2438 {
2439 struct ksz_device *dev = ds->priv;
2440
2441 if (!dev->dev_ops->mirror_add)
2442 return -EOPNOTSUPP;
2443
2444 return dev->dev_ops->mirror_add(dev, port, mirror, ingress, extack);
2445 }
2446
ksz_port_mirror_del(struct dsa_switch * ds,int port,struct dsa_mall_mirror_tc_entry * mirror)2447 static void ksz_port_mirror_del(struct dsa_switch *ds, int port,
2448 struct dsa_mall_mirror_tc_entry *mirror)
2449 {
2450 struct ksz_device *dev = ds->priv;
2451
2452 if (dev->dev_ops->mirror_del)
2453 dev->dev_ops->mirror_del(dev, port, mirror);
2454 }
2455
ksz_change_mtu(struct dsa_switch * ds,int port,int mtu)2456 static int ksz_change_mtu(struct dsa_switch *ds, int port, int mtu)
2457 {
2458 struct ksz_device *dev = ds->priv;
2459
2460 if (!dev->dev_ops->change_mtu)
2461 return -EOPNOTSUPP;
2462
2463 return dev->dev_ops->change_mtu(dev, port, mtu);
2464 }
2465
ksz_max_mtu(struct dsa_switch * ds,int port)2466 static int ksz_max_mtu(struct dsa_switch *ds, int port)
2467 {
2468 struct ksz_device *dev = ds->priv;
2469
2470 if (!dev->dev_ops->max_mtu)
2471 return -EOPNOTSUPP;
2472
2473 return dev->dev_ops->max_mtu(dev, port);
2474 }
2475
ksz_set_xmii(struct ksz_device * dev,int port,phy_interface_t interface)2476 static void ksz_set_xmii(struct ksz_device *dev, int port,
2477 phy_interface_t interface)
2478 {
2479 const u8 *bitval = dev->info->xmii_ctrl1;
2480 struct ksz_port *p = &dev->ports[port];
2481 const u16 *regs = dev->info->regs;
2482 u8 data8;
2483
2484 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2485
2486 data8 &= ~(P_MII_SEL_M | P_RGMII_ID_IG_ENABLE |
2487 P_RGMII_ID_EG_ENABLE);
2488
2489 switch (interface) {
2490 case PHY_INTERFACE_MODE_MII:
2491 data8 |= bitval[P_MII_SEL];
2492 break;
2493 case PHY_INTERFACE_MODE_RMII:
2494 data8 |= bitval[P_RMII_SEL];
2495 break;
2496 case PHY_INTERFACE_MODE_GMII:
2497 data8 |= bitval[P_GMII_SEL];
2498 break;
2499 case PHY_INTERFACE_MODE_RGMII:
2500 case PHY_INTERFACE_MODE_RGMII_ID:
2501 case PHY_INTERFACE_MODE_RGMII_TXID:
2502 case PHY_INTERFACE_MODE_RGMII_RXID:
2503 data8 |= bitval[P_RGMII_SEL];
2504 /* On KSZ9893, disable RGMII in-band status support */
2505 if (dev->chip_id == KSZ9893_CHIP_ID ||
2506 dev->chip_id == KSZ8563_CHIP_ID)
2507 data8 &= ~P_MII_MAC_MODE;
2508 break;
2509 default:
2510 dev_err(dev->dev, "Unsupported interface '%s' for port %d\n",
2511 phy_modes(interface), port);
2512 return;
2513 }
2514
2515 if (p->rgmii_tx_val)
2516 data8 |= P_RGMII_ID_EG_ENABLE;
2517
2518 if (p->rgmii_rx_val)
2519 data8 |= P_RGMII_ID_IG_ENABLE;
2520
2521 /* Write the updated value */
2522 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2523 }
2524
ksz_get_xmii(struct ksz_device * dev,int port,bool gbit)2525 phy_interface_t ksz_get_xmii(struct ksz_device *dev, int port, bool gbit)
2526 {
2527 const u8 *bitval = dev->info->xmii_ctrl1;
2528 const u16 *regs = dev->info->regs;
2529 phy_interface_t interface;
2530 u8 data8;
2531 u8 val;
2532
2533 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2534
2535 val = FIELD_GET(P_MII_SEL_M, data8);
2536
2537 if (val == bitval[P_MII_SEL]) {
2538 if (gbit)
2539 interface = PHY_INTERFACE_MODE_GMII;
2540 else
2541 interface = PHY_INTERFACE_MODE_MII;
2542 } else if (val == bitval[P_RMII_SEL]) {
2543 interface = PHY_INTERFACE_MODE_RGMII;
2544 } else {
2545 interface = PHY_INTERFACE_MODE_RGMII;
2546 if (data8 & P_RGMII_ID_EG_ENABLE)
2547 interface = PHY_INTERFACE_MODE_RGMII_TXID;
2548 if (data8 & P_RGMII_ID_IG_ENABLE) {
2549 interface = PHY_INTERFACE_MODE_RGMII_RXID;
2550 if (data8 & P_RGMII_ID_EG_ENABLE)
2551 interface = PHY_INTERFACE_MODE_RGMII_ID;
2552 }
2553 }
2554
2555 return interface;
2556 }
2557
ksz_phylink_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)2558 static void ksz_phylink_mac_config(struct dsa_switch *ds, int port,
2559 unsigned int mode,
2560 const struct phylink_link_state *state)
2561 {
2562 struct ksz_device *dev = ds->priv;
2563
2564 if (ksz_is_ksz88x3(dev))
2565 return;
2566
2567 /* Internal PHYs */
2568 if (dev->info->internal_phy[port])
2569 return;
2570
2571 if (phylink_autoneg_inband(mode)) {
2572 dev_err(dev->dev, "In-band AN not supported!\n");
2573 return;
2574 }
2575
2576 ksz_set_xmii(dev, port, state->interface);
2577
2578 if (dev->dev_ops->phylink_mac_config)
2579 dev->dev_ops->phylink_mac_config(dev, port, mode, state);
2580
2581 if (dev->dev_ops->setup_rgmii_delay)
2582 dev->dev_ops->setup_rgmii_delay(dev, port);
2583 }
2584
ksz_get_gbit(struct ksz_device * dev,int port)2585 bool ksz_get_gbit(struct ksz_device *dev, int port)
2586 {
2587 const u8 *bitval = dev->info->xmii_ctrl1;
2588 const u16 *regs = dev->info->regs;
2589 bool gbit = false;
2590 u8 data8;
2591 bool val;
2592
2593 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2594
2595 val = FIELD_GET(P_GMII_1GBIT_M, data8);
2596
2597 if (val == bitval[P_GMII_1GBIT])
2598 gbit = true;
2599
2600 return gbit;
2601 }
2602
ksz_set_gbit(struct ksz_device * dev,int port,bool gbit)2603 static void ksz_set_gbit(struct ksz_device *dev, int port, bool gbit)
2604 {
2605 const u8 *bitval = dev->info->xmii_ctrl1;
2606 const u16 *regs = dev->info->regs;
2607 u8 data8;
2608
2609 ksz_pread8(dev, port, regs[P_XMII_CTRL_1], &data8);
2610
2611 data8 &= ~P_GMII_1GBIT_M;
2612
2613 if (gbit)
2614 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_1GBIT]);
2615 else
2616 data8 |= FIELD_PREP(P_GMII_1GBIT_M, bitval[P_GMII_NOT_1GBIT]);
2617
2618 /* Write the updated value */
2619 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_1], data8);
2620 }
2621
ksz_set_100_10mbit(struct ksz_device * dev,int port,int speed)2622 static void ksz_set_100_10mbit(struct ksz_device *dev, int port, int speed)
2623 {
2624 const u8 *bitval = dev->info->xmii_ctrl0;
2625 const u16 *regs = dev->info->regs;
2626 u8 data8;
2627
2628 ksz_pread8(dev, port, regs[P_XMII_CTRL_0], &data8);
2629
2630 data8 &= ~P_MII_100MBIT_M;
2631
2632 if (speed == SPEED_100)
2633 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_100MBIT]);
2634 else
2635 data8 |= FIELD_PREP(P_MII_100MBIT_M, bitval[P_MII_10MBIT]);
2636
2637 /* Write the updated value */
2638 ksz_pwrite8(dev, port, regs[P_XMII_CTRL_0], data8);
2639 }
2640
ksz_port_set_xmii_speed(struct ksz_device * dev,int port,int speed)2641 static void ksz_port_set_xmii_speed(struct ksz_device *dev, int port, int speed)
2642 {
2643 if (speed == SPEED_1000)
2644 ksz_set_gbit(dev, port, true);
2645 else
2646 ksz_set_gbit(dev, port, false);
2647
2648 if (speed == SPEED_100 || speed == SPEED_10)
2649 ksz_set_100_10mbit(dev, port, speed);
2650 }
2651
ksz_duplex_flowctrl(struct ksz_device * dev,int port,int duplex,bool tx_pause,bool rx_pause)2652 static void ksz_duplex_flowctrl(struct ksz_device *dev, int port, int duplex,
2653 bool tx_pause, bool rx_pause)
2654 {
2655 const u8 *bitval = dev->info->xmii_ctrl0;
2656 const u32 *masks = dev->info->masks;
2657 const u16 *regs = dev->info->regs;
2658 u8 mask;
2659 u8 val;
2660
2661 mask = P_MII_DUPLEX_M | masks[P_MII_TX_FLOW_CTRL] |
2662 masks[P_MII_RX_FLOW_CTRL];
2663
2664 if (duplex == DUPLEX_FULL)
2665 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_FULL_DUPLEX]);
2666 else
2667 val = FIELD_PREP(P_MII_DUPLEX_M, bitval[P_MII_HALF_DUPLEX]);
2668
2669 if (tx_pause)
2670 val |= masks[P_MII_TX_FLOW_CTRL];
2671
2672 if (rx_pause)
2673 val |= masks[P_MII_RX_FLOW_CTRL];
2674
2675 ksz_prmw8(dev, port, regs[P_XMII_CTRL_0], mask, val);
2676 }
2677
ksz9477_phylink_mac_link_up(struct ksz_device * dev,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2678 static void ksz9477_phylink_mac_link_up(struct ksz_device *dev, int port,
2679 unsigned int mode,
2680 phy_interface_t interface,
2681 struct phy_device *phydev, int speed,
2682 int duplex, bool tx_pause,
2683 bool rx_pause)
2684 {
2685 struct ksz_port *p;
2686
2687 p = &dev->ports[port];
2688
2689 /* Internal PHYs */
2690 if (dev->info->internal_phy[port])
2691 return;
2692
2693 p->phydev.speed = speed;
2694
2695 ksz_port_set_xmii_speed(dev, port, speed);
2696
2697 ksz_duplex_flowctrl(dev, port, duplex, tx_pause, rx_pause);
2698 }
2699
ksz_phylink_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev,int speed,int duplex,bool tx_pause,bool rx_pause)2700 static void ksz_phylink_mac_link_up(struct dsa_switch *ds, int port,
2701 unsigned int mode,
2702 phy_interface_t interface,
2703 struct phy_device *phydev, int speed,
2704 int duplex, bool tx_pause, bool rx_pause)
2705 {
2706 struct ksz_device *dev = ds->priv;
2707
2708 if (dev->dev_ops->phylink_mac_link_up)
2709 dev->dev_ops->phylink_mac_link_up(dev, port, mode, interface,
2710 phydev, speed, duplex,
2711 tx_pause, rx_pause);
2712 }
2713
ksz_switch_detect(struct ksz_device * dev)2714 static int ksz_switch_detect(struct ksz_device *dev)
2715 {
2716 u8 id1, id2, id4;
2717 u16 id16;
2718 u32 id32;
2719 int ret;
2720
2721 /* read chip id */
2722 ret = ksz_read16(dev, REG_CHIP_ID0, &id16);
2723 if (ret)
2724 return ret;
2725
2726 id1 = FIELD_GET(SW_FAMILY_ID_M, id16);
2727 id2 = FIELD_GET(SW_CHIP_ID_M, id16);
2728
2729 switch (id1) {
2730 case KSZ87_FAMILY_ID:
2731 if (id2 == KSZ87_CHIP_ID_95) {
2732 u8 val;
2733
2734 dev->chip_id = KSZ8795_CHIP_ID;
2735
2736 ksz_read8(dev, KSZ8_PORT_STATUS_0, &val);
2737 if (val & KSZ8_PORT_FIBER_MODE)
2738 dev->chip_id = KSZ8765_CHIP_ID;
2739 } else if (id2 == KSZ87_CHIP_ID_94) {
2740 dev->chip_id = KSZ8794_CHIP_ID;
2741 } else {
2742 return -ENODEV;
2743 }
2744 break;
2745 case KSZ88_FAMILY_ID:
2746 if (id2 == KSZ88_CHIP_ID_63)
2747 dev->chip_id = KSZ8830_CHIP_ID;
2748 else
2749 return -ENODEV;
2750 break;
2751 default:
2752 ret = ksz_read32(dev, REG_CHIP_ID0, &id32);
2753 if (ret)
2754 return ret;
2755
2756 dev->chip_rev = FIELD_GET(SW_REV_ID_M, id32);
2757 id32 &= ~0xFF;
2758
2759 switch (id32) {
2760 case KSZ9477_CHIP_ID:
2761 case KSZ9896_CHIP_ID:
2762 case KSZ9897_CHIP_ID:
2763 case KSZ9567_CHIP_ID:
2764 case LAN9370_CHIP_ID:
2765 case LAN9371_CHIP_ID:
2766 case LAN9372_CHIP_ID:
2767 case LAN9373_CHIP_ID:
2768 case LAN9374_CHIP_ID:
2769 dev->chip_id = id32;
2770 break;
2771 case KSZ9893_CHIP_ID:
2772 ret = ksz_read8(dev, REG_CHIP_ID4,
2773 &id4);
2774 if (ret)
2775 return ret;
2776
2777 if (id4 == SKU_ID_KSZ8563)
2778 dev->chip_id = KSZ8563_CHIP_ID;
2779 else
2780 dev->chip_id = KSZ9893_CHIP_ID;
2781
2782 break;
2783 default:
2784 dev_err(dev->dev,
2785 "unsupported switch detected %x)\n", id32);
2786 return -ENODEV;
2787 }
2788 }
2789 return 0;
2790 }
2791
2792 static const struct dsa_switch_ops ksz_switch_ops = {
2793 .get_tag_protocol = ksz_get_tag_protocol,
2794 .get_phy_flags = ksz_get_phy_flags,
2795 .setup = ksz_setup,
2796 .teardown = ksz_teardown,
2797 .phy_read = ksz_phy_read16,
2798 .phy_write = ksz_phy_write16,
2799 .phylink_get_caps = ksz_phylink_get_caps,
2800 .phylink_mac_config = ksz_phylink_mac_config,
2801 .phylink_mac_link_up = ksz_phylink_mac_link_up,
2802 .phylink_mac_link_down = ksz_mac_link_down,
2803 .port_enable = ksz_enable_port,
2804 .set_ageing_time = ksz_set_ageing_time,
2805 .get_strings = ksz_get_strings,
2806 .get_ethtool_stats = ksz_get_ethtool_stats,
2807 .get_sset_count = ksz_sset_count,
2808 .port_bridge_join = ksz_port_bridge_join,
2809 .port_bridge_leave = ksz_port_bridge_leave,
2810 .port_stp_state_set = ksz_port_stp_state_set,
2811 .port_pre_bridge_flags = ksz_port_pre_bridge_flags,
2812 .port_bridge_flags = ksz_port_bridge_flags,
2813 .port_fast_age = ksz_port_fast_age,
2814 .port_vlan_filtering = ksz_port_vlan_filtering,
2815 .port_vlan_add = ksz_port_vlan_add,
2816 .port_vlan_del = ksz_port_vlan_del,
2817 .port_fdb_dump = ksz_port_fdb_dump,
2818 .port_fdb_add = ksz_port_fdb_add,
2819 .port_fdb_del = ksz_port_fdb_del,
2820 .port_mdb_add = ksz_port_mdb_add,
2821 .port_mdb_del = ksz_port_mdb_del,
2822 .port_mirror_add = ksz_port_mirror_add,
2823 .port_mirror_del = ksz_port_mirror_del,
2824 .get_stats64 = ksz_get_stats64,
2825 .get_pause_stats = ksz_get_pause_stats,
2826 .port_change_mtu = ksz_change_mtu,
2827 .port_max_mtu = ksz_max_mtu,
2828 };
2829
ksz_switch_alloc(struct device * base,void * priv)2830 struct ksz_device *ksz_switch_alloc(struct device *base, void *priv)
2831 {
2832 struct dsa_switch *ds;
2833 struct ksz_device *swdev;
2834
2835 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2836 if (!ds)
2837 return NULL;
2838
2839 ds->dev = base;
2840 ds->num_ports = DSA_MAX_PORTS;
2841 ds->ops = &ksz_switch_ops;
2842
2843 swdev = devm_kzalloc(base, sizeof(*swdev), GFP_KERNEL);
2844 if (!swdev)
2845 return NULL;
2846
2847 ds->priv = swdev;
2848 swdev->dev = base;
2849
2850 swdev->ds = ds;
2851 swdev->priv = priv;
2852
2853 return swdev;
2854 }
2855 EXPORT_SYMBOL(ksz_switch_alloc);
2856
ksz_parse_rgmii_delay(struct ksz_device * dev,int port_num,struct device_node * port_dn)2857 static void ksz_parse_rgmii_delay(struct ksz_device *dev, int port_num,
2858 struct device_node *port_dn)
2859 {
2860 phy_interface_t phy_mode = dev->ports[port_num].interface;
2861 int rx_delay = -1, tx_delay = -1;
2862
2863 if (!phy_interface_mode_is_rgmii(phy_mode))
2864 return;
2865
2866 of_property_read_u32(port_dn, "rx-internal-delay-ps", &rx_delay);
2867 of_property_read_u32(port_dn, "tx-internal-delay-ps", &tx_delay);
2868
2869 if (rx_delay == -1 && tx_delay == -1) {
2870 dev_warn(dev->dev,
2871 "Port %d interpreting RGMII delay settings based on \"phy-mode\" property, "
2872 "please update device tree to specify \"rx-internal-delay-ps\" and "
2873 "\"tx-internal-delay-ps\"",
2874 port_num);
2875
2876 if (phy_mode == PHY_INTERFACE_MODE_RGMII_RXID ||
2877 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2878 rx_delay = 2000;
2879
2880 if (phy_mode == PHY_INTERFACE_MODE_RGMII_TXID ||
2881 phy_mode == PHY_INTERFACE_MODE_RGMII_ID)
2882 tx_delay = 2000;
2883 }
2884
2885 if (rx_delay < 0)
2886 rx_delay = 0;
2887 if (tx_delay < 0)
2888 tx_delay = 0;
2889
2890 dev->ports[port_num].rgmii_rx_val = rx_delay;
2891 dev->ports[port_num].rgmii_tx_val = tx_delay;
2892 }
2893
ksz_switch_register(struct ksz_device * dev)2894 int ksz_switch_register(struct ksz_device *dev)
2895 {
2896 const struct ksz_chip_data *info;
2897 struct device_node *port, *ports;
2898 phy_interface_t interface;
2899 unsigned int port_num;
2900 int ret;
2901 int i;
2902
2903 if (dev->pdata)
2904 dev->chip_id = dev->pdata->chip_id;
2905
2906 dev->reset_gpio = devm_gpiod_get_optional(dev->dev, "reset",
2907 GPIOD_OUT_LOW);
2908 if (IS_ERR(dev->reset_gpio))
2909 return PTR_ERR(dev->reset_gpio);
2910
2911 if (dev->reset_gpio) {
2912 gpiod_set_value_cansleep(dev->reset_gpio, 1);
2913 usleep_range(10000, 12000);
2914 gpiod_set_value_cansleep(dev->reset_gpio, 0);
2915 msleep(100);
2916 }
2917
2918 mutex_init(&dev->dev_mutex);
2919 mutex_init(&dev->regmap_mutex);
2920 mutex_init(&dev->alu_mutex);
2921 mutex_init(&dev->vlan_mutex);
2922
2923 ret = ksz_switch_detect(dev);
2924 if (ret)
2925 return ret;
2926
2927 info = ksz_lookup_info(dev->chip_id);
2928 if (!info)
2929 return -ENODEV;
2930
2931 /* Update the compatible info with the probed one */
2932 dev->info = info;
2933
2934 dev_info(dev->dev, "found switch: %s, rev %i\n",
2935 dev->info->dev_name, dev->chip_rev);
2936
2937 ret = ksz_check_device_id(dev);
2938 if (ret)
2939 return ret;
2940
2941 dev->dev_ops = dev->info->ops;
2942
2943 ret = dev->dev_ops->init(dev);
2944 if (ret)
2945 return ret;
2946
2947 dev->ports = devm_kzalloc(dev->dev,
2948 dev->info->port_cnt * sizeof(struct ksz_port),
2949 GFP_KERNEL);
2950 if (!dev->ports)
2951 return -ENOMEM;
2952
2953 for (i = 0; i < dev->info->port_cnt; i++) {
2954 spin_lock_init(&dev->ports[i].mib.stats64_lock);
2955 mutex_init(&dev->ports[i].mib.cnt_mutex);
2956 dev->ports[i].mib.counters =
2957 devm_kzalloc(dev->dev,
2958 sizeof(u64) * (dev->info->mib_cnt + 1),
2959 GFP_KERNEL);
2960 if (!dev->ports[i].mib.counters)
2961 return -ENOMEM;
2962
2963 dev->ports[i].ksz_dev = dev;
2964 dev->ports[i].num = i;
2965 }
2966
2967 /* set the real number of ports */
2968 dev->ds->num_ports = dev->info->port_cnt;
2969
2970 /* Host port interface will be self detected, or specifically set in
2971 * device tree.
2972 */
2973 for (port_num = 0; port_num < dev->info->port_cnt; ++port_num)
2974 dev->ports[port_num].interface = PHY_INTERFACE_MODE_NA;
2975 if (dev->dev->of_node) {
2976 ret = of_get_phy_mode(dev->dev->of_node, &interface);
2977 if (ret == 0)
2978 dev->compat_interface = interface;
2979 ports = of_get_child_by_name(dev->dev->of_node, "ethernet-ports");
2980 if (!ports)
2981 ports = of_get_child_by_name(dev->dev->of_node, "ports");
2982 if (ports) {
2983 for_each_available_child_of_node(ports, port) {
2984 if (of_property_read_u32(port, "reg",
2985 &port_num))
2986 continue;
2987 if (!(dev->port_mask & BIT(port_num))) {
2988 of_node_put(port);
2989 of_node_put(ports);
2990 return -EINVAL;
2991 }
2992 of_get_phy_mode(port,
2993 &dev->ports[port_num].interface);
2994
2995 ksz_parse_rgmii_delay(dev, port_num, port);
2996 }
2997 of_node_put(ports);
2998 }
2999 dev->synclko_125 = of_property_read_bool(dev->dev->of_node,
3000 "microchip,synclko-125");
3001 dev->synclko_disable = of_property_read_bool(dev->dev->of_node,
3002 "microchip,synclko-disable");
3003 if (dev->synclko_125 && dev->synclko_disable) {
3004 dev_err(dev->dev, "inconsistent synclko settings\n");
3005 return -EINVAL;
3006 }
3007 }
3008
3009 ret = dsa_register_switch(dev->ds);
3010 if (ret) {
3011 dev->dev_ops->exit(dev);
3012 return ret;
3013 }
3014
3015 /* Read MIB counters every 30 seconds to avoid overflow. */
3016 dev->mib_read_interval = msecs_to_jiffies(5000);
3017
3018 /* Start the MIB timer. */
3019 schedule_delayed_work(&dev->mib_read, 0);
3020
3021 return ret;
3022 }
3023 EXPORT_SYMBOL(ksz_switch_register);
3024
ksz_switch_remove(struct ksz_device * dev)3025 void ksz_switch_remove(struct ksz_device *dev)
3026 {
3027 /* timer started */
3028 if (dev->mib_read_interval) {
3029 dev->mib_read_interval = 0;
3030 cancel_delayed_work_sync(&dev->mib_read);
3031 }
3032
3033 dev->dev_ops->exit(dev);
3034 dsa_unregister_switch(dev->ds);
3035
3036 if (dev->reset_gpio)
3037 gpiod_set_value_cansleep(dev->reset_gpio, 1);
3038
3039 }
3040 EXPORT_SYMBOL(ksz_switch_remove);
3041
3042 MODULE_AUTHOR("Woojung Huh <Woojung.Huh@microchip.com>");
3043 MODULE_DESCRIPTION("Microchip KSZ Series Switch DSA Driver");
3044 MODULE_LICENSE("GPL");
3045