Searched refs:shadow_regs (Results 1 – 5 of 5) sorted by relevance
70 u8 shadow_regs[MAX8660_N_REGS]; /* as chip is write only */ member80 u8 reg_val = (max8660->shadow_regs[reg] & mask) | val; in max8660_write()88 max8660->shadow_regs[reg] = reg_val; in max8660_write()101 u8 val = max8660->shadow_regs[MAX8660_OVER1]; in max8660_dcdc_is_enabled()127 u8 selector = max8660->shadow_regs[reg]; in max8660_dcdc_get_voltage_sel()166 u8 selector = max8660->shadow_regs[MAX8660_MDTV2]; in max8660_ldo5_get_voltage_sel()199 u8 val = max8660->shadow_regs[MAX8660_OVER2]; in max8660_ldo67_is_enabled()225 u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf; in max8660_ldo67_get_voltage_sel()412 max8660->shadow_regs[MAX8660_OVER1] = 5; in max8660_probe()424 max8660->shadow_regs[MAX8660_ADTV1] = in max8660_probe()[all …]
703 struct shadow_regs *shadow_regs; member
122 ha->shadow_regs->req_q_out = cpu_to_le32(0); in qla4xxx_init_rings()123 ha->shadow_regs->rsp_q_in = cpu_to_le32(0); in qla4xxx_init_rings()
249 struct shadow_regs { struct
4192 ha->shadow_regs = NULL; in qla4xxx_mem_free()4240 sizeof(struct shadow_regs) + in qla4xxx_mem_alloc()4272 ha->shadow_regs = (struct shadow_regs *) (ha->queues + align + in qla4xxx_mem_alloc()5720 return (uint16_t)le32_to_cpu(ha->shadow_regs->req_q_out); in qla4xxx_rd_shdw_req_q_out()5730 return (uint16_t)le32_to_cpu(ha->shadow_regs->rsp_q_in); in qla4xxx_rd_shdw_rsp_q_in()