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Searched refs:slice (Results 1 – 25 of 37) sorted by relevance

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/drivers/staging/media/sunxi/cedrus/
Dcedrus_vp8.c526 const struct v4l2_ctrl_vp8_frame *slice) in cedrus_read_header() argument
530 if (V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) { in cedrus_read_header()
554 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) in cedrus_read_header()
559 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) in cedrus_read_header()
569 if (!V4L2_VP8_FRAME_IS_KEY_FRAME(slice)) { in cedrus_read_header()
594 static void cedrus_vp8_update_probs(const struct v4l2_ctrl_vp8_frame *slice, in cedrus_vp8_update_probs() argument
599 memcpy(&prob_table[0x1008], slice->entropy.y_mode_probs, in cedrus_vp8_update_probs()
600 sizeof(slice->entropy.y_mode_probs)); in cedrus_vp8_update_probs()
601 memcpy(&prob_table[0x1010], slice->entropy.uv_mode_probs, in cedrus_vp8_update_probs()
602 sizeof(slice->entropy.uv_mode_probs)); in cedrus_vp8_update_probs()
[all …]
Dcedrus_h264.c217 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; in cedrus_write_ref_list0() local
220 slice->ref_pic_list0, in cedrus_write_ref_list0()
221 slice->num_ref_idx_l0_active_minus1 + 1, in cedrus_write_ref_list0()
228 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; in cedrus_write_ref_list1() local
231 slice->ref_pic_list1, in cedrus_write_ref_list1()
232 slice->num_ref_idx_l1_active_minus1 + 1, in cedrus_write_ref_list1()
325 const struct v4l2_ctrl_h264_slice_params *slice = run->h264.slice_params; in cedrus_set_params() local
369 cedrus_skip_bits(dev, slice->header_bit_size); in cedrus_set_params()
371 if (V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice)) in cedrus_set_params()
374 if ((slice->slice_type == V4L2_H264_SLICE_TYPE_P) || in cedrus_set_params()
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/drivers/misc/eeprom/
Dmax6875.c54 static void max6875_update_slice(struct i2c_client *client, int slice) in max6875_update_slice() argument
60 if (slice >= USER_EEPROM_SLICES) in max6875_update_slice()
65 buf = &data->data[slice << SLICE_BITS]; in max6875_update_slice()
67 if (!(data->valid & (1 << slice)) || in max6875_update_slice()
68 time_after(jiffies, data->last_updated[slice])) { in max6875_update_slice()
70 dev_dbg(&client->dev, "Starting update of slice %u\n", slice); in max6875_update_slice()
72 data->valid &= ~(1 << slice); in max6875_update_slice()
74 addr = USER_EEPROM_BASE + (slice << SLICE_BITS); in max6875_update_slice()
99 data->last_updated[slice] = jiffies; in max6875_update_slice()
100 data->valid |= (1 << slice); in max6875_update_slice()
[all …]
Deeprom.c42 static void eeprom_update_client(struct i2c_client *client, u8 slice) in eeprom_update_client() argument
49 if (!(data->valid & (1 << slice)) || in eeprom_update_client()
50 time_after(jiffies, data->last_updated[slice] + 300 * HZ)) { in eeprom_update_client()
51 dev_dbg(&client->dev, "Starting eeprom update, slice %u\n", slice); in eeprom_update_client()
54 for (i = slice << 5; i < (slice + 1) << 5; i += 32) in eeprom_update_client()
60 for (i = slice << 5; i < (slice + 1) << 5; i += 2) { in eeprom_update_client()
68 data->last_updated[slice] = jiffies; in eeprom_update_client()
69 data->valid |= (1 << slice); in eeprom_update_client()
81 u8 slice; in eeprom_read() local
84 for (slice = off >> 5; slice <= (off + count - 1) >> 5; slice++) in eeprom_read()
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/drivers/gpu/drm/omapdrm/
Dtcm.h222 static inline void tcm_slice(struct tcm_area *parent, struct tcm_area *slice) in tcm_slice() argument
224 *slice = *parent; in tcm_slice()
227 if (slice->tcm && !slice->is2d && in tcm_slice()
228 slice->p0.y != slice->p1.y && in tcm_slice()
229 (slice->p0.x || (slice->p1.x != slice->tcm->width - 1))) { in tcm_slice()
231 slice->p1.x = slice->tcm->width - 1; in tcm_slice()
232 slice->p1.y = (slice->p0.x) ? slice->p0.y : slice->p1.y - 1; in tcm_slice()
235 parent->p0.y = slice->p1.y + 1; in tcm_slice()
Domap_dmm_tiler.c463 struct tcm_area slice, area_s; in fill() local
485 tcm_for_each_slice(slice, *area, area_s) { in fill()
487 .x0 = slice.p0.x, .y0 = slice.p0.y, in fill()
488 .x1 = slice.p1.x, .y1 = slice.p1.y, in fill()
493 roll += tcm_sizeof(slice); in fill()
/drivers/hid/surface-hid/
Dsurface_hid.c45 struct surface_hid_buffer_slice *slice; in ssam_hid_get_descriptor() local
70 slice = (struct surface_hid_buffer_slice *)buffer; in ssam_hid_get_descriptor()
71 slice->entry = entry; in ssam_hid_get_descriptor()
72 slice->end = 0; in ssam_hid_get_descriptor()
77 while (!slice->end && offset < len) { in ssam_hid_get_descriptor()
78 put_unaligned_le32(offset, &slice->offset); in ssam_hid_get_descriptor()
79 put_unaligned_le32(length, &slice->length); in ssam_hid_get_descriptor()
84 sizeof(*slice)); in ssam_hid_get_descriptor()
88 offset = get_unaligned_le32(&slice->offset); in ssam_hid_get_descriptor()
89 length = get_unaligned_le32(&slice->length); in ssam_hid_get_descriptor()
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/drivers/gpu/drm/i915/gt/
Dintel_gt_regs.h45 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) argument
50 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) argument
404 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) argument
405 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) argument
460 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) argument
461 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ argument
462 ((slice) % 3) * 0x4)
465 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) argument
467 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) argument
468 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ argument
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Dintel_sseu.h122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
132 return sseu->subslice_mask.hsw[slice] & BIT(subslice); in intel_sseu_has_subslice()
156 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice);
Dintel_sseu.c37 intel_sseu_get_hsw_subslices(const struct sseu_dev_info *sseu, u8 slice) in intel_sseu_get_hsw_subslices() argument
40 if (WARN_ON(slice >= sseu->max_slices)) in intel_sseu_get_hsw_subslices()
43 return sseu->subslice_mask.hsw[slice]; in intel_sseu_get_hsw_subslices()
46 static u16 sseu_get_eus(const struct sseu_dev_info *sseu, int slice, in sseu_get_eus() argument
50 WARN_ON(slice > 0); in sseu_get_eus()
53 return sseu->eu_mask.hsw[slice][subslice]; in sseu_get_eus()
57 static void sseu_set_eus(struct sseu_dev_info *sseu, int slice, int subslice, in sseu_set_eus() argument
62 GEM_WARN_ON(slice > 0); in sseu_set_eus()
65 sseu->eu_mask.hsw[slice][subslice] = eu_mask; in sseu_set_eus()
Dintel_workarounds.c941 unsigned int slice, subslice; in gen9_wa_init_mcr() local
957 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
958 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
959 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
967 mcr = GEN8_MCR_SLICE(slice) | GEN8_MCR_SUBSLICE(subslice); in gen9_wa_init_mcr()
970 drm_dbg(&i915->drm, "MCR slice:%d/subslice:%d = %x\n", slice, subslice, mcr); in gen9_wa_init_mcr()
1069 unsigned int slice, unsigned int subslice) in __set_mcr_steering() argument
1073 mcr = GEN11_MCR_SLICE(slice) | GEN11_MCR_SUBSLICE(subslice); in __set_mcr_steering()
1080 unsigned int slice, unsigned int subslice) in __add_mcr_wa() argument
1084 __set_mcr_steering(wal, GEN8_MCR_SELECTOR, slice, subslice); in __add_mcr_wa()
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/drivers/gpu/drm/i915/
Di915_sysfs.c69 int slice = (int)(uintptr_t)attr->private; in i915_l3_read() local
81 if (i915->l3_parity.remap_info[slice]) in i915_l3_read()
83 i915->l3_parity.remap_info[slice] + offset / sizeof(u32), in i915_l3_read()
97 int slice = (int)(uintptr_t)attr->private; in i915_l3_write() local
115 if (i915->l3_parity.remap_info[slice]) { in i915_l3_write()
117 remap_info = i915->l3_parity.remap_info[slice]; in i915_l3_write()
119 i915->l3_parity.remap_info[slice] = remap_info; in i915_l3_write()
127 ctx->remap_slice |= BIT(slice); in i915_l3_write()
/drivers/misc/cxl/
Dmain.c66 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe); in _cxl_slbia()
81 int card, slice, id; in cxl_slbia_core() local
89 for (slice = 0; slice < adapter->slices; slice++) { in cxl_slbia_core()
90 afu = adapter->afu[slice]; in cxl_slbia_core()
244 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice) in cxl_alloc_afu() argument
254 afu->slice = slice; in cxl_alloc_afu()
Dtrace.h76 __entry->afu = ctx->afu->slice;
105 __entry->afu = ctx->afu->slice;
145 __entry->afu = ctx->afu->slice;
178 __entry->afu = ctx->afu->slice;
212 __entry->afu = ctx->afu->slice;
243 __entry->afu = ctx->afu->slice;
270 __entry->afu = ctx->afu->slice;
299 __entry->afu = ctx->afu->slice;
331 __entry->afu = ctx->afu->slice;
360 __entry->afu = ctx->afu->slice;
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Dpci.c789 p1n_base = p1_base(dev) + 0x10000 + (afu->slice * p1n_size); in pci_map_slice_regs()
790 p2n_base = p2_base(dev) + (afu->slice * p2n_size); in pci_map_slice_regs()
791 afu->psn_phys = p2_base(dev) + (adapter->native->ps_off + (afu->slice * adapter->ps_size)); in pci_map_slice_regs()
792 …afu_desc = p2_base(dev) + adapter->native->afu_desc_off + (afu->slice * adapter->native->afu_desc_… in pci_map_slice_regs()
1137 static int pci_init_afu(struct cxl *adapter, int slice, struct pci_dev *dev) in pci_init_afu() argument
1142 afu = cxl_alloc_afu(adapter, slice); in pci_init_afu()
1152 rc = dev_set_name(&afu->dev, "afu%i.%i", adapter->adapter_num, slice); in pci_init_afu()
1173 adapter->afu[afu->slice] = afu; in pci_init_afu()
1208 afu->adapter->afu[afu->slice] = NULL; in cxl_pci_remove_afu()
1562 int slice; in cxl_stop_trace_psl8() local
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Dguest.c391 pr_devel("Disabling AFU(%d) interrupts\n", ctx->afu->slice); in disable_afu_irqs()
407 pr_devel("Enabling AFU(%d) interrupts\n", ctx->afu->slice); in enable_afu_irqs()
739 dev_info(&afu->dev, "Activating AFU(%d) directed mode\n", afu->slice); in activate_afu_directed()
780 dev_info(&afu->dev, "Deactivating AFU(%d) directed mode\n", afu->slice); in deactivate_afu_directed()
807 pr_devel("AFU(%d) reset request\n", afu->slice); in guest_afu_reset()
815 afu->slice); in guest_map_slice_regs()
838 pr_devel("AFU(%d) update state to %#x\n", afu->slice, cur_state); in afu_update_state()
875 afu->slice, cur_state); in afu_update_state()
923 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np) in cxl_guest_init_afu() argument
929 pr_devel("in %s - AFU(%d)\n", __func__, slice); in cxl_guest_init_afu()
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Dfile.c28 #define CXL_AFU_MINOR_D(afu) (CXL_CARD_MINOR(afu->adapter) + 1 + (3 * afu->slice))
49 int slice = CXL_DEVT_AFU(inode->i_rdev); in __afu_open() local
52 pr_devel("afu_open afu%i.%i\n", slice, adapter_num); in __afu_open()
57 if (slice > adapter->slices) in __afu_open()
61 if (!(afu = adapter->afu[slice])) { in __afu_open()
297 afuid.afu_offset = ctx->afu->slice; in afu_ioctl_get_afu_id()
579 "afu%i.%i%s", afu->adapter->adapter_num, afu->slice, postfix); in cxl_add_chardev()
Dof.c458 int slice = 0, slice_ok = 0; in cxl_of_probe() local
475 if ((ret = cxl_guest_init_afu(adapter, slice, afu_np))) in cxl_of_probe()
477 slice, ret); in cxl_of_probe()
480 slice++; in cxl_of_probe()
/drivers/hte/
Dhte-tegra194.c106 int slice; member
256 if (m[eid].slice == NV_AON_SLICE_INVALID) in tegra_hte_map_to_line_id()
259 *mapped = (m[eid].slice << 5) + m[eid].bit_index; in tegra_hte_map_to_line_id()
341 u32 slice, sl_bit_shift, line_bit, val, reg; in tegra_hte_en_dis_common() local
358 slice = line_id >> sl_bit_shift; in tegra_hte_en_dis_common()
360 reg = (slice << sl_bit_shift) + HTE_SLICE0_TETEN; in tegra_hte_en_dis_common()
362 spin_lock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
364 if (test_bit(HTE_SUSPEND, &gs->sl[slice].flags)) { in tegra_hte_en_dis_common()
365 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
377 spin_unlock(&gs->sl[slice].s_lock); in tegra_hte_en_dis_common()
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/drivers/gpu/drm/i915/display/
Dintel_bw.c780 enum dbuf_slice slice; in intel_bw_state_changed() local
782 for_each_dbuf_slice(i915, slice) { in intel_bw_state_changed()
783 if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] || in intel_bw_state_changed()
784 old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice]) in intel_bw_state_changed()
804 enum dbuf_slice slice; in skl_plane_calc_dbuf_bw() local
810 for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) { in skl_plane_calc_dbuf_bw()
811 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate); in skl_plane_calc_dbuf_bw()
812 crtc_bw->active_planes[slice] |= BIT(plane_id); in skl_plane_calc_dbuf_bw()
854 enum dbuf_slice slice; in intel_bw_dbuf_min_cdclk() local
856 for_each_dbuf_slice(i915, slice) { in intel_bw_dbuf_min_cdclk()
[all …]
Dintel_display_power.c1022 enum dbuf_slice slice, bool enable) in gen9_dbuf_slice_set() argument
1024 i915_reg_t reg = DBUF_CTL_S(slice); in gen9_dbuf_slice_set()
1035 slice, str_enable_disable(enable)); in gen9_dbuf_slice_set()
1043 enum dbuf_slice slice; in gen9_dbuf_slices_update() local
1061 for_each_dbuf_slice(dev_priv, slice) in gen9_dbuf_slices_update()
1062 gen9_dbuf_slice_set(dev_priv, slice, req_slices & BIT(slice)); in gen9_dbuf_slices_update()
1089 enum dbuf_slice slice; in gen12_dbuf_slices_config() local
1094 for_each_dbuf_slice(dev_priv, slice) in gen12_dbuf_slices_config()
1095 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
/drivers/net/ethernet/myricom/myri10ge/
Dmyri10ge.c1796 int slice; in myri10ge_get_ethtool_stats() local
1837 for (slice = 0; slice < mgp->num_slices; slice++) { in myri10ge_get_ethtool_stats()
1838 ss = &mgp->ss[slice]; in myri10ge_get_ethtool_stats()
1839 data[i++] = slice; in myri10ge_get_ethtool_stats()
1943 int i, slice, status; in myri10ge_allocate_rings() local
1947 slice = ss - mgp->ss; in myri10ge_allocate_rings()
1948 cmd.data0 = slice; in myri10ge_allocate_rings()
1951 cmd.data0 = slice; in myri10ge_allocate_rings()
2022 slice, ss->rx_small.fill_cnt); in myri10ge_allocate_rings()
2029 slice, ss->rx_big.fill_cnt); in myri10ge_allocate_rings()
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/drivers/gpu/drm/nouveau/nvkm/subdev/ltc/
Dgm107.c110 const u32 slice = nvkm_rd32(device, 0x17e280) >> 28; in gm107_ltc_oneinit() local
117 ltc->lts_nr = slice; in gm107_ltc_oneinit()
Dgf100.c213 const u32 slice = nvkm_rd32(device, 0x17e8dc) >> 28; in gf100_ltc_oneinit() local
220 ltc->lts_nr = slice; in gf100_ltc_oneinit()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_capture.c288 int slice, subslice, iter, i, num_steer_regs, num_tot_regs = 0; in guc_capture_alloc_steered_lists_xe_lpd() local
304 for_each_ss_steering(iter, gt, slice, subslice) in guc_capture_alloc_steered_lists_xe_lpd()
321 for_each_ss_steering(iter, gt, slice, subslice) { in guc_capture_alloc_steered_lists_xe_lpd()
323 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); in guc_capture_alloc_steered_lists_xe_lpd()
348 int slice, subslice, i, iter, num_steer_regs, num_tot_regs = 0; in guc_capture_alloc_steered_lists_xe_hpg() local
365 for_each_ss_steering(iter, gt, slice, subslice) in guc_capture_alloc_steered_lists_xe_hpg()
382 for_each_ss_steering(iter, gt, slice, subslice) { in guc_capture_alloc_steered_lists_xe_hpg()
384 __fill_ext_reg(extarray, &xe_extregs[i], slice, subslice); in guc_capture_alloc_steered_lists_xe_hpg()
389 __fill_ext_reg(extarray, &xehpg_extregs[i], slice, subslice); in guc_capture_alloc_steered_lists_xe_hpg()

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