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Searched refs:spx5_wr (Results 1 – 11 of 11) sorted by relevance

/drivers/net/ethernet/microchip/sparx5/
Dsparx5_vlan.c18 spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); in sparx5_vlant_set_mask()
19 spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); in sparx5_vlant_set_mask()
20 spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); in sparx5_vlant_set_mask()
143 spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); in sparx5_pgid_clear()
144 spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); in sparx5_pgid_clear()
145 spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); in sparx5_pgid_clear()
166 spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); in sparx5_update_fwd()
167 spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); in sparx5_update_fwd()
168 spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); in sparx5_update_fwd()
178 spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); in sparx5_update_fwd()
[all …]
Dsparx5_fdma.c116 spx5_wr(((u64)rx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_rx_activate()
118 spx5_wr(((u64)rx->dma) >> 32, sparx5, FDMA_DCB_LLP1(rx->channel_id)); in sparx5_fdma_rx_activate()
121 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_RX_DCB_MAX_DBS) | in sparx5_fdma_rx_activate()
141 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_rx_activate()
162 spx5_wr(((u64)tx->dma) & GENMASK(31, 0), sparx5, in sparx5_fdma_tx_activate()
164 spx5_wr(((u64)tx->dma) >> 32, sparx5, FDMA_DCB_LLP1(tx->channel_id)); in sparx5_fdma_tx_activate()
167 spx5_wr(FDMA_CH_CFG_CH_DCB_DB_CNT_SET(FDMA_TX_DCB_MAX_DBS) | in sparx5_fdma_tx_activate()
177 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_ACTIVATE); in sparx5_fdma_tx_activate()
190 spx5_wr(BIT(rx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_rx_reload()
196 spx5_wr(BIT(tx->channel_id), sparx5, FDMA_CH_RELOAD); in sparx5_fdma_tx_reload()
[all …]
Dsparx5_packet.c26 spx5_wr(QS_XTR_FLUSH_FLUSH_SET(BIT(grp)), sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
32 spx5_wr(0, sparx5, QS_XTR_FLUSH); in sparx5_xtr_flush()
179 spx5_wr(QS_INJ_CTRL_SOF_SET(1) | in sparx5_inject()
185 spx5_wr(ifh[w], sparx5, QS_INJ_WR(grp)); in sparx5_inject()
192 spx5_wr(val, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
197 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
202 spx5_wr(QS_INJ_CTRL_GAP_SIZE_SET(1) | in sparx5_inject()
208 spx5_wr(0, sparx5, QS_INJ_WR(grp)); in sparx5_inject()
307 spx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
311 spx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) | in sparx5_manual_injection_mode()
[all …]
Dsparx5_mactable.c76 spx5_wr(mach, sparx5, LRN_MAC_ACCESS_CFG_0); in sparx5_mact_select()
77 spx5_wr(macl, sparx5, LRN_MAC_ACCESS_CFG_1); in sparx5_mact_select()
99 spx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(addr) | in sparx5_mact_learn()
104 spx5_wr(0, sparx5, LRN_MAC_ACCESS_CFG_3); in sparx5_mact_learn()
107 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LEARN) | in sparx5_mact_learn()
169 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1) | in sparx5_mact_getnext()
172 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET in sparx5_mact_getnext()
200 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_LOOKUP) | in sparx5_mact_find()
228 spx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(MAC_CMD_UNLEARN) | in sparx5_mact_forget()
443 spx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1), in sparx5_mact_pull_work()
[all …]
Dsparx5_main.c405 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
406 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
409 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
549 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
553 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
558 spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
559 spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
560 spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
561 spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
586 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
[all …]
Dsparx5_ptp.c426 spx5_wr((u32)tod_inc & 0xFFFFFFFF, sparx5, in sparx5_ptp_adjfine()
428 spx5_wr((u32)(tod_inc >> 32), sparx5, in sparx5_ptp_adjfine()
459 spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), in sparx5_ptp_settime64()
461 spx5_wr(lower_32_bits(ts->tv_sec), in sparx5_ptp_settime64()
463 spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); in sparx5_ptp_settime64()
536 spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), in sparx5_ptp_adjtime()
615 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
623 spx5_wr((u32)tod_adj & 0xFFFFFFFF, sparx5, in sparx5_ptp_init()
625 spx5_wr((u32)(tod_adj >> 32), sparx5, in sparx5_ptp_init()
634 spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); in sparx5_ptp_init()
Dsparx5_port.c89 spx5_wr(value, sparx5, DEV2G5_PCS1G_STICKY(portno)); in sparx5_get_dev2g5_status()
570 spx5_wr(DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(etype) | in sparx5_port_max_tags_set()
755 spx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1), in sparx5_port_pcs_low_set()
763 spx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(abil) | in sparx5_port_pcs_low_set()
770 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
889 spx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(tx_gap) | in sparx5_port_config_low_set()
902 spx5_wr(DEV2G5_MAC_ENA_CFG_RX_ENA | in sparx5_port_config_low_set()
1049 spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | in sparx5_port_init()
1066 spx5_wr(QSYS_ATOP_ATOP_SET(atop), in sparx5_port_init()
1071 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
[all …]
Dsparx5_calendar.c217 spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); in sparx5_config_auto_calendar()
229 spx5_wr(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(12), in sparx5_config_auto_calendar()
539 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), in sparx5_dsm_calendar_update()
552 spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), in sparx5_dsm_calendar_update()
Dsparx5_qos.c33 spx5_wr(HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(leak_time), sparx5, in sparx5_lg_set_leak_time()
195 spx5_wr(HSCH_SE_CONNECT_SE_LEAK_LINK_SET(idx_next), sparx5, in sparx5_lg_conf_set()
289 spx5_wr(HSCH_CIR_CFG_CIR_RATE_SET(sh->rate) | in sparx5_shaper_conf_set()
Dsparx5_main.h484 static inline void spx5_wr(u32 val, struct sparx5 *sparx5, in spx5_wr() function
Dsparx5_ethtool.c210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
1172 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno) | in sparx5_config_port_stats()