| /drivers/gpu/drm/i915/gt/ |
| D | intel_sseu.c | 13 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices, in intel_sseu_set_info() argument
16 sseu->max_slices = max_slices; in intel_sseu_set_info()
17 sseu->max_subslices = max_subslices; in intel_sseu_set_info()
18 sseu->max_eus_per_subslice = max_eus_per_subslice; in intel_sseu_set_info()
22 intel_sseu_subslice_total(const struct sseu_dev_info *sseu) in intel_sseu_subslice_total() argument
26 if (sseu->has_xehp_dss) in intel_sseu_subslice_total()
27 return bitmap_weight(sseu->subslice_mask.xehp, in intel_sseu_subslice_total()
28 XEHP_BITMAP_BITS(sseu->subslice_mask)); in intel_sseu_subslice_total()
30 for (i = 0; i < ARRAY_SIZE(sseu->subslice_mask.hsw); i++) in intel_sseu_subslice_total()
31 total += hweight8(sseu->subslice_mask.hsw[i]); in intel_sseu_subslice_total()
[all …]
|
| D | intel_sseu_debugfs.c | 16 struct sseu_dev_info *sseu) in cherryview_sseu_device_status() argument
36 sseu->slice_mask = BIT(0); in cherryview_sseu_device_status()
37 sseu->subslice_mask.hsw[0] |= BIT(ss); in cherryview_sseu_device_status()
42 sseu->eu_total += eu_cnt; in cherryview_sseu_device_status()
43 sseu->eu_per_subslice = max_t(unsigned int, in cherryview_sseu_device_status()
44 sseu->eu_per_subslice, eu_cnt); in cherryview_sseu_device_status()
50 struct sseu_dev_info *sseu) in gen11_sseu_device_status() argument
58 for (s = 0; s < info->sseu.max_slices; s++) { in gen11_sseu_device_status()
82 for (s = 0; s < info->sseu.max_slices; s++) { in gen11_sseu_device_status()
87 sseu->slice_mask |= BIT(s); in gen11_sseu_device_status()
[all …]
|
| D | intel_sseu.h | 109 intel_sseu_from_device_info(const struct sseu_dev_info *sseu) in intel_sseu_from_device_info() argument
112 .slice_mask = sseu->slice_mask, in intel_sseu_from_device_info()
113 .subslice_mask = sseu->subslice_mask.hsw[0], in intel_sseu_from_device_info()
114 .min_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
115 .max_eus_per_subslice = sseu->max_eus_per_subslice, in intel_sseu_from_device_info()
122 intel_sseu_has_subslice(const struct sseu_dev_info *sseu, int slice, in intel_sseu_has_subslice() argument
125 if (slice >= sseu->max_slices || in intel_sseu_has_subslice()
126 subslice >= sseu->max_subslices) in intel_sseu_has_subslice()
129 if (sseu->has_xehp_dss) in intel_sseu_has_subslice()
130 return test_bit(subslice, sseu->subslice_mask.xehp); in intel_sseu_has_subslice()
[all …]
|
| D | intel_context_sseu.c | 18 const struct intel_sseu sseu) in gen8_emit_rpcs_config() argument
33 *cs++ = intel_sseu_make_rpcs(rq->engine->gt, &sseu); in gen8_emit_rpcs_config()
41 gen8_modify_rpcs(struct intel_context *ce, const struct intel_sseu sseu) in gen8_modify_rpcs() argument
66 ret = gen8_emit_rpcs_config(rq, ce, sseu); in gen8_modify_rpcs()
76 const struct intel_sseu sseu) in intel_context_reconfigure_sseu() argument
87 if (!memcmp(&ce->sseu, &sseu, sizeof(sseu))) in intel_context_reconfigure_sseu()
90 ret = gen8_modify_rpcs(ce, sseu); in intel_context_reconfigure_sseu()
92 ce->sseu = sseu; in intel_context_reconfigure_sseu()
|
| D | intel_gt_mcr.h | 45 intel_sseu_has_subslice(&(gt_)->info.sseu, 0, ss_) : \
46 intel_sseu_has_subslice(&(gt_)->info.sseu, group_, instance_))
|
| D | intel_workarounds.c | 433 if (!is_power_of_2(gt->info.sseu.subslice_7eu[i])) in skl_tune_iz_hashing()
442 ss = ffs(gt->info.sseu.subslice_7eu[i]) - 1; in skl_tune_iz_hashing()
940 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in gen9_wa_init_mcr() local
957 slice = ffs(sseu->slice_mask) - 1; in gen9_wa_init_mcr()
958 GEM_BUG_ON(slice >= ARRAY_SIZE(sseu->subslice_mask.hsw)); in gen9_wa_init_mcr()
959 subslice = ffs(intel_sseu_get_hsw_subslices(sseu, slice)); in gen9_wa_init_mcr()
1096 const struct sseu_dev_info *sseu = >->info.sseu; in icl_wa_init_mcr() local
1100 GEM_BUG_ON(hweight8(sseu->slice_mask) > 1); in icl_wa_init_mcr()
1111 subslice = __ffs(intel_sseu_get_hsw_subslices(sseu, 0)); in icl_wa_init_mcr()
1127 const struct sseu_dev_info *sseu = >->info.sseu; in xehp_init_mcr() local
[all …]
|
| D | intel_gt_types.h | 251 struct sseu_dev_info sseu; member
|
| D | intel_context_types.h | 170 struct intel_sseu sseu; member
|
| D | intel_context.c | 385 ce->sseu = engine->sseu; in intel_context_init()
|
| D | intel_context.h | 47 const struct intel_sseu sseu);
|
| D | intel_engine_types.h | 389 struct intel_sseu sseu; member
|
| D | intel_gt_mcr.c | 102 intel_slicemask_from_xehp_dssmask(gt->info.sseu.subslice_mask, in intel_gt_mcr_init()
|
| D | intel_engine_cs.c | 806 int ss_per_ccs = info->sseu.max_subslices / I915_MAX_CCS; in engine_mask_apply_compute_fuses()
816 ccs_mask = intel_slicemask_from_xehp_dssmask(info->sseu.compute_subslice_mask, in engine_mask_apply_compute_fuses()
1143 engine->sseu = in engine_setup_common()
1144 intel_sseu_from_device_info(&engine->gt->info.sseu); in engine_setup_common()
|
| D | intel_gt.c | 929 intel_sseu_dump(&info->sseu, p); in intel_gt_info_print()
|
| D | intel_lrc.c | 1414 intel_sseu_make_rpcs(engine->gt, &ce->sseu); in lrc_update_regs()
|
| D | intel_rps.c | 1235 switch (gt->info.sseu.eu_total) { in chv_rps_max_freq()
|
| /drivers/gpu/drm/i915/ |
| D | i915_query.c | 32 static int fill_topology_info(const struct sseu_dev_info *sseu, in fill_topology_info() argument
38 int ss_stride = GEN_SSEU_STRIDE(sseu->max_subslices); in fill_topology_info()
39 int eu_stride = GEN_SSEU_STRIDE(sseu->max_eus_per_subslice); in fill_topology_info()
42 BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); in fill_topology_info()
44 if (sseu->max_slices == 0) in fill_topology_info()
47 slice_length = sizeof(sseu->slice_mask); in fill_topology_info()
48 subslice_length = sseu->max_slices * ss_stride; in fill_topology_info()
49 eu_length = sseu->max_slices * sseu->max_subslices * eu_stride; in fill_topology_info()
59 topo.max_slices = sseu->max_slices; in fill_topology_info()
60 topo.max_subslices = sseu->max_subslices; in fill_topology_info()
[all …]
|
| D | i915_getparam.c | 18 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu; in i915_getparam_ioctl() local
76 value = intel_sseu_subslice_total(sseu); in i915_getparam_ioctl()
81 value = sseu->eu_total; in i915_getparam_ioctl()
98 value = sseu->min_eu_in_pool; in i915_getparam_ioctl()
155 value = sseu->slice_mask; in i915_getparam_ioctl()
165 value = intel_sseu_get_hsw_subslices(sseu, 0); in i915_getparam_ioctl()
|
| D | i915_perf_types.h | 417 struct intel_sseu sseu; member
|
| D | i915_perf.c | 366 struct intel_sseu sseu; member
2269 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu); in gen8_configure_context()
2413 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu); in oa_configure_all_contexts()
2813 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu; in get_default_sseu_config()
2983 perf->sseu = props->sseu; in i915_oa_stream_init()
3495 get_default_sseu_config(&props->sseu, props->engine); in i915_perf_open_ioctl_locked()
3750 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu); in read_properties_unlocked()
|
| /drivers/gpu/drm/i915/gem/ |
| D | i915_gem_context.c | 818 struct intel_sseu *sseu; in set_proto_ctx_sseu() local
854 sseu = &pe->sseu; in set_proto_ctx_sseu()
864 sseu = &pc->legacy_rcs_sseu; in set_proto_ctx_sseu()
867 ret = i915_gem_user_to_context_sseu(to_gt(i915), &user_sseu, sseu); in set_proto_ctx_sseu()
960 struct intel_sseu sseu) in intel_context_set_gem() argument
986 if (sseu.slice_mask && !WARN_ON(ce->engine->class != RENDER_CLASS)) in intel_context_set_gem()
987 ret = intel_context_reconfigure_sseu(ce, sseu); in intel_context_set_gem()
1111 struct intel_sseu sseu = {}; in default_engines() local
1130 sseu = rcs_sseu; in default_engines()
1132 ret = intel_context_set_gem(ce, ctx, sseu); in default_engines()
[all …]
|
| D | i915_gem_context_types.h | 125 struct intel_sseu sseu; member
|
| /drivers/gpu/drm/i915/gem/selftests/ |
| D | i915_gem_context.c | 1168 unsigned int slices = hweight32(ce->engine->sseu.slice_mask); in __sseu_finish()
1209 struct intel_sseu sseu) in __sseu_test() argument
1220 ret = intel_context_reconfigure_sseu(ce, sseu); in __sseu_test()
1225 hweight32(sseu.slice_mask), spin); in __sseu_test()
1270 if (hweight32(engine->sseu.slice_mask) < 2) in __igt_ctx_sseu()
1273 if (!engine->gt->info.sseu.has_slice_pg) in __igt_ctx_sseu()
1280 pg_sseu = engine->sseu; in __igt_ctx_sseu()
1283 ~(~0 << (hweight32(engine->sseu.subslice_mask) / 2)); in __igt_ctx_sseu()
1287 hweight32(engine->sseu.slice_mask), in __igt_ctx_sseu()
1301 ret = __sseu_test(name, flags, ce, obj, engine->sseu); in __igt_ctx_sseu()
[all …]
|
| /drivers/gpu/drm/i915/gt/uc/ |
| D | intel_guc_capture.c | 292 struct sseu_dev_info *sseu; in guc_capture_alloc_steered_lists_xe_lpd() local
303 sseu = >->info.sseu; in guc_capture_alloc_steered_lists_xe_lpd()
347 struct sseu_dev_info *sseu; in guc_capture_alloc_steered_lists_xe_hpg() local
364 sseu = >->info.sseu; in guc_capture_alloc_steered_lists_xe_hpg()
|
| D | intel_guc_ads.c | 749 hweight8(gt->info.sseu.slice_mask)); in __guc_ads_init()
|