| /drivers/cpuidle/ |
| D | dt_idle_genpd.c | 26 struct genpd_power_state *states, int state_count) in pd_parse_state_nodes() argument
32 ret = parse_state(to_of_node(states[i].fwnode), &state); in pd_parse_state_nodes()
42 states[i].data = state_buf; in pd_parse_state_nodes()
50 kfree(states[i].data); in pd_parse_state_nodes()
56 struct genpd_power_state **states, in pd_parse_states() argument
62 ret = of_genpd_parse_idle_states(np, states, state_count); in pd_parse_states()
67 ret = pd_parse_state_nodes(parse_state, *states, *state_count); in pd_parse_states()
69 kfree(*states); in pd_parse_states()
74 static void pd_free_states(struct genpd_power_state *states, in pd_free_states() argument
80 kfree(states[i].data); in pd_free_states()
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| D | cpuidle-riscv-sbi.c | 32 u32 *states; member
99 u32 *states = __this_cpu_read(sbi_cpuidle_data.states); in sbi_cpuidle_enter_state() local
100 u32 state = states[idx]; in sbi_cpuidle_enter_state()
114 u32 *states = data->states; in __sbi_enter_domain_idle_state() local
134 state = states[idx]; in __sbi_enter_domain_idle_state()
254 drv->states[state_count - 1].enter = sbi_enter_domain_idle_state; in sbi_dt_cpu_init_topology()
255 drv->states[state_count - 1].enter_s2idle = in sbi_dt_cpu_init_topology()
270 u32 *states; in sbi_cpuidle_dt_init_states() local
277 states = devm_kcalloc(dev, state_count, sizeof(*states), GFP_KERNEL); in sbi_cpuidle_dt_init_states()
278 if (!states) { in sbi_cpuidle_dt_init_states()
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| D | cpuidle-mvebu-v7.c | 36 if (drv->states[index].flags & MVEBU_V7_FLAG_DEEP_IDLE) in mvebu_v7_enter_idle()
50 .states[0] = ARM_CPUIDLE_WFI_STATE,
51 .states[1] = {
59 .states[2] = {
73 .states[0] = ARM_CPUIDLE_WFI_STATE,
74 .states[1] = {
88 .states[0] = ARM_CPUIDLE_WFI_STATE,
89 .states[1] = {
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| D | cpuidle-psci.c | 63 u32 *states = data->psci_states; in __psci_enter_domain_idle_state() local
86 state = states[idx]; in __psci_enter_domain_idle_state()
251 drv->states[state_count - 1].enter = psci_enter_domain_idle_state; in psci_dt_cpu_init_topology()
252 drv->states[state_count - 1].enter_s2idle = psci_enter_s2idle_domain_idle_state; in psci_dt_cpu_init_topology()
367 drv->states[0].enter = psci_enter_idle_state; in psci_idle_init_cpu()
368 drv->states[0].exit_latency = 1; in psci_idle_init_cpu()
369 drv->states[0].target_residency = 1; in psci_idle_init_cpu()
370 drv->states[0].power_usage = UINT_MAX; in psci_idle_init_cpu()
371 strcpy(drv->states[0].name, "WFI"); in psci_idle_init_cpu()
372 strcpy(drv->states[0].desc, "ARM WFI"); in psci_idle_init_cpu()
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| D | cpuidle.c | 74 if (drv->states[i].enter_dead) in cpuidle_play_dead()
75 return drv->states[i].enter_dead(dev, i); in cpuidle_play_dead()
90 struct cpuidle_state *s = &drv->states[i]; in find_deepest_state()
144 struct cpuidle_state *target_state = &drv->states[index]; in enter_s2idle_proper()
220 target_state = &drv->states[index]; in cpuidle_enter_state()
235 target_state = &drv->states[index]; in cpuidle_enter_state()
275 s64 diff, delay = drv->states[entered_state].exit_latency_ns; in cpuidle_enter_state()
289 if (diff < drv->states[entered_state].target_residency_ns) { in cpuidle_enter_state()
308 if (diff - delay >= drv->states[i].target_residency_ns) { in cpuidle_enter_state()
428 state_limit = drv->states[i].target_residency_ns; in cpuidle_poll_time()
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| D | cpuidle-big_little.c | 62 .states[0] = ARM_CPUIDLE_WFI_STATE,
63 .states[1] = {
83 .states[0] = ARM_CPUIDLE_WFI_STATE,
84 .states[1] = {
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| /drivers/regulator/ |
| D | gpio-regulator.c | 39 struct gpio_regulator_state *states; member
51 if (data->states[ptr].gpios == data->state) in gpio_regulator_get_value()
52 return data->states[ptr].value; in gpio_regulator_get_value()
65 if (data->states[ptr].value < best_val && in gpio_regulator_set_voltage()
66 data->states[ptr].value >= min_uV && in gpio_regulator_set_voltage()
67 data->states[ptr].value <= max_uV) { in gpio_regulator_set_voltage()
68 target = data->states[ptr].gpios; in gpio_regulator_set_voltage()
69 best_val = data->states[ptr].value; in gpio_regulator_set_voltage()
94 return data->states[selector].value; in gpio_regulator_list_voltage()
104 if (data->states[ptr].value > best_val && in gpio_regulator_set_current_limit()
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| D | irq_helpers.c | 107 stat = &rid->states[i]; in regulator_notifier_isr_work()
132 stat = &rid->states[i]; in regulator_notifier_isr_work()
214 rdev = rid->states[i].rdev; in regulator_notifier_isr()
240 stat = &rid->states[i]; in regulator_notifier_isr()
286 h->rdata.states = devm_kzalloc(dev, sizeof(*h->rdata.states) * in init_rdev_state()
288 if (!h->rdata.states) in init_rdev_state()
295 h->rdata.states[i].possible_errs = common_err; in init_rdev_state()
297 h->rdata.states[i].possible_errs |= *rdev_err++; in init_rdev_state()
298 h->rdata.states[i].rdev = *rdev++; in init_rdev_state()
309 if (h->rdata.states[i].possible_errs) in init_rdev_errors()
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| /drivers/cpuidle/governors/ |
| D | ladder.c | 40 struct ladder_device_state states[CPUIDLE_STATE_MAX]; member
55 ldev->states[old_idx].stats.promotion_count = 0; in ladder_do_selection()
56 ldev->states[old_idx].stats.demotion_count = 0; in ladder_do_selection()
72 int first_idx = drv->states[0].flags & CPUIDLE_FLAG_POLLING ? 1 : 0; in ladder_select_state()
82 last_state = &ldev->states[last_idx]; in ladder_select_state()
84 last_residency = dev->last_residency_ns - drv->states[last_idx].exit_latency_ns; in ladder_select_state()
90 drv->states[last_idx + 1].exit_latency_ns <= latency_req) { in ladder_select_state()
102 drv->states[last_idx].exit_latency_ns > latency_req)) { in ladder_select_state()
106 if (drv->states[i].exit_latency_ns <= latency_req) in ladder_select_state()
136 int first_idx = drv->states[0].flags & CPUIDLE_FLAG_POLLING ? 1 : 0; in ladder_enable_device()
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| D | menu.c | 294 ((data->next_timer_ns < drv->states[1].target_residency_ns || in menu_select()
295 latency_req < drv->states[1].exit_latency_ns) && in menu_select()
302 *stop_tick = !(drv->states[0].flags & CPUIDLE_FLAG_POLLING); in menu_select()
344 struct cpuidle_state *s = &drv->states[i]; in menu_select()
357 if ((drv->states[idx].flags & CPUIDLE_FLAG_POLLING) && in menu_select()
374 predicted_ns = drv->states[idx].target_residency_ns; in menu_select()
384 if (drv->states[idx].target_residency_ns < TICK_NSEC && in menu_select()
403 if (((drv->states[idx].flags & CPUIDLE_FLAG_POLLING) || in menu_select()
407 if (idx > 0 && drv->states[idx].target_residency_ns > delta_tick) { in menu_select()
419 if (drv->states[i].target_residency_ns <= delta_tick) in menu_select()
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| D | teo.c | 254 u64 lat_ns = drv->states[dev->last_state_idx].exit_latency_ns; in teo_update()
284 s64 target_residency_ns = drv->states[i].target_residency_ns; in teo_update()
331 return (drv->states[idx].target_residency_ns + in teo_middle_of_bin()
332 drv->states[idx+1].target_residency_ns) / 2; in teo_middle_of_bin()
351 (no_poll && drv->states[i].flags & CPUIDLE_FLAG_POLLING)) in teo_find_shallower_state()
355 if (drv->states[i].target_residency_ns <= duration_ns) in teo_find_shallower_state()
402 if (drv->states[1].target_residency_ns > duration_ns) in teo_select()
423 if ((!idx && !(drv->states[0].flags & CPUIDLE_FLAG_POLLING) && in teo_select()
441 struct cpuidle_state *s = &drv->states[i]; in teo_select()
585 if (((drv->states[idx].flags & CPUIDLE_FLAG_POLLING) || in teo_select()
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| /drivers/cpufreq/ |
| D | ia64-acpi-cpufreq.c | 97 if (value == data->acpi_data.states[i].status) in extract_clock()
98 return data->acpi_data.states[i].core_frequency; in extract_clock()
100 return data->acpi_data.states[i-1].core_frequency; in extract_clock()
159 value = (u32) data->acpi_data.states[state].control; in processor_set_freq()
254 if ((data->acpi_data.states[i].transition_latency * 1000) > in acpi_cpufreq_cpu_init()
257 data->acpi_data.states[i].transition_latency * 1000; in acpi_cpufreq_cpu_init()
266 data->acpi_data.states[i].core_frequency * 1000; in acpi_cpufreq_cpu_init()
282 (u32) data->acpi_data.states[i].core_frequency, in acpi_cpufreq_cpu_init()
283 (u32) data->acpi_data.states[i].power, in acpi_cpufreq_cpu_init()
284 (u32) data->acpi_data.states[i].transition_latency, in acpi_cpufreq_cpu_init()
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| D | acpi-cpufreq.c | 208 if (value == perf->states[i].status) in extract_io()
230 if (msr == perf->states[pos->driver_data].status) in extract_msr()
447 drv_write(data, mask, perf->states[next_perf_state].control); in acpi_cpufreq_target()
493 perf->states[next_perf_state].control); in acpi_cpufreq_fast_switch()
508 unsigned long freqn = perf->states[0].core_frequency * 1000; in acpi_cpufreq_guess_freq()
512 freqn = perf->states[i+1].core_frequency * 1000; in acpi_cpufreq_guess_freq()
523 return perf->states[0].core_frequency * 1000; in acpi_cpufreq_guess_freq()
810 if ((perf->states[i].transition_latency * 1000) > in acpi_cpufreq_cpu_init()
813 perf->states[i].transition_latency * 1000; in acpi_cpufreq_cpu_init()
825 if (i > 0 && perf->states[i].core_frequency >= in acpi_cpufreq_cpu_init()
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| /drivers/acpi/ |
| D | processor_idle.c | 168 return cx - pr->power.states >= pr->power.timer_broadcast_on_state; in lapic_timer_needs_broadcast()
218 pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2; in acpi_processor_get_power_info_fadt()
219 pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3; in acpi_processor_get_power_info_fadt()
232 pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4; in acpi_processor_get_power_info_fadt()
233 pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5; in acpi_processor_get_power_info_fadt()
236 pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.c2_latency; in acpi_processor_get_power_info_fadt()
237 pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.c3_latency; in acpi_processor_get_power_info_fadt()
247 pr->power.states[ACPI_STATE_C2].address = 0; in acpi_processor_get_power_info_fadt()
258 pr->power.states[ACPI_STATE_C3].address = 0; in acpi_processor_get_power_info_fadt()
262 pr->power.states[ACPI_STATE_C2].address, in acpi_processor_get_power_info_fadt()
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| D | processor_perflib.c | 98 qos_value = pr->performance->states[index].core_frequency * 1000; in acpi_processor_get_platform_limit()
160 *limit = pr->performance->states[pr->performance_platform_limit]. in acpi_processor_get_bios_limit()
335 pr->performance->states = in acpi_processor_get_performance_states()
339 if (!pr->performance->states) { in acpi_processor_get_performance_states()
346 struct acpi_processor_px *px = &(pr->performance->states[i]); in acpi_processor_get_performance_states()
359 kfree(pr->performance->states); in acpi_processor_get_performance_states()
390 memcpy(&(pr->performance->states[last_invalid]), in acpi_processor_get_performance_states()
401 kfree(pr->performance->states); in acpi_processor_get_performance_states()
402 pr->performance->states = NULL; in acpi_processor_get_performance_states()
792 kfree(pr->performance->states); in acpi_processor_unregister_performance()
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| /drivers/gpu/drm/ |
| D | drm_blend.c | 448 struct drm_plane_state **states; in drm_atomic_helper_crtc_normalize_zpos() local
456 states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL); in drm_atomic_helper_crtc_normalize_zpos()
457 if (!states) in drm_atomic_helper_crtc_normalize_zpos()
471 states[n++] = plane_state; in drm_atomic_helper_crtc_normalize_zpos()
477 sort(states, n, sizeof(*states), drm_atomic_state_zpos_cmp, NULL); in drm_atomic_helper_crtc_normalize_zpos()
480 plane = states[i]->plane; in drm_atomic_helper_crtc_normalize_zpos()
482 states[i]->normalized_zpos = i; in drm_atomic_helper_crtc_normalize_zpos()
489 kfree(states); in drm_atomic_helper_crtc_normalize_zpos()
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| /drivers/i2c/muxes/ |
| D | i2c-mux-pinctrl.c | 19 struct pinctrl_state *states[]; member
26 return pinctrl_select_state(mux->pinctrl, mux->states[chan]); in i2c_mux_pinctrl_select()
96 struct_size(mux, states, num_names), in i2c_mux_pinctrl_probe()
121 mux->states[i] = pinctrl_lookup_state(mux->pinctrl, name); in i2c_mux_pinctrl_probe()
122 if (IS_ERR(mux->states[i])) { in i2c_mux_pinctrl_probe()
123 ret = PTR_ERR(mux->states[i]); in i2c_mux_pinctrl_probe()
144 if (root != i2c_mux_pinctrl_root_adapter(mux->states[i])) { in i2c_mux_pinctrl_probe()
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| /drivers/base/power/ |
| D | domain_governor.c | 168 min_sleep_ns = genpd->states[state].power_off_latency_ns + in next_wakeup_allows_state()
169 genpd->states[state].residency_ns; in next_wakeup_allows_state()
190 off_on_time_ns = genpd->states[state].power_off_latency_ns + in __default_power_down_ok()
191 genpd->states[state].power_on_latency_ns; in __default_power_down_ok()
261 genpd->states[state].power_on_latency_ns; in __default_power_down_ok()
392 if (idle_duration_ns >= (genpd->states[i].residency_ns + in cpu_power_down_ok()
393 genpd->states[i].power_off_latency_ns)) { in cpu_power_down_ok()
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| /drivers/gpu/drm/omapdrm/ |
| D | omap_drv.c | 145 struct drm_plane_state **states; in omap_atomic_update_normalize_zpos() local
148 states = kmalloc_array(total_planes, sizeof(*states), GFP_KERNEL); in omap_atomic_update_normalize_zpos()
149 if (!states) in omap_atomic_update_normalize_zpos()
172 states[n++] = plane_state; in omap_atomic_update_normalize_zpos()
175 sort(states, n, sizeof(*states), in omap_atomic_update_normalize_zpos()
179 plane = states[i]->plane; in omap_atomic_update_normalize_zpos()
181 states[i]->normalized_zpos = i + inc; in omap_atomic_update_normalize_zpos()
184 states[i]->normalized_zpos); in omap_atomic_update_normalize_zpos()
186 if (is_omap_plane_dual_overlay(states[i])) in omap_atomic_update_normalize_zpos()
193 kfree(states); in omap_atomic_update_normalize_zpos()
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| /drivers/xen/ |
| D | xen-acpi-processor.c | 70 cx = &_pr->power.states[i]; in push_cxx_to_hypervisor()
110 set_xen_guest_handle(op.u.set_pminfo.power.states, dst_cx_states); in push_cxx_to_hypervisor()
118 cx = &_pr->power.states[i]; in push_cxx_to_hypervisor()
153 memcpy(&(dst_states[i]), &(_pr->performance->states[i]), in xen_copy_pss_data()
227 set_xen_guest_handle(dst_perf->states, dst_states); in push_pxx_to_hypervisor()
252 (u32) perf->states[i].core_frequency, in push_pxx_to_hypervisor()
253 (u32) perf->states[i].power, in push_pxx_to_hypervisor()
254 (u32) perf->states[i].transition_latency); in push_pxx_to_hypervisor()
280 if (_pr->performance && _pr->performance->states) in upload_pm_data()
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| /drivers/mux/ |
| D | gpio.c | 73 mux_chip->mux->states = BIT(pins); in mux_gpio_probe()
77 if (idle_state < 0 || idle_state >= mux_chip->mux->states) { in mux_gpio_probe()
90 mux_chip->mux->states); in mux_gpio_probe()
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| D | adgs1408.c | 83 mux->states = 8; in adgs1408_probe()
85 mux->states = 4; in adgs1408_probe()
92 if (idle_state < mux->states) { in adgs1408_probe()
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| /drivers/thermal/ |
| D | thermal_sysfs.c | 744 int i, states = stats->max_states; in reset_store() local
751 states * states * sizeof(*stats->trans_table)); in reset_store()
827 unsigned long states; in cooling_device_stats_setup() local
836 if (cdev->ops->get_max_state(cdev, &states)) in cooling_device_stats_setup()
839 states++; /* Total number of states is highest state + 1 */ in cooling_device_stats_setup()
842 var += sizeof(*stats->time_in_state) * states; in cooling_device_stats_setup()
843 var += sizeof(*stats->trans_table) * states * states; in cooling_device_stats_setup()
850 stats->trans_table = (unsigned int *)(stats->time_in_state + states); in cooling_device_stats_setup()
853 stats->max_states = states; in cooling_device_stats_setup()
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| /drivers/tty/serial/ |
| D | st-asc.c | 40 struct pinctrl_state *states[2]; member
563 ascport->states[DEFAULT]); in asc_set_termios()
567 if (!ascport->rts && ascport->states[NO_HW_FLOWCTRL]) { in asc_set_termios()
569 ascport->states[NO_HW_FLOWCTRL]); in asc_set_termios()
757 ascport->states[DEFAULT] = in asc_init_port()
759 if (IS_ERR(ascport->states[DEFAULT])) { in asc_init_port()
760 ret = PTR_ERR(ascport->states[DEFAULT]); in asc_init_port()
767 ascport->states[NO_HW_FLOWCTRL] = in asc_init_port()
769 if (IS_ERR(ascport->states[NO_HW_FLOWCTRL])) in asc_init_port()
770 ascport->states[NO_HW_FLOWCTRL] = NULL; in asc_init_port()
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| /drivers/gpu/drm/amd/pm/ |
| D | amdgpu_pm.c | 388 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" : in amdgpu_get_pp_num_states()
389 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" : in amdgpu_get_pp_num_states()
390 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" : in amdgpu_get_pp_num_states()
391 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default"); in amdgpu_get_pp_num_states()
428 if (pm == data.states[i]) in amdgpu_get_pp_cur_state()
479 if (ret || idx >= ARRAY_SIZE(data.states)) in amdgpu_set_pp_force_state()
482 idx = array_index_nospec(idx, ARRAY_SIZE(data.states)); in amdgpu_set_pp_force_state()
494 state = data.states[idx]; in amdgpu_set_pp_force_state()
1892 uint32_t mask, enum amdgpu_device_attr_states *states) in ss_power_attr_update() argument
1895 *states = ATTR_STATE_UNSUPPORTED; in ss_power_attr_update()
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