1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
24 #include <linux/fs.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
29
30 #include <asm/cpu.h>
31 #include <asm/div64.h>
32 #include <asm/msr.h>
33 #include <asm/cpu_device_id.h>
34 #include <asm/cpufeature.h>
35 #include <asm/intel-family.h>
36 #include "../drivers/thermal/intel/thermal_interrupt.h"
37
38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
39
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
43
44 #ifdef CONFIG_ACPI
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
47 #endif
48
49 #define FRAC_BITS 8
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
52
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
mul_fp(int32_t x,int32_t y)60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
div_fp(s64 x,s64 y)65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
ceiling_fp(int32_t x)70 static inline int ceiling_fp(int32_t x)
71 {
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79 }
80
mul_ext_fp(u64 x,u64 y)81 static inline u64 mul_ext_fp(u64 x, u64 y)
82 {
83 return (x * y) >> EXT_FRAC_BITS;
84 }
85
div_ext_fp(u64 x,u64 y)86 static inline u64 div_ext_fp(u64 x, u64 y)
87 {
88 return div64_u64(x << EXT_FRAC_BITS, y);
89 }
90
91 /**
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
103 * current sample
104 * @time: Current time from scheduler
105 *
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
108 */
109 struct sample {
110 int32_t core_avg_perf;
111 int32_t busy_scaled;
112 u64 aperf;
113 u64 mperf;
114 u64 tsc;
115 u64 time;
116 };
117
118 /**
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
127 * @scaling: Scaling factor between performance and frequency
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @min_freq: @min_pstate frequency in cpufreq units
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
132 *
133 * Stores the per cpu model P state limits and current P state.
134 */
135 struct pstate_data {
136 int current_pstate;
137 int min_pstate;
138 int max_pstate;
139 int max_pstate_physical;
140 int perf_ctl_scaling;
141 int scaling;
142 int turbo_pstate;
143 unsigned int min_freq;
144 unsigned int max_freq;
145 unsigned int turbo_freq;
146 };
147
148 /**
149 * struct vid_data - Stores voltage information data
150 * @min: VID data for this platform corresponding to
151 * the lowest P state
152 * @max: VID data corresponding to the highest P State.
153 * @turbo: VID data for turbo P state
154 * @ratio: Ratio of (vid max - vid min) /
155 * (max P state - Min P State)
156 *
157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158 * This data is used in Atom platforms, where in addition to target P state,
159 * the voltage data needs to be specified to select next P State.
160 */
161 struct vid_data {
162 int min;
163 int max;
164 int turbo;
165 int32_t ratio;
166 };
167
168 /**
169 * struct global_params - Global parameters, mostly tunable via sysfs.
170 * @no_turbo: Whether or not to use turbo P-states.
171 * @turbo_disabled: Whether or not turbo P-states are available at all,
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
173 * not the maximum reported turbo P-state is different from
174 * the maximum reported non-turbo one.
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
177 * P-state capacity.
178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
179 * P-state capacity.
180 */
181 struct global_params {
182 bool no_turbo;
183 bool turbo_disabled;
184 bool turbo_disabled_mf;
185 int max_perf_pct;
186 int min_perf_pct;
187 };
188
189 /**
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @prev_cummulative_iowait: IO Wait time difference from last and
205 * current sample
206 * @sample: Storage for storing last Sample data
207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
209 * @acpi_perf_data: Stores ACPI perf information read from _PSS
210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
211 * @epp_powersave: Last saved HWP energy performance preference
212 * (EPP) or energy performance bias (EPB),
213 * when policy switched to performance
214 * @epp_policy: Last saved policy used to set EPP/EPB
215 * @epp_default: Power on default HWP energy performance
216 * preference/bias
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
220 * @last_io_update: Last time when IO wake flag was set
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @hwp_notify_work: workqueue for HWP notifications.
225 *
226 * This structure stores per CPU instance data for all CPUs.
227 */
228 struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251 #endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_cached;
257 u64 hwp_req_cached;
258 u64 hwp_cap_cached;
259 u64 last_io_update;
260 unsigned int sched_flags;
261 u32 hwp_boost_min;
262 bool suspended;
263 struct delayed_work hwp_notify_work;
264 };
265
266 static struct cpudata **all_cpu_data;
267
268 /**
269 * struct pstate_funcs - Per CPU model specific callbacks
270 * @get_max: Callback to get maximum non turbo effective P state
271 * @get_max_physical: Callback to get maximum non turbo physical P state
272 * @get_min: Callback to get minimum P state
273 * @get_turbo: Callback to get turbo P state
274 * @get_scaling: Callback to get frequency scaling factor
275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
283 struct pstate_funcs {
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
288 int (*get_scaling)(void);
289 int (*get_cpu_scaling)(int cpu);
290 int (*get_aperf_mperf_shift)(void);
291 u64 (*get_val)(struct cpudata*, int pstate);
292 void (*get_vid)(struct cpudata *);
293 };
294
295 static struct pstate_funcs pstate_funcs __read_mostly;
296
297 static int hwp_active __read_mostly;
298 static int hwp_mode_bdw __read_mostly;
299 static bool per_cpu_limits __read_mostly;
300 static bool hwp_boost __read_mostly;
301
302 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
303
304 #ifdef CONFIG_ACPI
305 static bool acpi_ppc;
306 #endif
307
308 static struct global_params global;
309
310 static DEFINE_MUTEX(intel_pstate_driver_lock);
311 static DEFINE_MUTEX(intel_pstate_limits_lock);
312
313 #ifdef CONFIG_ACPI
314
intel_pstate_acpi_pm_profile_server(void)315 static bool intel_pstate_acpi_pm_profile_server(void)
316 {
317 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
318 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
319 return true;
320
321 return false;
322 }
323
intel_pstate_get_ppc_enable_status(void)324 static bool intel_pstate_get_ppc_enable_status(void)
325 {
326 if (intel_pstate_acpi_pm_profile_server())
327 return true;
328
329 return acpi_ppc;
330 }
331
332 #ifdef CONFIG_ACPI_CPPC_LIB
333
334 /* The work item is needed to avoid CPU hotplug locking issues */
intel_pstste_sched_itmt_work_fn(struct work_struct * work)335 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
336 {
337 sched_set_itmt_support();
338 }
339
340 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
341
342 #define CPPC_MAX_PERF U8_MAX
343
intel_pstate_set_itmt_prio(int cpu)344 static void intel_pstate_set_itmt_prio(int cpu)
345 {
346 struct cppc_perf_caps cppc_perf;
347 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
348 int ret;
349
350 ret = cppc_get_perf_caps(cpu, &cppc_perf);
351 if (ret)
352 return;
353
354 /*
355 * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
356 * In this case we can't use CPPC.highest_perf to enable ITMT.
357 * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
358 */
359 if (cppc_perf.highest_perf == CPPC_MAX_PERF)
360 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
361
362 /*
363 * The priorities can be set regardless of whether or not
364 * sched_set_itmt_support(true) has been called and it is valid to
365 * update them at any time after it has been called.
366 */
367 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
368
369 if (max_highest_perf <= min_highest_perf) {
370 if (cppc_perf.highest_perf > max_highest_perf)
371 max_highest_perf = cppc_perf.highest_perf;
372
373 if (cppc_perf.highest_perf < min_highest_perf)
374 min_highest_perf = cppc_perf.highest_perf;
375
376 if (max_highest_perf > min_highest_perf) {
377 /*
378 * This code can be run during CPU online under the
379 * CPU hotplug locks, so sched_set_itmt_support()
380 * cannot be called from here. Queue up a work item
381 * to invoke it.
382 */
383 schedule_work(&sched_itmt_work);
384 }
385 }
386 }
387
intel_pstate_get_cppc_guaranteed(int cpu)388 static int intel_pstate_get_cppc_guaranteed(int cpu)
389 {
390 struct cppc_perf_caps cppc_perf;
391 int ret;
392
393 ret = cppc_get_perf_caps(cpu, &cppc_perf);
394 if (ret)
395 return ret;
396
397 if (cppc_perf.guaranteed_perf)
398 return cppc_perf.guaranteed_perf;
399
400 return cppc_perf.nominal_perf;
401 }
402 #else /* CONFIG_ACPI_CPPC_LIB */
intel_pstate_set_itmt_prio(int cpu)403 static inline void intel_pstate_set_itmt_prio(int cpu)
404 {
405 }
406 #endif /* CONFIG_ACPI_CPPC_LIB */
407
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)408 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
409 {
410 struct cpudata *cpu;
411 int ret;
412 int i;
413
414 if (hwp_active) {
415 intel_pstate_set_itmt_prio(policy->cpu);
416 return;
417 }
418
419 if (!intel_pstate_get_ppc_enable_status())
420 return;
421
422 cpu = all_cpu_data[policy->cpu];
423
424 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
425 policy->cpu);
426 if (ret)
427 return;
428
429 /*
430 * Check if the control value in _PSS is for PERF_CTL MSR, which should
431 * guarantee that the states returned by it map to the states in our
432 * list directly.
433 */
434 if (cpu->acpi_perf_data.control_register.space_id !=
435 ACPI_ADR_SPACE_FIXED_HARDWARE)
436 goto err;
437
438 /*
439 * If there is only one entry _PSS, simply ignore _PSS and continue as
440 * usual without taking _PSS into account
441 */
442 if (cpu->acpi_perf_data.state_count < 2)
443 goto err;
444
445 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
446 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
447 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
448 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
449 (u32) cpu->acpi_perf_data.states[i].core_frequency,
450 (u32) cpu->acpi_perf_data.states[i].power,
451 (u32) cpu->acpi_perf_data.states[i].control);
452 }
453
454 cpu->valid_pss_table = true;
455 pr_debug("_PPC limits will be enforced\n");
456
457 return;
458
459 err:
460 cpu->valid_pss_table = false;
461 acpi_processor_unregister_performance(policy->cpu);
462 }
463
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)464 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
465 {
466 struct cpudata *cpu;
467
468 cpu = all_cpu_data[policy->cpu];
469 if (!cpu->valid_pss_table)
470 return;
471
472 acpi_processor_unregister_performance(policy->cpu);
473 }
474 #else /* CONFIG_ACPI */
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)475 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
476 {
477 }
478
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)479 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
480 {
481 }
482
intel_pstate_acpi_pm_profile_server(void)483 static inline bool intel_pstate_acpi_pm_profile_server(void)
484 {
485 return false;
486 }
487 #endif /* CONFIG_ACPI */
488
489 #ifndef CONFIG_ACPI_CPPC_LIB
intel_pstate_get_cppc_guaranteed(int cpu)490 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
491 {
492 return -ENOTSUPP;
493 }
494 #endif /* CONFIG_ACPI_CPPC_LIB */
495
intel_pstate_freq_to_hwp_rel(struct cpudata * cpu,int freq,unsigned int relation)496 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
497 unsigned int relation)
498 {
499 if (freq == cpu->pstate.turbo_freq)
500 return cpu->pstate.turbo_pstate;
501
502 if (freq == cpu->pstate.max_freq)
503 return cpu->pstate.max_pstate;
504
505 switch (relation) {
506 case CPUFREQ_RELATION_H:
507 return freq / cpu->pstate.scaling;
508 case CPUFREQ_RELATION_C:
509 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
510 }
511
512 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
513 }
514
intel_pstate_freq_to_hwp(struct cpudata * cpu,int freq)515 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
516 {
517 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
518 }
519
520 /**
521 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
522 * @cpu: Target CPU.
523 *
524 * On hybrid processors, HWP may expose more performance levels than there are
525 * P-states accessible through the PERF_CTL interface. If that happens, the
526 * scaling factor between HWP performance levels and CPU frequency will be less
527 * than the scaling factor between P-state values and CPU frequency.
528 *
529 * In that case, adjust the CPU parameters used in computations accordingly.
530 */
intel_pstate_hybrid_hwp_adjust(struct cpudata * cpu)531 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
532 {
533 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
534 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
535 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
536 int scaling = cpu->pstate.scaling;
537 int freq;
538
539 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
540 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
541 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
542 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
543 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
544 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
545
546 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
547 perf_ctl_scaling);
548 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
549 perf_ctl_scaling);
550
551 freq = perf_ctl_max_phys * perf_ctl_scaling;
552 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
553
554 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
555 cpu->pstate.min_freq = freq;
556 /*
557 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
558 * the effective range of HWP performance levels.
559 */
560 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
561 }
562
update_turbo_state(void)563 static inline void update_turbo_state(void)
564 {
565 u64 misc_en;
566 struct cpudata *cpu;
567
568 cpu = all_cpu_data[0];
569 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
570 global.turbo_disabled =
571 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
572 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
573 }
574
min_perf_pct_min(void)575 static int min_perf_pct_min(void)
576 {
577 struct cpudata *cpu = all_cpu_data[0];
578 int turbo_pstate = cpu->pstate.turbo_pstate;
579
580 return turbo_pstate ?
581 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
582 }
583
intel_pstate_get_epb(struct cpudata * cpu_data)584 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
585 {
586 u64 epb;
587 int ret;
588
589 if (!boot_cpu_has(X86_FEATURE_EPB))
590 return -ENXIO;
591
592 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
593 if (ret)
594 return (s16)ret;
595
596 return (s16)(epb & 0x0f);
597 }
598
intel_pstate_get_epp(struct cpudata * cpu_data,u64 hwp_req_data)599 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
600 {
601 s16 epp;
602
603 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
604 /*
605 * When hwp_req_data is 0, means that caller didn't read
606 * MSR_HWP_REQUEST, so need to read and get EPP.
607 */
608 if (!hwp_req_data) {
609 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
610 &hwp_req_data);
611 if (epp)
612 return epp;
613 }
614 epp = (hwp_req_data >> 24) & 0xff;
615 } else {
616 /* When there is no EPP present, HWP uses EPB settings */
617 epp = intel_pstate_get_epb(cpu_data);
618 }
619
620 return epp;
621 }
622
intel_pstate_set_epb(int cpu,s16 pref)623 static int intel_pstate_set_epb(int cpu, s16 pref)
624 {
625 u64 epb;
626 int ret;
627
628 if (!boot_cpu_has(X86_FEATURE_EPB))
629 return -ENXIO;
630
631 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
632 if (ret)
633 return ret;
634
635 epb = (epb & ~0x0f) | pref;
636 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
637
638 return 0;
639 }
640
641 /*
642 * EPP/EPB display strings corresponding to EPP index in the
643 * energy_perf_strings[]
644 * index String
645 *-------------------------------------
646 * 0 default
647 * 1 performance
648 * 2 balance_performance
649 * 3 balance_power
650 * 4 power
651 */
652
653 enum energy_perf_value_index {
654 EPP_INDEX_DEFAULT = 0,
655 EPP_INDEX_PERFORMANCE,
656 EPP_INDEX_BALANCE_PERFORMANCE,
657 EPP_INDEX_BALANCE_POWERSAVE,
658 EPP_INDEX_POWERSAVE,
659 };
660
661 static const char * const energy_perf_strings[] = {
662 [EPP_INDEX_DEFAULT] = "default",
663 [EPP_INDEX_PERFORMANCE] = "performance",
664 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
665 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
666 [EPP_INDEX_POWERSAVE] = "power",
667 NULL
668 };
669 static unsigned int epp_values[] = {
670 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
671 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
672 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
673 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
674 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
675 };
676
intel_pstate_get_energy_pref_index(struct cpudata * cpu_data,int * raw_epp)677 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
678 {
679 s16 epp;
680 int index = -EINVAL;
681
682 *raw_epp = 0;
683 epp = intel_pstate_get_epp(cpu_data, 0);
684 if (epp < 0)
685 return epp;
686
687 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
688 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
689 return EPP_INDEX_PERFORMANCE;
690 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
691 return EPP_INDEX_BALANCE_PERFORMANCE;
692 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
693 return EPP_INDEX_BALANCE_POWERSAVE;
694 if (epp == epp_values[EPP_INDEX_POWERSAVE])
695 return EPP_INDEX_POWERSAVE;
696 *raw_epp = epp;
697 return 0;
698 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
699 /*
700 * Range:
701 * 0x00-0x03 : Performance
702 * 0x04-0x07 : Balance performance
703 * 0x08-0x0B : Balance power
704 * 0x0C-0x0F : Power
705 * The EPB is a 4 bit value, but our ranges restrict the
706 * value which can be set. Here only using top two bits
707 * effectively.
708 */
709 index = (epp >> 2) + 1;
710 }
711
712 return index;
713 }
714
intel_pstate_set_epp(struct cpudata * cpu,u32 epp)715 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
716 {
717 int ret;
718
719 /*
720 * Use the cached HWP Request MSR value, because in the active mode the
721 * register itself may be updated by intel_pstate_hwp_boost_up() or
722 * intel_pstate_hwp_boost_down() at any time.
723 */
724 u64 value = READ_ONCE(cpu->hwp_req_cached);
725
726 value &= ~GENMASK_ULL(31, 24);
727 value |= (u64)epp << 24;
728 /*
729 * The only other updater of hwp_req_cached in the active mode,
730 * intel_pstate_hwp_set(), is called under the same lock as this
731 * function, so it cannot run in parallel with the update below.
732 */
733 WRITE_ONCE(cpu->hwp_req_cached, value);
734 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
735 if (!ret)
736 cpu->epp_cached = epp;
737
738 return ret;
739 }
740
intel_pstate_set_energy_pref_index(struct cpudata * cpu_data,int pref_index,bool use_raw,u32 raw_epp)741 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
742 int pref_index, bool use_raw,
743 u32 raw_epp)
744 {
745 int epp = -EINVAL;
746 int ret;
747
748 if (!pref_index)
749 epp = cpu_data->epp_default;
750
751 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
752 if (use_raw)
753 epp = raw_epp;
754 else if (epp == -EINVAL)
755 epp = epp_values[pref_index];
756
757 /*
758 * To avoid confusion, refuse to set EPP to any values different
759 * from 0 (performance) if the current policy is "performance",
760 * because those values would be overridden.
761 */
762 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
763 return -EBUSY;
764
765 ret = intel_pstate_set_epp(cpu_data, epp);
766 } else {
767 if (epp == -EINVAL)
768 epp = (pref_index - 1) << 2;
769 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
770 }
771
772 return ret;
773 }
774
show_energy_performance_available_preferences(struct cpufreq_policy * policy,char * buf)775 static ssize_t show_energy_performance_available_preferences(
776 struct cpufreq_policy *policy, char *buf)
777 {
778 int i = 0;
779 int ret = 0;
780
781 while (energy_perf_strings[i] != NULL)
782 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
783
784 ret += sprintf(&buf[ret], "\n");
785
786 return ret;
787 }
788
789 cpufreq_freq_attr_ro(energy_performance_available_preferences);
790
791 static struct cpufreq_driver intel_pstate;
792
store_energy_performance_preference(struct cpufreq_policy * policy,const char * buf,size_t count)793 static ssize_t store_energy_performance_preference(
794 struct cpufreq_policy *policy, const char *buf, size_t count)
795 {
796 struct cpudata *cpu = all_cpu_data[policy->cpu];
797 char str_preference[21];
798 bool raw = false;
799 ssize_t ret;
800 u32 epp = 0;
801
802 ret = sscanf(buf, "%20s", str_preference);
803 if (ret != 1)
804 return -EINVAL;
805
806 ret = match_string(energy_perf_strings, -1, str_preference);
807 if (ret < 0) {
808 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
809 return ret;
810
811 ret = kstrtouint(buf, 10, &epp);
812 if (ret)
813 return ret;
814
815 if (epp > 255)
816 return -EINVAL;
817
818 raw = true;
819 }
820
821 /*
822 * This function runs with the policy R/W semaphore held, which
823 * guarantees that the driver pointer will not change while it is
824 * running.
825 */
826 if (!intel_pstate_driver)
827 return -EAGAIN;
828
829 mutex_lock(&intel_pstate_limits_lock);
830
831 if (intel_pstate_driver == &intel_pstate) {
832 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
833 } else {
834 /*
835 * In the passive mode the governor needs to be stopped on the
836 * target CPU before the EPP update and restarted after it,
837 * which is super-heavy-weight, so make sure it is worth doing
838 * upfront.
839 */
840 if (!raw)
841 epp = ret ? epp_values[ret] : cpu->epp_default;
842
843 if (cpu->epp_cached != epp) {
844 int err;
845
846 cpufreq_stop_governor(policy);
847 ret = intel_pstate_set_epp(cpu, epp);
848 err = cpufreq_start_governor(policy);
849 if (!ret)
850 ret = err;
851 } else {
852 ret = 0;
853 }
854 }
855
856 mutex_unlock(&intel_pstate_limits_lock);
857
858 return ret ?: count;
859 }
860
show_energy_performance_preference(struct cpufreq_policy * policy,char * buf)861 static ssize_t show_energy_performance_preference(
862 struct cpufreq_policy *policy, char *buf)
863 {
864 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
865 int preference, raw_epp;
866
867 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
868 if (preference < 0)
869 return preference;
870
871 if (raw_epp)
872 return sprintf(buf, "%d\n", raw_epp);
873 else
874 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
875 }
876
877 cpufreq_freq_attr_rw(energy_performance_preference);
878
show_base_frequency(struct cpufreq_policy * policy,char * buf)879 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
880 {
881 struct cpudata *cpu = all_cpu_data[policy->cpu];
882 int ratio, freq;
883
884 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
885 if (ratio <= 0) {
886 u64 cap;
887
888 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
889 ratio = HWP_GUARANTEED_PERF(cap);
890 }
891
892 freq = ratio * cpu->pstate.scaling;
893 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
894 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
895
896 return sprintf(buf, "%d\n", freq);
897 }
898
899 cpufreq_freq_attr_ro(base_frequency);
900
901 static struct freq_attr *hwp_cpufreq_attrs[] = {
902 &energy_performance_preference,
903 &energy_performance_available_preferences,
904 &base_frequency,
905 NULL,
906 };
907
__intel_pstate_get_hwp_cap(struct cpudata * cpu)908 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
909 {
910 u64 cap;
911
912 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
913 WRITE_ONCE(cpu->hwp_cap_cached, cap);
914 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
915 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
916 }
917
intel_pstate_get_hwp_cap(struct cpudata * cpu)918 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
919 {
920 int scaling = cpu->pstate.scaling;
921
922 __intel_pstate_get_hwp_cap(cpu);
923
924 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
925 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
926 if (scaling != cpu->pstate.perf_ctl_scaling) {
927 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
928
929 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
930 perf_ctl_scaling);
931 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
932 perf_ctl_scaling);
933 }
934 }
935
intel_pstate_hwp_set(unsigned int cpu)936 static void intel_pstate_hwp_set(unsigned int cpu)
937 {
938 struct cpudata *cpu_data = all_cpu_data[cpu];
939 int max, min;
940 u64 value;
941 s16 epp;
942
943 max = cpu_data->max_perf_ratio;
944 min = cpu_data->min_perf_ratio;
945
946 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
947 min = max;
948
949 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
950
951 value &= ~HWP_MIN_PERF(~0L);
952 value |= HWP_MIN_PERF(min);
953
954 value &= ~HWP_MAX_PERF(~0L);
955 value |= HWP_MAX_PERF(max);
956
957 if (cpu_data->epp_policy == cpu_data->policy)
958 goto skip_epp;
959
960 cpu_data->epp_policy = cpu_data->policy;
961
962 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
963 epp = intel_pstate_get_epp(cpu_data, value);
964 cpu_data->epp_powersave = epp;
965 /* If EPP read was failed, then don't try to write */
966 if (epp < 0)
967 goto skip_epp;
968
969 epp = 0;
970 } else {
971 /* skip setting EPP, when saved value is invalid */
972 if (cpu_data->epp_powersave < 0)
973 goto skip_epp;
974
975 /*
976 * No need to restore EPP when it is not zero. This
977 * means:
978 * - Policy is not changed
979 * - user has manually changed
980 * - Error reading EPB
981 */
982 epp = intel_pstate_get_epp(cpu_data, value);
983 if (epp)
984 goto skip_epp;
985
986 epp = cpu_data->epp_powersave;
987 }
988 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
989 value &= ~GENMASK_ULL(31, 24);
990 value |= (u64)epp << 24;
991 } else {
992 intel_pstate_set_epb(cpu, epp);
993 }
994 skip_epp:
995 WRITE_ONCE(cpu_data->hwp_req_cached, value);
996 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
997 }
998
999 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1000
intel_pstate_hwp_offline(struct cpudata * cpu)1001 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1002 {
1003 u64 value = READ_ONCE(cpu->hwp_req_cached);
1004 int min_perf;
1005
1006 intel_pstate_disable_hwp_interrupt(cpu);
1007
1008 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1009 /*
1010 * In case the EPP has been set to "performance" by the
1011 * active mode "performance" scaling algorithm, replace that
1012 * temporary value with the cached EPP one.
1013 */
1014 value &= ~GENMASK_ULL(31, 24);
1015 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1016 /*
1017 * However, make sure that EPP will be set to "performance" when
1018 * the CPU is brought back online again and the "performance"
1019 * scaling algorithm is still in effect.
1020 */
1021 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1022 }
1023
1024 /*
1025 * Clear the desired perf field in the cached HWP request value to
1026 * prevent nonzero desired values from being leaked into the active
1027 * mode.
1028 */
1029 value &= ~HWP_DESIRED_PERF(~0L);
1030 WRITE_ONCE(cpu->hwp_req_cached, value);
1031
1032 value &= ~GENMASK_ULL(31, 0);
1033 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1034
1035 /* Set hwp_max = hwp_min */
1036 value |= HWP_MAX_PERF(min_perf);
1037 value |= HWP_MIN_PERF(min_perf);
1038
1039 /* Set EPP to min */
1040 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1041 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1042
1043 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1044 }
1045
1046 #define POWER_CTL_EE_ENABLE 1
1047 #define POWER_CTL_EE_DISABLE 2
1048
1049 static int power_ctl_ee_state;
1050
set_power_ctl_ee_state(bool input)1051 static void set_power_ctl_ee_state(bool input)
1052 {
1053 u64 power_ctl;
1054
1055 mutex_lock(&intel_pstate_driver_lock);
1056 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1057 if (input) {
1058 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1059 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1060 } else {
1061 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1062 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1063 }
1064 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1065 mutex_unlock(&intel_pstate_driver_lock);
1066 }
1067
1068 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1069
intel_pstate_hwp_reenable(struct cpudata * cpu)1070 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1071 {
1072 intel_pstate_hwp_enable(cpu);
1073 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1074 }
1075
intel_pstate_suspend(struct cpufreq_policy * policy)1076 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1077 {
1078 struct cpudata *cpu = all_cpu_data[policy->cpu];
1079
1080 pr_debug("CPU %d suspending\n", cpu->cpu);
1081
1082 cpu->suspended = true;
1083
1084 /* disable HWP interrupt and cancel any pending work */
1085 intel_pstate_disable_hwp_interrupt(cpu);
1086
1087 return 0;
1088 }
1089
intel_pstate_resume(struct cpufreq_policy * policy)1090 static int intel_pstate_resume(struct cpufreq_policy *policy)
1091 {
1092 struct cpudata *cpu = all_cpu_data[policy->cpu];
1093
1094 pr_debug("CPU %d resuming\n", cpu->cpu);
1095
1096 /* Only restore if the system default is changed */
1097 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1098 set_power_ctl_ee_state(true);
1099 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1100 set_power_ctl_ee_state(false);
1101
1102 if (cpu->suspended && hwp_active) {
1103 mutex_lock(&intel_pstate_limits_lock);
1104
1105 /* Re-enable HWP, because "online" has not done that. */
1106 intel_pstate_hwp_reenable(cpu);
1107
1108 mutex_unlock(&intel_pstate_limits_lock);
1109 }
1110
1111 cpu->suspended = false;
1112
1113 return 0;
1114 }
1115
intel_pstate_update_policies(void)1116 static void intel_pstate_update_policies(void)
1117 {
1118 int cpu;
1119
1120 for_each_possible_cpu(cpu)
1121 cpufreq_update_policy(cpu);
1122 }
1123
__intel_pstate_update_max_freq(struct cpudata * cpudata,struct cpufreq_policy * policy)1124 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1125 struct cpufreq_policy *policy)
1126 {
1127 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1128 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1129 refresh_frequency_limits(policy);
1130 }
1131
intel_pstate_update_max_freq(unsigned int cpu)1132 static void intel_pstate_update_max_freq(unsigned int cpu)
1133 {
1134 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1135
1136 if (!policy)
1137 return;
1138
1139 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1140
1141 cpufreq_cpu_release(policy);
1142 }
1143
intel_pstate_update_limits(unsigned int cpu)1144 static void intel_pstate_update_limits(unsigned int cpu)
1145 {
1146 mutex_lock(&intel_pstate_driver_lock);
1147
1148 update_turbo_state();
1149 /*
1150 * If turbo has been turned on or off globally, policy limits for
1151 * all CPUs need to be updated to reflect that.
1152 */
1153 if (global.turbo_disabled_mf != global.turbo_disabled) {
1154 global.turbo_disabled_mf = global.turbo_disabled;
1155 arch_set_max_freq_ratio(global.turbo_disabled);
1156 for_each_possible_cpu(cpu)
1157 intel_pstate_update_max_freq(cpu);
1158 } else {
1159 cpufreq_update_policy(cpu);
1160 }
1161
1162 mutex_unlock(&intel_pstate_driver_lock);
1163 }
1164
1165 /************************** sysfs begin ************************/
1166 #define show_one(file_name, object) \
1167 static ssize_t show_##file_name \
1168 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1169 { \
1170 return sprintf(buf, "%u\n", global.object); \
1171 }
1172
1173 static ssize_t intel_pstate_show_status(char *buf);
1174 static int intel_pstate_update_status(const char *buf, size_t size);
1175
show_status(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1176 static ssize_t show_status(struct kobject *kobj,
1177 struct kobj_attribute *attr, char *buf)
1178 {
1179 ssize_t ret;
1180
1181 mutex_lock(&intel_pstate_driver_lock);
1182 ret = intel_pstate_show_status(buf);
1183 mutex_unlock(&intel_pstate_driver_lock);
1184
1185 return ret;
1186 }
1187
store_status(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1188 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1189 const char *buf, size_t count)
1190 {
1191 char *p = memchr(buf, '\n', count);
1192 int ret;
1193
1194 mutex_lock(&intel_pstate_driver_lock);
1195 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1196 mutex_unlock(&intel_pstate_driver_lock);
1197
1198 return ret < 0 ? ret : count;
1199 }
1200
show_turbo_pct(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1201 static ssize_t show_turbo_pct(struct kobject *kobj,
1202 struct kobj_attribute *attr, char *buf)
1203 {
1204 struct cpudata *cpu;
1205 int total, no_turbo, turbo_pct;
1206 uint32_t turbo_fp;
1207
1208 mutex_lock(&intel_pstate_driver_lock);
1209
1210 if (!intel_pstate_driver) {
1211 mutex_unlock(&intel_pstate_driver_lock);
1212 return -EAGAIN;
1213 }
1214
1215 cpu = all_cpu_data[0];
1216
1217 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1218 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1219 turbo_fp = div_fp(no_turbo, total);
1220 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1221
1222 mutex_unlock(&intel_pstate_driver_lock);
1223
1224 return sprintf(buf, "%u\n", turbo_pct);
1225 }
1226
show_num_pstates(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1227 static ssize_t show_num_pstates(struct kobject *kobj,
1228 struct kobj_attribute *attr, char *buf)
1229 {
1230 struct cpudata *cpu;
1231 int total;
1232
1233 mutex_lock(&intel_pstate_driver_lock);
1234
1235 if (!intel_pstate_driver) {
1236 mutex_unlock(&intel_pstate_driver_lock);
1237 return -EAGAIN;
1238 }
1239
1240 cpu = all_cpu_data[0];
1241 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1242
1243 mutex_unlock(&intel_pstate_driver_lock);
1244
1245 return sprintf(buf, "%u\n", total);
1246 }
1247
show_no_turbo(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1248 static ssize_t show_no_turbo(struct kobject *kobj,
1249 struct kobj_attribute *attr, char *buf)
1250 {
1251 ssize_t ret;
1252
1253 mutex_lock(&intel_pstate_driver_lock);
1254
1255 if (!intel_pstate_driver) {
1256 mutex_unlock(&intel_pstate_driver_lock);
1257 return -EAGAIN;
1258 }
1259
1260 update_turbo_state();
1261 if (global.turbo_disabled)
1262 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1263 else
1264 ret = sprintf(buf, "%u\n", global.no_turbo);
1265
1266 mutex_unlock(&intel_pstate_driver_lock);
1267
1268 return ret;
1269 }
1270
store_no_turbo(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1271 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1272 const char *buf, size_t count)
1273 {
1274 unsigned int input;
1275 int ret;
1276
1277 ret = sscanf(buf, "%u", &input);
1278 if (ret != 1)
1279 return -EINVAL;
1280
1281 mutex_lock(&intel_pstate_driver_lock);
1282
1283 if (!intel_pstate_driver) {
1284 mutex_unlock(&intel_pstate_driver_lock);
1285 return -EAGAIN;
1286 }
1287
1288 mutex_lock(&intel_pstate_limits_lock);
1289
1290 update_turbo_state();
1291 if (global.turbo_disabled) {
1292 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1293 mutex_unlock(&intel_pstate_limits_lock);
1294 mutex_unlock(&intel_pstate_driver_lock);
1295 return -EPERM;
1296 }
1297
1298 global.no_turbo = clamp_t(int, input, 0, 1);
1299
1300 if (global.no_turbo) {
1301 struct cpudata *cpu = all_cpu_data[0];
1302 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1303
1304 /* Squash the global minimum into the permitted range. */
1305 if (global.min_perf_pct > pct)
1306 global.min_perf_pct = pct;
1307 }
1308
1309 mutex_unlock(&intel_pstate_limits_lock);
1310
1311 intel_pstate_update_policies();
1312 arch_set_max_freq_ratio(global.no_turbo);
1313
1314 mutex_unlock(&intel_pstate_driver_lock);
1315
1316 return count;
1317 }
1318
update_qos_request(enum freq_qos_req_type type)1319 static void update_qos_request(enum freq_qos_req_type type)
1320 {
1321 struct freq_qos_request *req;
1322 struct cpufreq_policy *policy;
1323 int i;
1324
1325 for_each_possible_cpu(i) {
1326 struct cpudata *cpu = all_cpu_data[i];
1327 unsigned int freq, perf_pct;
1328
1329 policy = cpufreq_cpu_get(i);
1330 if (!policy)
1331 continue;
1332
1333 req = policy->driver_data;
1334 cpufreq_cpu_put(policy);
1335
1336 if (!req)
1337 continue;
1338
1339 if (hwp_active)
1340 intel_pstate_get_hwp_cap(cpu);
1341
1342 if (type == FREQ_QOS_MIN) {
1343 perf_pct = global.min_perf_pct;
1344 } else {
1345 req++;
1346 perf_pct = global.max_perf_pct;
1347 }
1348
1349 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1350
1351 if (freq_qos_update_request(req, freq) < 0)
1352 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1353 }
1354 }
1355
store_max_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1356 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1357 const char *buf, size_t count)
1358 {
1359 unsigned int input;
1360 int ret;
1361
1362 ret = sscanf(buf, "%u", &input);
1363 if (ret != 1)
1364 return -EINVAL;
1365
1366 mutex_lock(&intel_pstate_driver_lock);
1367
1368 if (!intel_pstate_driver) {
1369 mutex_unlock(&intel_pstate_driver_lock);
1370 return -EAGAIN;
1371 }
1372
1373 mutex_lock(&intel_pstate_limits_lock);
1374
1375 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1376
1377 mutex_unlock(&intel_pstate_limits_lock);
1378
1379 if (intel_pstate_driver == &intel_pstate)
1380 intel_pstate_update_policies();
1381 else
1382 update_qos_request(FREQ_QOS_MAX);
1383
1384 mutex_unlock(&intel_pstate_driver_lock);
1385
1386 return count;
1387 }
1388
store_min_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1389 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1390 const char *buf, size_t count)
1391 {
1392 unsigned int input;
1393 int ret;
1394
1395 ret = sscanf(buf, "%u", &input);
1396 if (ret != 1)
1397 return -EINVAL;
1398
1399 mutex_lock(&intel_pstate_driver_lock);
1400
1401 if (!intel_pstate_driver) {
1402 mutex_unlock(&intel_pstate_driver_lock);
1403 return -EAGAIN;
1404 }
1405
1406 mutex_lock(&intel_pstate_limits_lock);
1407
1408 global.min_perf_pct = clamp_t(int, input,
1409 min_perf_pct_min(), global.max_perf_pct);
1410
1411 mutex_unlock(&intel_pstate_limits_lock);
1412
1413 if (intel_pstate_driver == &intel_pstate)
1414 intel_pstate_update_policies();
1415 else
1416 update_qos_request(FREQ_QOS_MIN);
1417
1418 mutex_unlock(&intel_pstate_driver_lock);
1419
1420 return count;
1421 }
1422
show_hwp_dynamic_boost(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1423 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1424 struct kobj_attribute *attr, char *buf)
1425 {
1426 return sprintf(buf, "%u\n", hwp_boost);
1427 }
1428
store_hwp_dynamic_boost(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1429 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1430 struct kobj_attribute *b,
1431 const char *buf, size_t count)
1432 {
1433 unsigned int input;
1434 int ret;
1435
1436 ret = kstrtouint(buf, 10, &input);
1437 if (ret)
1438 return ret;
1439
1440 mutex_lock(&intel_pstate_driver_lock);
1441 hwp_boost = !!input;
1442 intel_pstate_update_policies();
1443 mutex_unlock(&intel_pstate_driver_lock);
1444
1445 return count;
1446 }
1447
show_energy_efficiency(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1448 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1449 char *buf)
1450 {
1451 u64 power_ctl;
1452 int enable;
1453
1454 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1455 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1456 return sprintf(buf, "%d\n", !enable);
1457 }
1458
store_energy_efficiency(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1459 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1460 const char *buf, size_t count)
1461 {
1462 bool input;
1463 int ret;
1464
1465 ret = kstrtobool(buf, &input);
1466 if (ret)
1467 return ret;
1468
1469 set_power_ctl_ee_state(input);
1470
1471 return count;
1472 }
1473
1474 show_one(max_perf_pct, max_perf_pct);
1475 show_one(min_perf_pct, min_perf_pct);
1476
1477 define_one_global_rw(status);
1478 define_one_global_rw(no_turbo);
1479 define_one_global_rw(max_perf_pct);
1480 define_one_global_rw(min_perf_pct);
1481 define_one_global_ro(turbo_pct);
1482 define_one_global_ro(num_pstates);
1483 define_one_global_rw(hwp_dynamic_boost);
1484 define_one_global_rw(energy_efficiency);
1485
1486 static struct attribute *intel_pstate_attributes[] = {
1487 &status.attr,
1488 &no_turbo.attr,
1489 NULL
1490 };
1491
1492 static const struct attribute_group intel_pstate_attr_group = {
1493 .attrs = intel_pstate_attributes,
1494 };
1495
1496 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1497
1498 static struct kobject *intel_pstate_kobject;
1499
intel_pstate_sysfs_expose_params(void)1500 static void __init intel_pstate_sysfs_expose_params(void)
1501 {
1502 int rc;
1503
1504 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1505 &cpu_subsys.dev_root->kobj);
1506 if (WARN_ON(!intel_pstate_kobject))
1507 return;
1508
1509 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1510 if (WARN_ON(rc))
1511 return;
1512
1513 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1514 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1515 WARN_ON(rc);
1516
1517 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1518 WARN_ON(rc);
1519 }
1520
1521 /*
1522 * If per cpu limits are enforced there are no global limits, so
1523 * return without creating max/min_perf_pct attributes
1524 */
1525 if (per_cpu_limits)
1526 return;
1527
1528 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1529 WARN_ON(rc);
1530
1531 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1532 WARN_ON(rc);
1533
1534 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1535 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1536 WARN_ON(rc);
1537 }
1538 }
1539
intel_pstate_sysfs_remove(void)1540 static void __init intel_pstate_sysfs_remove(void)
1541 {
1542 if (!intel_pstate_kobject)
1543 return;
1544
1545 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1546
1547 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1548 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1549 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1550 }
1551
1552 if (!per_cpu_limits) {
1553 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1554 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1555
1556 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1557 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1558 }
1559
1560 kobject_put(intel_pstate_kobject);
1561 }
1562
intel_pstate_sysfs_expose_hwp_dynamic_boost(void)1563 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1564 {
1565 int rc;
1566
1567 if (!hwp_active)
1568 return;
1569
1570 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1571 WARN_ON_ONCE(rc);
1572 }
1573
intel_pstate_sysfs_hide_hwp_dynamic_boost(void)1574 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1575 {
1576 if (!hwp_active)
1577 return;
1578
1579 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1580 }
1581
1582 /************************** sysfs end ************************/
1583
intel_pstate_notify_work(struct work_struct * work)1584 static void intel_pstate_notify_work(struct work_struct *work)
1585 {
1586 struct cpudata *cpudata =
1587 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1588 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1589
1590 if (policy) {
1591 intel_pstate_get_hwp_cap(cpudata);
1592 __intel_pstate_update_max_freq(cpudata, policy);
1593
1594 cpufreq_cpu_release(policy);
1595 }
1596
1597 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1598 }
1599
1600 static DEFINE_SPINLOCK(hwp_notify_lock);
1601 static cpumask_t hwp_intr_enable_mask;
1602
notify_hwp_interrupt(void)1603 void notify_hwp_interrupt(void)
1604 {
1605 unsigned int this_cpu = smp_processor_id();
1606 struct cpudata *cpudata;
1607 unsigned long flags;
1608 u64 value;
1609
1610 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1611 return;
1612
1613 rdmsrl_safe(MSR_HWP_STATUS, &value);
1614 if (!(value & 0x01))
1615 return;
1616
1617 spin_lock_irqsave(&hwp_notify_lock, flags);
1618
1619 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1620 goto ack_intr;
1621
1622 /*
1623 * Currently we never free all_cpu_data. And we can't reach here
1624 * without this allocated. But for safety for future changes, added
1625 * check.
1626 */
1627 if (unlikely(!READ_ONCE(all_cpu_data)))
1628 goto ack_intr;
1629
1630 /*
1631 * The free is done during cleanup, when cpufreq registry is failed.
1632 * We wouldn't be here if it fails on init or switch status. But for
1633 * future changes, added check.
1634 */
1635 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1636 if (unlikely(!cpudata))
1637 goto ack_intr;
1638
1639 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1640
1641 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1642
1643 return;
1644
1645 ack_intr:
1646 wrmsrl_safe(MSR_HWP_STATUS, 0);
1647 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1648 }
1649
intel_pstate_disable_hwp_interrupt(struct cpudata * cpudata)1650 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1651 {
1652 unsigned long flags;
1653
1654 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1655 return;
1656
1657 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1658 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1659
1660 spin_lock_irqsave(&hwp_notify_lock, flags);
1661 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1662 cancel_delayed_work(&cpudata->hwp_notify_work);
1663 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1664 }
1665
intel_pstate_enable_hwp_interrupt(struct cpudata * cpudata)1666 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1667 {
1668 /* Enable HWP notification interrupt for guaranteed performance change */
1669 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1670 unsigned long flags;
1671
1672 spin_lock_irqsave(&hwp_notify_lock, flags);
1673 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1674 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1675 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1676
1677 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1678 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1679 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1680 }
1681 }
1682
intel_pstate_update_epp_defaults(struct cpudata * cpudata)1683 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1684 {
1685 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1686
1687 /*
1688 * If this CPU gen doesn't call for change in balance_perf
1689 * EPP return.
1690 */
1691 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1692 return;
1693
1694 /*
1695 * If powerup EPP is something other than chipset default 0x80 and
1696 * - is more performance oriented than 0x80 (default balance_perf EPP)
1697 * - But less performance oriented than performance EPP
1698 * then use this as new balance_perf EPP.
1699 */
1700 if (cpudata->epp_default < HWP_EPP_BALANCE_PERFORMANCE &&
1701 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1702 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1703 return;
1704 }
1705
1706 /*
1707 * Use hard coded value per gen to update the balance_perf
1708 * and default EPP.
1709 */
1710 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1711 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1712 }
1713
intel_pstate_hwp_enable(struct cpudata * cpudata)1714 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1715 {
1716 /* First disable HWP notification interrupt till we activate again */
1717 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1718 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1719
1720 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1721
1722 intel_pstate_enable_hwp_interrupt(cpudata);
1723
1724 if (cpudata->epp_default >= 0)
1725 return;
1726
1727 intel_pstate_update_epp_defaults(cpudata);
1728 }
1729
atom_get_min_pstate(int not_used)1730 static int atom_get_min_pstate(int not_used)
1731 {
1732 u64 value;
1733
1734 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1735 return (value >> 8) & 0x7F;
1736 }
1737
atom_get_max_pstate(int not_used)1738 static int atom_get_max_pstate(int not_used)
1739 {
1740 u64 value;
1741
1742 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1743 return (value >> 16) & 0x7F;
1744 }
1745
atom_get_turbo_pstate(int not_used)1746 static int atom_get_turbo_pstate(int not_used)
1747 {
1748 u64 value;
1749
1750 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1751 return value & 0x7F;
1752 }
1753
atom_get_val(struct cpudata * cpudata,int pstate)1754 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1755 {
1756 u64 val;
1757 int32_t vid_fp;
1758 u32 vid;
1759
1760 val = (u64)pstate << 8;
1761 if (global.no_turbo && !global.turbo_disabled)
1762 val |= (u64)1 << 32;
1763
1764 vid_fp = cpudata->vid.min + mul_fp(
1765 int_tofp(pstate - cpudata->pstate.min_pstate),
1766 cpudata->vid.ratio);
1767
1768 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1769 vid = ceiling_fp(vid_fp);
1770
1771 if (pstate > cpudata->pstate.max_pstate)
1772 vid = cpudata->vid.turbo;
1773
1774 return val | vid;
1775 }
1776
silvermont_get_scaling(void)1777 static int silvermont_get_scaling(void)
1778 {
1779 u64 value;
1780 int i;
1781 /* Defined in Table 35-6 from SDM (Sept 2015) */
1782 static int silvermont_freq_table[] = {
1783 83300, 100000, 133300, 116700, 80000};
1784
1785 rdmsrl(MSR_FSB_FREQ, value);
1786 i = value & 0x7;
1787 WARN_ON(i > 4);
1788
1789 return silvermont_freq_table[i];
1790 }
1791
airmont_get_scaling(void)1792 static int airmont_get_scaling(void)
1793 {
1794 u64 value;
1795 int i;
1796 /* Defined in Table 35-10 from SDM (Sept 2015) */
1797 static int airmont_freq_table[] = {
1798 83300, 100000, 133300, 116700, 80000,
1799 93300, 90000, 88900, 87500};
1800
1801 rdmsrl(MSR_FSB_FREQ, value);
1802 i = value & 0xF;
1803 WARN_ON(i > 8);
1804
1805 return airmont_freq_table[i];
1806 }
1807
atom_get_vid(struct cpudata * cpudata)1808 static void atom_get_vid(struct cpudata *cpudata)
1809 {
1810 u64 value;
1811
1812 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1813 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1814 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1815 cpudata->vid.ratio = div_fp(
1816 cpudata->vid.max - cpudata->vid.min,
1817 int_tofp(cpudata->pstate.max_pstate -
1818 cpudata->pstate.min_pstate));
1819
1820 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1821 cpudata->vid.turbo = value & 0x7f;
1822 }
1823
core_get_min_pstate(int cpu)1824 static int core_get_min_pstate(int cpu)
1825 {
1826 u64 value;
1827
1828 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1829 return (value >> 40) & 0xFF;
1830 }
1831
core_get_max_pstate_physical(int cpu)1832 static int core_get_max_pstate_physical(int cpu)
1833 {
1834 u64 value;
1835
1836 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1837 return (value >> 8) & 0xFF;
1838 }
1839
core_get_tdp_ratio(int cpu,u64 plat_info)1840 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1841 {
1842 /* Check how many TDP levels present */
1843 if (plat_info & 0x600000000) {
1844 u64 tdp_ctrl;
1845 u64 tdp_ratio;
1846 int tdp_msr;
1847 int err;
1848
1849 /* Get the TDP level (0, 1, 2) to get ratios */
1850 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1851 if (err)
1852 return err;
1853
1854 /* TDP MSR are continuous starting at 0x648 */
1855 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1856 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1857 if (err)
1858 return err;
1859
1860 /* For level 1 and 2, bits[23:16] contain the ratio */
1861 if (tdp_ctrl & 0x03)
1862 tdp_ratio >>= 16;
1863
1864 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1865 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1866
1867 return (int)tdp_ratio;
1868 }
1869
1870 return -ENXIO;
1871 }
1872
core_get_max_pstate(int cpu)1873 static int core_get_max_pstate(int cpu)
1874 {
1875 u64 tar;
1876 u64 plat_info;
1877 int max_pstate;
1878 int tdp_ratio;
1879 int err;
1880
1881 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1882 max_pstate = (plat_info >> 8) & 0xFF;
1883
1884 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1885 if (tdp_ratio <= 0)
1886 return max_pstate;
1887
1888 if (hwp_active) {
1889 /* Turbo activation ratio is not used on HWP platforms */
1890 return tdp_ratio;
1891 }
1892
1893 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1894 if (!err) {
1895 int tar_levels;
1896
1897 /* Do some sanity checking for safety */
1898 tar_levels = tar & 0xff;
1899 if (tdp_ratio - 1 == tar_levels) {
1900 max_pstate = tar_levels;
1901 pr_debug("max_pstate=TAC %x\n", max_pstate);
1902 }
1903 }
1904
1905 return max_pstate;
1906 }
1907
core_get_turbo_pstate(int cpu)1908 static int core_get_turbo_pstate(int cpu)
1909 {
1910 u64 value;
1911 int nont, ret;
1912
1913 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1914 nont = core_get_max_pstate(cpu);
1915 ret = (value) & 255;
1916 if (ret <= nont)
1917 ret = nont;
1918 return ret;
1919 }
1920
core_get_scaling(void)1921 static inline int core_get_scaling(void)
1922 {
1923 return 100000;
1924 }
1925
core_get_val(struct cpudata * cpudata,int pstate)1926 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1927 {
1928 u64 val;
1929
1930 val = (u64)pstate << 8;
1931 if (global.no_turbo && !global.turbo_disabled)
1932 val |= (u64)1 << 32;
1933
1934 return val;
1935 }
1936
knl_get_aperf_mperf_shift(void)1937 static int knl_get_aperf_mperf_shift(void)
1938 {
1939 return 10;
1940 }
1941
knl_get_turbo_pstate(int cpu)1942 static int knl_get_turbo_pstate(int cpu)
1943 {
1944 u64 value;
1945 int nont, ret;
1946
1947 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1948 nont = core_get_max_pstate(cpu);
1949 ret = (((value) >> 8) & 0xFF);
1950 if (ret <= nont)
1951 ret = nont;
1952 return ret;
1953 }
1954
hybrid_get_type(void * data)1955 static void hybrid_get_type(void *data)
1956 {
1957 u8 *cpu_type = data;
1958
1959 *cpu_type = get_this_hybrid_cpu_type();
1960 }
1961
hybrid_get_cpu_scaling(int cpu)1962 static int hybrid_get_cpu_scaling(int cpu)
1963 {
1964 u8 cpu_type = 0;
1965
1966 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1967 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1968 if (cpu_type == 0x40)
1969 return 78741;
1970
1971 return core_get_scaling();
1972 }
1973
intel_pstate_set_pstate(struct cpudata * cpu,int pstate)1974 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1975 {
1976 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1977 cpu->pstate.current_pstate = pstate;
1978 /*
1979 * Generally, there is no guarantee that this code will always run on
1980 * the CPU being updated, so force the register update to run on the
1981 * right CPU.
1982 */
1983 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1984 pstate_funcs.get_val(cpu, pstate));
1985 }
1986
intel_pstate_set_min_pstate(struct cpudata * cpu)1987 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1988 {
1989 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1990 }
1991
intel_pstate_max_within_limits(struct cpudata * cpu)1992 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1993 {
1994 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1995
1996 update_turbo_state();
1997 intel_pstate_set_pstate(cpu, pstate);
1998 }
1999
intel_pstate_get_cpu_pstates(struct cpudata * cpu)2000 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2001 {
2002 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2003 int perf_ctl_scaling = pstate_funcs.get_scaling();
2004
2005 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2006 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2007 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2008
2009 if (hwp_active && !hwp_mode_bdw) {
2010 __intel_pstate_get_hwp_cap(cpu);
2011
2012 if (pstate_funcs.get_cpu_scaling) {
2013 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2014 if (cpu->pstate.scaling != perf_ctl_scaling)
2015 intel_pstate_hybrid_hwp_adjust(cpu);
2016 } else {
2017 cpu->pstate.scaling = perf_ctl_scaling;
2018 }
2019 } else {
2020 cpu->pstate.scaling = perf_ctl_scaling;
2021 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2022 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2023 }
2024
2025 if (cpu->pstate.scaling == perf_ctl_scaling) {
2026 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2027 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2028 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2029 }
2030
2031 if (pstate_funcs.get_aperf_mperf_shift)
2032 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2033
2034 if (pstate_funcs.get_vid)
2035 pstate_funcs.get_vid(cpu);
2036
2037 intel_pstate_set_min_pstate(cpu);
2038 }
2039
2040 /*
2041 * Long hold time will keep high perf limits for long time,
2042 * which negatively impacts perf/watt for some workloads,
2043 * like specpower. 3ms is based on experiements on some
2044 * workoads.
2045 */
2046 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2047
intel_pstate_hwp_boost_up(struct cpudata * cpu)2048 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2049 {
2050 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2051 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2052 u32 max_limit = (hwp_req & 0xff00) >> 8;
2053 u32 min_limit = (hwp_req & 0xff);
2054 u32 boost_level1;
2055
2056 /*
2057 * Cases to consider (User changes via sysfs or boot time):
2058 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2059 * No boost, return.
2060 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2061 * Should result in one level boost only for P0.
2062 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2063 * Should result in two level boost:
2064 * (min + p1)/2 and P1.
2065 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2066 * Should result in three level boost:
2067 * (min + p1)/2, P1 and P0.
2068 */
2069
2070 /* If max and min are equal or already at max, nothing to boost */
2071 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2072 return;
2073
2074 if (!cpu->hwp_boost_min)
2075 cpu->hwp_boost_min = min_limit;
2076
2077 /* level at half way mark between min and guranteed */
2078 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2079
2080 if (cpu->hwp_boost_min < boost_level1)
2081 cpu->hwp_boost_min = boost_level1;
2082 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2083 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2084 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2085 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2086 cpu->hwp_boost_min = max_limit;
2087 else
2088 return;
2089
2090 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2091 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2092 cpu->last_update = cpu->sample.time;
2093 }
2094
intel_pstate_hwp_boost_down(struct cpudata * cpu)2095 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2096 {
2097 if (cpu->hwp_boost_min) {
2098 bool expired;
2099
2100 /* Check if we are idle for hold time to boost down */
2101 expired = time_after64(cpu->sample.time, cpu->last_update +
2102 hwp_boost_hold_time_ns);
2103 if (expired) {
2104 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2105 cpu->hwp_boost_min = 0;
2106 }
2107 }
2108 cpu->last_update = cpu->sample.time;
2109 }
2110
intel_pstate_update_util_hwp_local(struct cpudata * cpu,u64 time)2111 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2112 u64 time)
2113 {
2114 cpu->sample.time = time;
2115
2116 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2117 bool do_io = false;
2118
2119 cpu->sched_flags = 0;
2120 /*
2121 * Set iowait_boost flag and update time. Since IO WAIT flag
2122 * is set all the time, we can't just conclude that there is
2123 * some IO bound activity is scheduled on this CPU with just
2124 * one occurrence. If we receive at least two in two
2125 * consecutive ticks, then we treat as boost candidate.
2126 */
2127 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2128 do_io = true;
2129
2130 cpu->last_io_update = time;
2131
2132 if (do_io)
2133 intel_pstate_hwp_boost_up(cpu);
2134
2135 } else {
2136 intel_pstate_hwp_boost_down(cpu);
2137 }
2138 }
2139
intel_pstate_update_util_hwp(struct update_util_data * data,u64 time,unsigned int flags)2140 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2141 u64 time, unsigned int flags)
2142 {
2143 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2144
2145 cpu->sched_flags |= flags;
2146
2147 if (smp_processor_id() == cpu->cpu)
2148 intel_pstate_update_util_hwp_local(cpu, time);
2149 }
2150
intel_pstate_calc_avg_perf(struct cpudata * cpu)2151 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2152 {
2153 struct sample *sample = &cpu->sample;
2154
2155 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2156 }
2157
intel_pstate_sample(struct cpudata * cpu,u64 time)2158 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2159 {
2160 u64 aperf, mperf;
2161 unsigned long flags;
2162 u64 tsc;
2163
2164 local_irq_save(flags);
2165 rdmsrl(MSR_IA32_APERF, aperf);
2166 rdmsrl(MSR_IA32_MPERF, mperf);
2167 tsc = rdtsc();
2168 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2169 local_irq_restore(flags);
2170 return false;
2171 }
2172 local_irq_restore(flags);
2173
2174 cpu->last_sample_time = cpu->sample.time;
2175 cpu->sample.time = time;
2176 cpu->sample.aperf = aperf;
2177 cpu->sample.mperf = mperf;
2178 cpu->sample.tsc = tsc;
2179 cpu->sample.aperf -= cpu->prev_aperf;
2180 cpu->sample.mperf -= cpu->prev_mperf;
2181 cpu->sample.tsc -= cpu->prev_tsc;
2182
2183 cpu->prev_aperf = aperf;
2184 cpu->prev_mperf = mperf;
2185 cpu->prev_tsc = tsc;
2186 /*
2187 * First time this function is invoked in a given cycle, all of the
2188 * previous sample data fields are equal to zero or stale and they must
2189 * be populated with meaningful numbers for things to work, so assume
2190 * that sample.time will always be reset before setting the utilization
2191 * update hook and make the caller skip the sample then.
2192 */
2193 if (cpu->last_sample_time) {
2194 intel_pstate_calc_avg_perf(cpu);
2195 return true;
2196 }
2197 return false;
2198 }
2199
get_avg_frequency(struct cpudata * cpu)2200 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2201 {
2202 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2203 }
2204
get_avg_pstate(struct cpudata * cpu)2205 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2206 {
2207 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2208 cpu->sample.core_avg_perf);
2209 }
2210
get_target_pstate(struct cpudata * cpu)2211 static inline int32_t get_target_pstate(struct cpudata *cpu)
2212 {
2213 struct sample *sample = &cpu->sample;
2214 int32_t busy_frac;
2215 int target, avg_pstate;
2216
2217 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2218 sample->tsc);
2219
2220 if (busy_frac < cpu->iowait_boost)
2221 busy_frac = cpu->iowait_boost;
2222
2223 sample->busy_scaled = busy_frac * 100;
2224
2225 target = global.no_turbo || global.turbo_disabled ?
2226 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2227 target += target >> 2;
2228 target = mul_fp(target, busy_frac);
2229 if (target < cpu->pstate.min_pstate)
2230 target = cpu->pstate.min_pstate;
2231
2232 /*
2233 * If the average P-state during the previous cycle was higher than the
2234 * current target, add 50% of the difference to the target to reduce
2235 * possible performance oscillations and offset possible performance
2236 * loss related to moving the workload from one CPU to another within
2237 * a package/module.
2238 */
2239 avg_pstate = get_avg_pstate(cpu);
2240 if (avg_pstate > target)
2241 target += (avg_pstate - target) >> 1;
2242
2243 return target;
2244 }
2245
intel_pstate_prepare_request(struct cpudata * cpu,int pstate)2246 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2247 {
2248 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2249 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2250
2251 return clamp_t(int, pstate, min_pstate, max_pstate);
2252 }
2253
intel_pstate_update_pstate(struct cpudata * cpu,int pstate)2254 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2255 {
2256 if (pstate == cpu->pstate.current_pstate)
2257 return;
2258
2259 cpu->pstate.current_pstate = pstate;
2260 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2261 }
2262
intel_pstate_adjust_pstate(struct cpudata * cpu)2263 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2264 {
2265 int from = cpu->pstate.current_pstate;
2266 struct sample *sample;
2267 int target_pstate;
2268
2269 update_turbo_state();
2270
2271 target_pstate = get_target_pstate(cpu);
2272 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2273 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2274 intel_pstate_update_pstate(cpu, target_pstate);
2275
2276 sample = &cpu->sample;
2277 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2278 fp_toint(sample->busy_scaled),
2279 from,
2280 cpu->pstate.current_pstate,
2281 sample->mperf,
2282 sample->aperf,
2283 sample->tsc,
2284 get_avg_frequency(cpu),
2285 fp_toint(cpu->iowait_boost * 100));
2286 }
2287
intel_pstate_update_util(struct update_util_data * data,u64 time,unsigned int flags)2288 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2289 unsigned int flags)
2290 {
2291 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2292 u64 delta_ns;
2293
2294 /* Don't allow remote callbacks */
2295 if (smp_processor_id() != cpu->cpu)
2296 return;
2297
2298 delta_ns = time - cpu->last_update;
2299 if (flags & SCHED_CPUFREQ_IOWAIT) {
2300 /* Start over if the CPU may have been idle. */
2301 if (delta_ns > TICK_NSEC) {
2302 cpu->iowait_boost = ONE_EIGHTH_FP;
2303 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2304 cpu->iowait_boost <<= 1;
2305 if (cpu->iowait_boost > int_tofp(1))
2306 cpu->iowait_boost = int_tofp(1);
2307 } else {
2308 cpu->iowait_boost = ONE_EIGHTH_FP;
2309 }
2310 } else if (cpu->iowait_boost) {
2311 /* Clear iowait_boost if the CPU may have been idle. */
2312 if (delta_ns > TICK_NSEC)
2313 cpu->iowait_boost = 0;
2314 else
2315 cpu->iowait_boost >>= 1;
2316 }
2317 cpu->last_update = time;
2318 delta_ns = time - cpu->sample.time;
2319 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2320 return;
2321
2322 if (intel_pstate_sample(cpu, time))
2323 intel_pstate_adjust_pstate(cpu);
2324 }
2325
2326 static struct pstate_funcs core_funcs = {
2327 .get_max = core_get_max_pstate,
2328 .get_max_physical = core_get_max_pstate_physical,
2329 .get_min = core_get_min_pstate,
2330 .get_turbo = core_get_turbo_pstate,
2331 .get_scaling = core_get_scaling,
2332 .get_val = core_get_val,
2333 };
2334
2335 static const struct pstate_funcs silvermont_funcs = {
2336 .get_max = atom_get_max_pstate,
2337 .get_max_physical = atom_get_max_pstate,
2338 .get_min = atom_get_min_pstate,
2339 .get_turbo = atom_get_turbo_pstate,
2340 .get_val = atom_get_val,
2341 .get_scaling = silvermont_get_scaling,
2342 .get_vid = atom_get_vid,
2343 };
2344
2345 static const struct pstate_funcs airmont_funcs = {
2346 .get_max = atom_get_max_pstate,
2347 .get_max_physical = atom_get_max_pstate,
2348 .get_min = atom_get_min_pstate,
2349 .get_turbo = atom_get_turbo_pstate,
2350 .get_val = atom_get_val,
2351 .get_scaling = airmont_get_scaling,
2352 .get_vid = atom_get_vid,
2353 };
2354
2355 static const struct pstate_funcs knl_funcs = {
2356 .get_max = core_get_max_pstate,
2357 .get_max_physical = core_get_max_pstate_physical,
2358 .get_min = core_get_min_pstate,
2359 .get_turbo = knl_get_turbo_pstate,
2360 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2361 .get_scaling = core_get_scaling,
2362 .get_val = core_get_val,
2363 };
2364
2365 #define X86_MATCH(model, policy) \
2366 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2367 X86_FEATURE_APERFMPERF, &policy)
2368
2369 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2370 X86_MATCH(SANDYBRIDGE, core_funcs),
2371 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2372 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2373 X86_MATCH(IVYBRIDGE, core_funcs),
2374 X86_MATCH(HASWELL, core_funcs),
2375 X86_MATCH(BROADWELL, core_funcs),
2376 X86_MATCH(IVYBRIDGE_X, core_funcs),
2377 X86_MATCH(HASWELL_X, core_funcs),
2378 X86_MATCH(HASWELL_L, core_funcs),
2379 X86_MATCH(HASWELL_G, core_funcs),
2380 X86_MATCH(BROADWELL_G, core_funcs),
2381 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2382 X86_MATCH(SKYLAKE_L, core_funcs),
2383 X86_MATCH(BROADWELL_X, core_funcs),
2384 X86_MATCH(SKYLAKE, core_funcs),
2385 X86_MATCH(BROADWELL_D, core_funcs),
2386 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2387 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2388 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2389 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2390 X86_MATCH(SKYLAKE_X, core_funcs),
2391 X86_MATCH(COMETLAKE, core_funcs),
2392 X86_MATCH(ICELAKE_X, core_funcs),
2393 X86_MATCH(TIGERLAKE, core_funcs),
2394 {}
2395 };
2396 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2397
2398 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2399 X86_MATCH(BROADWELL_D, core_funcs),
2400 X86_MATCH(BROADWELL_X, core_funcs),
2401 X86_MATCH(SKYLAKE_X, core_funcs),
2402 X86_MATCH(ICELAKE_X, core_funcs),
2403 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2404 {}
2405 };
2406
2407 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2408 X86_MATCH(KABYLAKE, core_funcs),
2409 {}
2410 };
2411
2412 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2413 X86_MATCH(SKYLAKE_X, core_funcs),
2414 X86_MATCH(SKYLAKE, core_funcs),
2415 {}
2416 };
2417
intel_pstate_init_cpu(unsigned int cpunum)2418 static int intel_pstate_init_cpu(unsigned int cpunum)
2419 {
2420 struct cpudata *cpu;
2421
2422 cpu = all_cpu_data[cpunum];
2423
2424 if (!cpu) {
2425 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2426 if (!cpu)
2427 return -ENOMEM;
2428
2429 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2430
2431 cpu->cpu = cpunum;
2432
2433 cpu->epp_default = -EINVAL;
2434
2435 if (hwp_active) {
2436 const struct x86_cpu_id *id;
2437
2438 intel_pstate_hwp_enable(cpu);
2439
2440 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2441 if (id && intel_pstate_acpi_pm_profile_server())
2442 hwp_boost = true;
2443 }
2444 } else if (hwp_active) {
2445 /*
2446 * Re-enable HWP in case this happens after a resume from ACPI
2447 * S3 if the CPU was offline during the whole system/resume
2448 * cycle.
2449 */
2450 intel_pstate_hwp_reenable(cpu);
2451 }
2452
2453 cpu->epp_powersave = -EINVAL;
2454 cpu->epp_policy = 0;
2455
2456 intel_pstate_get_cpu_pstates(cpu);
2457
2458 pr_debug("controlling: cpu %d\n", cpunum);
2459
2460 return 0;
2461 }
2462
intel_pstate_set_update_util_hook(unsigned int cpu_num)2463 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2464 {
2465 struct cpudata *cpu = all_cpu_data[cpu_num];
2466
2467 if (hwp_active && !hwp_boost)
2468 return;
2469
2470 if (cpu->update_util_set)
2471 return;
2472
2473 /* Prevent intel_pstate_update_util() from using stale data. */
2474 cpu->sample.time = 0;
2475 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2476 (hwp_active ?
2477 intel_pstate_update_util_hwp :
2478 intel_pstate_update_util));
2479 cpu->update_util_set = true;
2480 }
2481
intel_pstate_clear_update_util_hook(unsigned int cpu)2482 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2483 {
2484 struct cpudata *cpu_data = all_cpu_data[cpu];
2485
2486 if (!cpu_data->update_util_set)
2487 return;
2488
2489 cpufreq_remove_update_util_hook(cpu);
2490 cpu_data->update_util_set = false;
2491 synchronize_rcu();
2492 }
2493
intel_pstate_get_max_freq(struct cpudata * cpu)2494 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2495 {
2496 return global.turbo_disabled || global.no_turbo ?
2497 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2498 }
2499
intel_pstate_update_perf_limits(struct cpudata * cpu,unsigned int policy_min,unsigned int policy_max)2500 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2501 unsigned int policy_min,
2502 unsigned int policy_max)
2503 {
2504 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2505 int32_t max_policy_perf, min_policy_perf;
2506
2507 max_policy_perf = policy_max / perf_ctl_scaling;
2508 if (policy_max == policy_min) {
2509 min_policy_perf = max_policy_perf;
2510 } else {
2511 min_policy_perf = policy_min / perf_ctl_scaling;
2512 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2513 0, max_policy_perf);
2514 }
2515
2516 /*
2517 * HWP needs some special consideration, because HWP_REQUEST uses
2518 * abstract values to represent performance rather than pure ratios.
2519 */
2520 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2521 int freq;
2522
2523 freq = max_policy_perf * perf_ctl_scaling;
2524 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2525 freq = min_policy_perf * perf_ctl_scaling;
2526 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2527 }
2528
2529 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2530 cpu->cpu, min_policy_perf, max_policy_perf);
2531
2532 /* Normalize user input to [min_perf, max_perf] */
2533 if (per_cpu_limits) {
2534 cpu->min_perf_ratio = min_policy_perf;
2535 cpu->max_perf_ratio = max_policy_perf;
2536 } else {
2537 int turbo_max = cpu->pstate.turbo_pstate;
2538 int32_t global_min, global_max;
2539
2540 /* Global limits are in percent of the maximum turbo P-state. */
2541 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2542 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2543 global_min = clamp_t(int32_t, global_min, 0, global_max);
2544
2545 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2546 global_min, global_max);
2547
2548 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2549 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2550 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2551 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2552
2553 /* Make sure min_perf <= max_perf */
2554 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2555 cpu->max_perf_ratio);
2556
2557 }
2558 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2559 cpu->max_perf_ratio,
2560 cpu->min_perf_ratio);
2561 }
2562
intel_pstate_set_policy(struct cpufreq_policy * policy)2563 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2564 {
2565 struct cpudata *cpu;
2566
2567 if (!policy->cpuinfo.max_freq)
2568 return -ENODEV;
2569
2570 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2571 policy->cpuinfo.max_freq, policy->max);
2572
2573 cpu = all_cpu_data[policy->cpu];
2574 cpu->policy = policy->policy;
2575
2576 mutex_lock(&intel_pstate_limits_lock);
2577
2578 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2579
2580 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2581 /*
2582 * NOHZ_FULL CPUs need this as the governor callback may not
2583 * be invoked on them.
2584 */
2585 intel_pstate_clear_update_util_hook(policy->cpu);
2586 intel_pstate_max_within_limits(cpu);
2587 } else {
2588 intel_pstate_set_update_util_hook(policy->cpu);
2589 }
2590
2591 if (hwp_active) {
2592 /*
2593 * When hwp_boost was active before and dynamically it
2594 * was turned off, in that case we need to clear the
2595 * update util hook.
2596 */
2597 if (!hwp_boost)
2598 intel_pstate_clear_update_util_hook(policy->cpu);
2599 intel_pstate_hwp_set(policy->cpu);
2600 }
2601 /*
2602 * policy->cur is never updated with the intel_pstate driver, but it
2603 * is used as a stale frequency value. So, keep it within limits.
2604 */
2605 policy->cur = policy->min;
2606
2607 mutex_unlock(&intel_pstate_limits_lock);
2608
2609 return 0;
2610 }
2611
intel_pstate_adjust_policy_max(struct cpudata * cpu,struct cpufreq_policy_data * policy)2612 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2613 struct cpufreq_policy_data *policy)
2614 {
2615 if (!hwp_active &&
2616 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2617 policy->max < policy->cpuinfo.max_freq &&
2618 policy->max > cpu->pstate.max_freq) {
2619 pr_debug("policy->max > max non turbo frequency\n");
2620 policy->max = policy->cpuinfo.max_freq;
2621 }
2622 }
2623
intel_pstate_verify_cpu_policy(struct cpudata * cpu,struct cpufreq_policy_data * policy)2624 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2625 struct cpufreq_policy_data *policy)
2626 {
2627 int max_freq;
2628
2629 update_turbo_state();
2630 if (hwp_active) {
2631 intel_pstate_get_hwp_cap(cpu);
2632 max_freq = global.no_turbo || global.turbo_disabled ?
2633 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2634 } else {
2635 max_freq = intel_pstate_get_max_freq(cpu);
2636 }
2637 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2638
2639 intel_pstate_adjust_policy_max(cpu, policy);
2640 }
2641
intel_pstate_verify_policy(struct cpufreq_policy_data * policy)2642 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2643 {
2644 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2645
2646 return 0;
2647 }
2648
intel_cpufreq_cpu_offline(struct cpufreq_policy * policy)2649 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2650 {
2651 struct cpudata *cpu = all_cpu_data[policy->cpu];
2652
2653 pr_debug("CPU %d going offline\n", cpu->cpu);
2654
2655 if (cpu->suspended)
2656 return 0;
2657
2658 /*
2659 * If the CPU is an SMT thread and it goes offline with the performance
2660 * settings different from the minimum, it will prevent its sibling
2661 * from getting to lower performance levels, so force the minimum
2662 * performance on CPU offline to prevent that from happening.
2663 */
2664 if (hwp_active)
2665 intel_pstate_hwp_offline(cpu);
2666 else
2667 intel_pstate_set_min_pstate(cpu);
2668
2669 intel_pstate_exit_perf_limits(policy);
2670
2671 return 0;
2672 }
2673
intel_pstate_cpu_online(struct cpufreq_policy * policy)2674 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2675 {
2676 struct cpudata *cpu = all_cpu_data[policy->cpu];
2677
2678 pr_debug("CPU %d going online\n", cpu->cpu);
2679
2680 intel_pstate_init_acpi_perf_limits(policy);
2681
2682 if (hwp_active) {
2683 /*
2684 * Re-enable HWP and clear the "suspended" flag to let "resume"
2685 * know that it need not do that.
2686 */
2687 intel_pstate_hwp_reenable(cpu);
2688 cpu->suspended = false;
2689 }
2690
2691 return 0;
2692 }
2693
intel_pstate_cpu_offline(struct cpufreq_policy * policy)2694 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2695 {
2696 intel_pstate_clear_update_util_hook(policy->cpu);
2697
2698 return intel_cpufreq_cpu_offline(policy);
2699 }
2700
intel_pstate_cpu_exit(struct cpufreq_policy * policy)2701 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2702 {
2703 pr_debug("CPU %d exiting\n", policy->cpu);
2704
2705 policy->fast_switch_possible = false;
2706
2707 return 0;
2708 }
2709
__intel_pstate_cpu_init(struct cpufreq_policy * policy)2710 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2711 {
2712 struct cpudata *cpu;
2713 int rc;
2714
2715 rc = intel_pstate_init_cpu(policy->cpu);
2716 if (rc)
2717 return rc;
2718
2719 cpu = all_cpu_data[policy->cpu];
2720
2721 cpu->max_perf_ratio = 0xFF;
2722 cpu->min_perf_ratio = 0;
2723
2724 /* cpuinfo and default policy values */
2725 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2726 update_turbo_state();
2727 global.turbo_disabled_mf = global.turbo_disabled;
2728 policy->cpuinfo.max_freq = global.turbo_disabled ?
2729 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2730
2731 policy->min = policy->cpuinfo.min_freq;
2732 policy->max = policy->cpuinfo.max_freq;
2733
2734 intel_pstate_init_acpi_perf_limits(policy);
2735
2736 policy->fast_switch_possible = true;
2737
2738 return 0;
2739 }
2740
intel_pstate_cpu_init(struct cpufreq_policy * policy)2741 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2742 {
2743 int ret = __intel_pstate_cpu_init(policy);
2744
2745 if (ret)
2746 return ret;
2747
2748 /*
2749 * Set the policy to powersave to provide a valid fallback value in case
2750 * the default cpufreq governor is neither powersave nor performance.
2751 */
2752 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2753
2754 if (hwp_active) {
2755 struct cpudata *cpu = all_cpu_data[policy->cpu];
2756
2757 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2758 }
2759
2760 return 0;
2761 }
2762
2763 static struct cpufreq_driver intel_pstate = {
2764 .flags = CPUFREQ_CONST_LOOPS,
2765 .verify = intel_pstate_verify_policy,
2766 .setpolicy = intel_pstate_set_policy,
2767 .suspend = intel_pstate_suspend,
2768 .resume = intel_pstate_resume,
2769 .init = intel_pstate_cpu_init,
2770 .exit = intel_pstate_cpu_exit,
2771 .offline = intel_pstate_cpu_offline,
2772 .online = intel_pstate_cpu_online,
2773 .update_limits = intel_pstate_update_limits,
2774 .name = "intel_pstate",
2775 };
2776
intel_cpufreq_verify_policy(struct cpufreq_policy_data * policy)2777 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2778 {
2779 struct cpudata *cpu = all_cpu_data[policy->cpu];
2780
2781 intel_pstate_verify_cpu_policy(cpu, policy);
2782 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2783
2784 return 0;
2785 }
2786
2787 /* Use of trace in passive mode:
2788 *
2789 * In passive mode the trace core_busy field (also known as the
2790 * performance field, and lablelled as such on the graphs; also known as
2791 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2792 * driver call was via the normal or fast switch path. Various graphs
2793 * output from the intel_pstate_tracer.py utility that include core_busy
2794 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2795 * so we use 10 to indicate the normal path through the driver, and
2796 * 90 to indicate the fast switch path through the driver.
2797 * The scaled_busy field is not used, and is set to 0.
2798 */
2799
2800 #define INTEL_PSTATE_TRACE_TARGET 10
2801 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2802
intel_cpufreq_trace(struct cpudata * cpu,unsigned int trace_type,int old_pstate)2803 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2804 {
2805 struct sample *sample;
2806
2807 if (!trace_pstate_sample_enabled())
2808 return;
2809
2810 if (!intel_pstate_sample(cpu, ktime_get()))
2811 return;
2812
2813 sample = &cpu->sample;
2814 trace_pstate_sample(trace_type,
2815 0,
2816 old_pstate,
2817 cpu->pstate.current_pstate,
2818 sample->mperf,
2819 sample->aperf,
2820 sample->tsc,
2821 get_avg_frequency(cpu),
2822 fp_toint(cpu->iowait_boost * 100));
2823 }
2824
intel_cpufreq_hwp_update(struct cpudata * cpu,u32 min,u32 max,u32 desired,bool fast_switch)2825 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2826 u32 desired, bool fast_switch)
2827 {
2828 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2829
2830 value &= ~HWP_MIN_PERF(~0L);
2831 value |= HWP_MIN_PERF(min);
2832
2833 value &= ~HWP_MAX_PERF(~0L);
2834 value |= HWP_MAX_PERF(max);
2835
2836 value &= ~HWP_DESIRED_PERF(~0L);
2837 value |= HWP_DESIRED_PERF(desired);
2838
2839 if (value == prev)
2840 return;
2841
2842 WRITE_ONCE(cpu->hwp_req_cached, value);
2843 if (fast_switch)
2844 wrmsrl(MSR_HWP_REQUEST, value);
2845 else
2846 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2847 }
2848
intel_cpufreq_perf_ctl_update(struct cpudata * cpu,u32 target_pstate,bool fast_switch)2849 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2850 u32 target_pstate, bool fast_switch)
2851 {
2852 if (fast_switch)
2853 wrmsrl(MSR_IA32_PERF_CTL,
2854 pstate_funcs.get_val(cpu, target_pstate));
2855 else
2856 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2857 pstate_funcs.get_val(cpu, target_pstate));
2858 }
2859
intel_cpufreq_update_pstate(struct cpufreq_policy * policy,int target_pstate,bool fast_switch)2860 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2861 int target_pstate, bool fast_switch)
2862 {
2863 struct cpudata *cpu = all_cpu_data[policy->cpu];
2864 int old_pstate = cpu->pstate.current_pstate;
2865
2866 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2867 if (hwp_active) {
2868 int max_pstate = policy->strict_target ?
2869 target_pstate : cpu->max_perf_ratio;
2870
2871 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2872 fast_switch);
2873 } else if (target_pstate != old_pstate) {
2874 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2875 }
2876
2877 cpu->pstate.current_pstate = target_pstate;
2878
2879 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2880 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2881
2882 return target_pstate;
2883 }
2884
intel_cpufreq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)2885 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2886 unsigned int target_freq,
2887 unsigned int relation)
2888 {
2889 struct cpudata *cpu = all_cpu_data[policy->cpu];
2890 struct cpufreq_freqs freqs;
2891 int target_pstate;
2892
2893 update_turbo_state();
2894
2895 freqs.old = policy->cur;
2896 freqs.new = target_freq;
2897
2898 cpufreq_freq_transition_begin(policy, &freqs);
2899
2900 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2901 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2902
2903 freqs.new = target_pstate * cpu->pstate.scaling;
2904
2905 cpufreq_freq_transition_end(policy, &freqs, false);
2906
2907 return 0;
2908 }
2909
intel_cpufreq_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)2910 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2911 unsigned int target_freq)
2912 {
2913 struct cpudata *cpu = all_cpu_data[policy->cpu];
2914 int target_pstate;
2915
2916 update_turbo_state();
2917
2918 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2919
2920 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2921
2922 return target_pstate * cpu->pstate.scaling;
2923 }
2924
intel_cpufreq_adjust_perf(unsigned int cpunum,unsigned long min_perf,unsigned long target_perf,unsigned long capacity)2925 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2926 unsigned long min_perf,
2927 unsigned long target_perf,
2928 unsigned long capacity)
2929 {
2930 struct cpudata *cpu = all_cpu_data[cpunum];
2931 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2932 int old_pstate = cpu->pstate.current_pstate;
2933 int cap_pstate, min_pstate, max_pstate, target_pstate;
2934
2935 update_turbo_state();
2936 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2937 HWP_HIGHEST_PERF(hwp_cap);
2938
2939 /* Optimization: Avoid unnecessary divisions. */
2940
2941 target_pstate = cap_pstate;
2942 if (target_perf < capacity)
2943 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2944
2945 min_pstate = cap_pstate;
2946 if (min_perf < capacity)
2947 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2948
2949 if (min_pstate < cpu->pstate.min_pstate)
2950 min_pstate = cpu->pstate.min_pstate;
2951
2952 if (min_pstate < cpu->min_perf_ratio)
2953 min_pstate = cpu->min_perf_ratio;
2954
2955 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2956 if (max_pstate < min_pstate)
2957 max_pstate = min_pstate;
2958
2959 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2960
2961 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2962
2963 cpu->pstate.current_pstate = target_pstate;
2964 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2965 }
2966
intel_cpufreq_cpu_init(struct cpufreq_policy * policy)2967 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2968 {
2969 struct freq_qos_request *req;
2970 struct cpudata *cpu;
2971 struct device *dev;
2972 int ret, freq;
2973
2974 dev = get_cpu_device(policy->cpu);
2975 if (!dev)
2976 return -ENODEV;
2977
2978 ret = __intel_pstate_cpu_init(policy);
2979 if (ret)
2980 return ret;
2981
2982 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2983 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2984 policy->cur = policy->cpuinfo.min_freq;
2985
2986 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2987 if (!req) {
2988 ret = -ENOMEM;
2989 goto pstate_exit;
2990 }
2991
2992 cpu = all_cpu_data[policy->cpu];
2993
2994 if (hwp_active) {
2995 u64 value;
2996
2997 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
2998
2999 intel_pstate_get_hwp_cap(cpu);
3000
3001 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3002 WRITE_ONCE(cpu->hwp_req_cached, value);
3003
3004 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3005 } else {
3006 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3007 }
3008
3009 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3010
3011 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3012 freq);
3013 if (ret < 0) {
3014 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3015 goto free_req;
3016 }
3017
3018 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3019
3020 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3021 freq);
3022 if (ret < 0) {
3023 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3024 goto remove_min_req;
3025 }
3026
3027 policy->driver_data = req;
3028
3029 return 0;
3030
3031 remove_min_req:
3032 freq_qos_remove_request(req);
3033 free_req:
3034 kfree(req);
3035 pstate_exit:
3036 intel_pstate_exit_perf_limits(policy);
3037
3038 return ret;
3039 }
3040
intel_cpufreq_cpu_exit(struct cpufreq_policy * policy)3041 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3042 {
3043 struct freq_qos_request *req;
3044
3045 req = policy->driver_data;
3046
3047 freq_qos_remove_request(req + 1);
3048 freq_qos_remove_request(req);
3049 kfree(req);
3050
3051 return intel_pstate_cpu_exit(policy);
3052 }
3053
intel_cpufreq_suspend(struct cpufreq_policy * policy)3054 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3055 {
3056 intel_pstate_suspend(policy);
3057
3058 if (hwp_active) {
3059 struct cpudata *cpu = all_cpu_data[policy->cpu];
3060 u64 value = READ_ONCE(cpu->hwp_req_cached);
3061
3062 /*
3063 * Clear the desired perf field in MSR_HWP_REQUEST in case
3064 * intel_cpufreq_adjust_perf() is in use and the last value
3065 * written by it may not be suitable.
3066 */
3067 value &= ~HWP_DESIRED_PERF(~0L);
3068 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3069 WRITE_ONCE(cpu->hwp_req_cached, value);
3070 }
3071
3072 return 0;
3073 }
3074
3075 static struct cpufreq_driver intel_cpufreq = {
3076 .flags = CPUFREQ_CONST_LOOPS,
3077 .verify = intel_cpufreq_verify_policy,
3078 .target = intel_cpufreq_target,
3079 .fast_switch = intel_cpufreq_fast_switch,
3080 .init = intel_cpufreq_cpu_init,
3081 .exit = intel_cpufreq_cpu_exit,
3082 .offline = intel_cpufreq_cpu_offline,
3083 .online = intel_pstate_cpu_online,
3084 .suspend = intel_cpufreq_suspend,
3085 .resume = intel_pstate_resume,
3086 .update_limits = intel_pstate_update_limits,
3087 .name = "intel_cpufreq",
3088 };
3089
3090 static struct cpufreq_driver *default_driver;
3091
intel_pstate_driver_cleanup(void)3092 static void intel_pstate_driver_cleanup(void)
3093 {
3094 unsigned int cpu;
3095
3096 cpus_read_lock();
3097 for_each_online_cpu(cpu) {
3098 if (all_cpu_data[cpu]) {
3099 if (intel_pstate_driver == &intel_pstate)
3100 intel_pstate_clear_update_util_hook(cpu);
3101
3102 spin_lock(&hwp_notify_lock);
3103 kfree(all_cpu_data[cpu]);
3104 WRITE_ONCE(all_cpu_data[cpu], NULL);
3105 spin_unlock(&hwp_notify_lock);
3106 }
3107 }
3108 cpus_read_unlock();
3109
3110 intel_pstate_driver = NULL;
3111 }
3112
intel_pstate_register_driver(struct cpufreq_driver * driver)3113 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3114 {
3115 int ret;
3116
3117 if (driver == &intel_pstate)
3118 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3119
3120 memset(&global, 0, sizeof(global));
3121 global.max_perf_pct = 100;
3122
3123 intel_pstate_driver = driver;
3124 ret = cpufreq_register_driver(intel_pstate_driver);
3125 if (ret) {
3126 intel_pstate_driver_cleanup();
3127 return ret;
3128 }
3129
3130 global.min_perf_pct = min_perf_pct_min();
3131
3132 return 0;
3133 }
3134
intel_pstate_show_status(char * buf)3135 static ssize_t intel_pstate_show_status(char *buf)
3136 {
3137 if (!intel_pstate_driver)
3138 return sprintf(buf, "off\n");
3139
3140 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3141 "active" : "passive");
3142 }
3143
intel_pstate_update_status(const char * buf,size_t size)3144 static int intel_pstate_update_status(const char *buf, size_t size)
3145 {
3146 if (size == 3 && !strncmp(buf, "off", size)) {
3147 if (!intel_pstate_driver)
3148 return -EINVAL;
3149
3150 if (hwp_active)
3151 return -EBUSY;
3152
3153 cpufreq_unregister_driver(intel_pstate_driver);
3154 intel_pstate_driver_cleanup();
3155 return 0;
3156 }
3157
3158 if (size == 6 && !strncmp(buf, "active", size)) {
3159 if (intel_pstate_driver) {
3160 if (intel_pstate_driver == &intel_pstate)
3161 return 0;
3162
3163 cpufreq_unregister_driver(intel_pstate_driver);
3164 }
3165
3166 return intel_pstate_register_driver(&intel_pstate);
3167 }
3168
3169 if (size == 7 && !strncmp(buf, "passive", size)) {
3170 if (intel_pstate_driver) {
3171 if (intel_pstate_driver == &intel_cpufreq)
3172 return 0;
3173
3174 cpufreq_unregister_driver(intel_pstate_driver);
3175 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3176 }
3177
3178 return intel_pstate_register_driver(&intel_cpufreq);
3179 }
3180
3181 return -EINVAL;
3182 }
3183
3184 static int no_load __initdata;
3185 static int no_hwp __initdata;
3186 static int hwp_only __initdata;
3187 static unsigned int force_load __initdata;
3188
intel_pstate_msrs_not_valid(void)3189 static int __init intel_pstate_msrs_not_valid(void)
3190 {
3191 if (!pstate_funcs.get_max(0) ||
3192 !pstate_funcs.get_min(0) ||
3193 !pstate_funcs.get_turbo(0))
3194 return -ENODEV;
3195
3196 return 0;
3197 }
3198
copy_cpu_funcs(struct pstate_funcs * funcs)3199 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3200 {
3201 pstate_funcs.get_max = funcs->get_max;
3202 pstate_funcs.get_max_physical = funcs->get_max_physical;
3203 pstate_funcs.get_min = funcs->get_min;
3204 pstate_funcs.get_turbo = funcs->get_turbo;
3205 pstate_funcs.get_scaling = funcs->get_scaling;
3206 pstate_funcs.get_val = funcs->get_val;
3207 pstate_funcs.get_vid = funcs->get_vid;
3208 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3209 }
3210
3211 #ifdef CONFIG_ACPI
3212
intel_pstate_no_acpi_pss(void)3213 static bool __init intel_pstate_no_acpi_pss(void)
3214 {
3215 int i;
3216
3217 for_each_possible_cpu(i) {
3218 acpi_status status;
3219 union acpi_object *pss;
3220 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3221 struct acpi_processor *pr = per_cpu(processors, i);
3222
3223 if (!pr)
3224 continue;
3225
3226 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3227 if (ACPI_FAILURE(status))
3228 continue;
3229
3230 pss = buffer.pointer;
3231 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3232 kfree(pss);
3233 return false;
3234 }
3235
3236 kfree(pss);
3237 }
3238
3239 pr_debug("ACPI _PSS not found\n");
3240 return true;
3241 }
3242
intel_pstate_no_acpi_pcch(void)3243 static bool __init intel_pstate_no_acpi_pcch(void)
3244 {
3245 acpi_status status;
3246 acpi_handle handle;
3247
3248 status = acpi_get_handle(NULL, "\\_SB", &handle);
3249 if (ACPI_FAILURE(status))
3250 goto not_found;
3251
3252 if (acpi_has_method(handle, "PCCH"))
3253 return false;
3254
3255 not_found:
3256 pr_debug("ACPI PCCH not found\n");
3257 return true;
3258 }
3259
intel_pstate_has_acpi_ppc(void)3260 static bool __init intel_pstate_has_acpi_ppc(void)
3261 {
3262 int i;
3263
3264 for_each_possible_cpu(i) {
3265 struct acpi_processor *pr = per_cpu(processors, i);
3266
3267 if (!pr)
3268 continue;
3269 if (acpi_has_method(pr->handle, "_PPC"))
3270 return true;
3271 }
3272 pr_debug("ACPI _PPC not found\n");
3273 return false;
3274 }
3275
3276 enum {
3277 PSS,
3278 PPC,
3279 };
3280
3281 /* Hardware vendor-specific info that has its own power management modes */
3282 static struct acpi_platform_list plat_info[] __initdata = {
3283 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3284 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3285 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3286 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3287 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3288 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3289 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3290 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3291 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3292 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3293 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3294 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3295 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3296 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3297 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3298 { } /* End */
3299 };
3300
3301 #define BITMASK_OOB (BIT(8) | BIT(18))
3302
intel_pstate_platform_pwr_mgmt_exists(void)3303 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3304 {
3305 const struct x86_cpu_id *id;
3306 u64 misc_pwr;
3307 int idx;
3308
3309 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3310 if (id) {
3311 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3312 if (misc_pwr & BITMASK_OOB) {
3313 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3314 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3315 return true;
3316 }
3317 }
3318
3319 idx = acpi_match_platform_list(plat_info);
3320 if (idx < 0)
3321 return false;
3322
3323 switch (plat_info[idx].data) {
3324 case PSS:
3325 if (!intel_pstate_no_acpi_pss())
3326 return false;
3327
3328 return intel_pstate_no_acpi_pcch();
3329 case PPC:
3330 return intel_pstate_has_acpi_ppc() && !force_load;
3331 }
3332
3333 return false;
3334 }
3335
intel_pstate_request_control_from_smm(void)3336 static void intel_pstate_request_control_from_smm(void)
3337 {
3338 /*
3339 * It may be unsafe to request P-states control from SMM if _PPC support
3340 * has not been enabled.
3341 */
3342 if (acpi_ppc)
3343 acpi_processor_pstate_control();
3344 }
3345 #else /* CONFIG_ACPI not enabled */
intel_pstate_platform_pwr_mgmt_exists(void)3346 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
intel_pstate_has_acpi_ppc(void)3347 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
intel_pstate_request_control_from_smm(void)3348 static inline void intel_pstate_request_control_from_smm(void) {}
3349 #endif /* CONFIG_ACPI */
3350
3351 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3352
3353 #define X86_MATCH_HWP(model, hwp_mode) \
3354 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3355 X86_FEATURE_HWP, hwp_mode)
3356
3357 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3358 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3359 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3360 X86_MATCH_HWP(ANY, 0),
3361 {}
3362 };
3363
intel_pstate_hwp_is_enabled(void)3364 static bool intel_pstate_hwp_is_enabled(void)
3365 {
3366 u64 value;
3367
3368 rdmsrl(MSR_PM_ENABLE, value);
3369 return !!(value & 0x1);
3370 }
3371
3372 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3373 /*
3374 * Set EPP value as 102, this is the max suggested EPP
3375 * which can result in one core turbo frequency for
3376 * AlderLake Mobile CPUs.
3377 */
3378 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3379 {}
3380 };
3381
intel_pstate_init(void)3382 static int __init intel_pstate_init(void)
3383 {
3384 static struct cpudata **_all_cpu_data;
3385 const struct x86_cpu_id *id;
3386 int rc;
3387
3388 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3389 return -ENODEV;
3390
3391 id = x86_match_cpu(hwp_support_ids);
3392 if (id) {
3393 bool hwp_forced = intel_pstate_hwp_is_enabled();
3394
3395 if (hwp_forced)
3396 pr_info("HWP enabled by BIOS\n");
3397 else if (no_load)
3398 return -ENODEV;
3399
3400 copy_cpu_funcs(&core_funcs);
3401 /*
3402 * Avoid enabling HWP for processors without EPP support,
3403 * because that means incomplete HWP implementation which is a
3404 * corner case and supporting it is generally problematic.
3405 *
3406 * If HWP is enabled already, though, there is no choice but to
3407 * deal with it.
3408 */
3409 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3410 WRITE_ONCE(hwp_active, 1);
3411 hwp_mode_bdw = id->driver_data;
3412 intel_pstate.attr = hwp_cpufreq_attrs;
3413 intel_cpufreq.attr = hwp_cpufreq_attrs;
3414 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3415 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3416 if (!default_driver)
3417 default_driver = &intel_pstate;
3418
3419 if (boot_cpu_has(X86_FEATURE_HYBRID_CPU))
3420 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling;
3421
3422 goto hwp_cpu_matched;
3423 }
3424 pr_info("HWP not enabled\n");
3425 } else {
3426 if (no_load)
3427 return -ENODEV;
3428
3429 id = x86_match_cpu(intel_pstate_cpu_ids);
3430 if (!id) {
3431 pr_info("CPU model not supported\n");
3432 return -ENODEV;
3433 }
3434
3435 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3436 }
3437
3438 if (intel_pstate_msrs_not_valid()) {
3439 pr_info("Invalid MSRs\n");
3440 return -ENODEV;
3441 }
3442 /* Without HWP start in the passive mode. */
3443 if (!default_driver)
3444 default_driver = &intel_cpufreq;
3445
3446 hwp_cpu_matched:
3447 /*
3448 * The Intel pstate driver will be ignored if the platform
3449 * firmware has its own power management modes.
3450 */
3451 if (intel_pstate_platform_pwr_mgmt_exists()) {
3452 pr_info("P-states controlled by the platform\n");
3453 return -ENODEV;
3454 }
3455
3456 if (!hwp_active && hwp_only)
3457 return -ENOTSUPP;
3458
3459 pr_info("Intel P-state driver initializing\n");
3460
3461 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3462 if (!_all_cpu_data)
3463 return -ENOMEM;
3464
3465 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3466
3467 intel_pstate_request_control_from_smm();
3468
3469 intel_pstate_sysfs_expose_params();
3470
3471 if (hwp_active) {
3472 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3473
3474 if (id)
3475 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3476 }
3477
3478 mutex_lock(&intel_pstate_driver_lock);
3479 rc = intel_pstate_register_driver(default_driver);
3480 mutex_unlock(&intel_pstate_driver_lock);
3481 if (rc) {
3482 intel_pstate_sysfs_remove();
3483 return rc;
3484 }
3485
3486 if (hwp_active) {
3487 const struct x86_cpu_id *id;
3488
3489 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3490 if (id) {
3491 set_power_ctl_ee_state(false);
3492 pr_info("Disabling energy efficiency optimization\n");
3493 }
3494
3495 pr_info("HWP enabled\n");
3496 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3497 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3498 }
3499
3500 return 0;
3501 }
3502 device_initcall(intel_pstate_init);
3503
intel_pstate_setup(char * str)3504 static int __init intel_pstate_setup(char *str)
3505 {
3506 if (!str)
3507 return -EINVAL;
3508
3509 if (!strcmp(str, "disable"))
3510 no_load = 1;
3511 else if (!strcmp(str, "active"))
3512 default_driver = &intel_pstate;
3513 else if (!strcmp(str, "passive"))
3514 default_driver = &intel_cpufreq;
3515
3516 if (!strcmp(str, "no_hwp"))
3517 no_hwp = 1;
3518
3519 if (!strcmp(str, "force"))
3520 force_load = 1;
3521 if (!strcmp(str, "hwp_only"))
3522 hwp_only = 1;
3523 if (!strcmp(str, "per_cpu_perf_limits"))
3524 per_cpu_limits = true;
3525
3526 #ifdef CONFIG_ACPI
3527 if (!strcmp(str, "support_acpi_ppc"))
3528 acpi_ppc = true;
3529 #endif
3530
3531 return 0;
3532 }
3533 early_param("intel_pstate", intel_pstate_setup);
3534
3535 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3536 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3537 MODULE_LICENSE("GPL");
3538