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Searched refs:t10 (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/i915/display/
Dintel_pps.c1128 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); in intel_pps_readout_hw_state()
1149 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); in intel_pps_dump_state()
1162 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { in intel_pps_verify_state()
1172 delays->t10 || delays->t11_t12; in pps_delays_valid()
1234 spec->t10 = 500 * 10; in pps_init_delays_spec()
1268 assign_final(t10); in pps_init_delays()
1276 intel_dp->pps.panel_power_down_delay = get_delay(t10); in pps_init_delays()
1350 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); in pps_init_registers()
Dintel_bios.h56 u16 t10; member
/drivers/infiniband/ulp/srp/
DKconfig12 committee. See <http://www.t10.org/>.
/drivers/infiniband/ulp/srpt/
DKconfig13 of the INCITS T10 technical committee (http://www.t10.org/).
/drivers/gpu/drm/gma500/
Dintel_bios.h448 u16 t10; member
Dcdv_intel_dp.c2042 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> in cdv_intel_dp_init()
2049 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); in cdv_intel_dp_init()
2055 intel_dp->panel_power_down_delay = cur.t10 / 10; in cdv_intel_dp_init()
Dintel_bios.c85 dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, in parse_edp()
/drivers/gpu/drm/qxl/
Dqxl_dev.h641 uint32_t t10; member