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Searched refs:tc_cfg (Results 1 – 14 of 14) sorted by relevance

/drivers/net/ethernet/qlogic/qlcnic/
Dqlcnic_dcb.c155 struct qlcnic_dcb_tc_cfg tc_cfg[QLC_DCB_MAX_TC]; member
659 struct qlcnic_dcb_tc_cfg *tc_cfg; in qlcnic_dcb_fill_cee_tc_params() local
664 tc_cfg = &type->tc_cfg[tc]; in qlcnic_dcb_fill_cee_tc_params()
665 tc_cfg->valid = true; in qlcnic_dcb_fill_cee_tc_params()
666 tc_cfg->up_tc_map |= QLC_DCB_GET_MAP(i); in qlcnic_dcb_fill_cee_tc_params()
670 tc_cfg->prio_cfg[i].valid = true; in qlcnic_dcb_fill_cee_tc_params()
671 tc_cfg->prio_cfg[i].pfc_type = QLC_PFC_FULL; in qlcnic_dcb_fill_cee_tc_params()
679 tc_cfg->pgid = pgid; in qlcnic_dcb_fill_cee_tc_params()
681 tc_cfg->prio_type = QLC_PRIO_LINK; in qlcnic_dcb_fill_cee_tc_params()
682 type->pg_cfg[tc_cfg->pgid].prio_count++; in qlcnic_dcb_fill_cee_tc_params()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_encoder_phys_cmd.c325 struct dpu_hw_tear_check tc_cfg = { 0 }; in dpu_encoder_phys_cmd_tearcheck_config() local
363 tc_cfg.vsync_count = vsync_hz / in dpu_encoder_phys_cmd_tearcheck_config()
370 tc_cfg.hw_vsync_mode = 1; in dpu_encoder_phys_cmd_tearcheck_config()
371 tc_cfg.sync_cfg_height = mode->vtotal * 2; in dpu_encoder_phys_cmd_tearcheck_config()
372 tc_cfg.vsync_init_val = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()
373 tc_cfg.sync_threshold_start = DEFAULT_TEARCHECK_SYNC_THRESH_START; in dpu_encoder_phys_cmd_tearcheck_config()
374 tc_cfg.sync_threshold_continue = DEFAULT_TEARCHECK_SYNC_THRESH_CONTINUE; in dpu_encoder_phys_cmd_tearcheck_config()
375 tc_cfg.start_pos = mode->vdisplay; in dpu_encoder_phys_cmd_tearcheck_config()
376 tc_cfg.rd_ptr_irq = mode->vdisplay + 1; in dpu_encoder_phys_cmd_tearcheck_config()
384 phys_enc->hw_pp->idx - PINGPONG_0, tc_enable, tc_cfg.start_pos, in dpu_encoder_phys_cmd_tearcheck_config()
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/drivers/net/ethernet/intel/ice/
Dice_lib.c925 if (!vsi->tc_cfg.numtc) { in ice_vsi_setup_q_map()
927 vsi->tc_cfg.numtc = 1; in ice_vsi_setup_q_map()
928 vsi->tc_cfg.ena_tc = 1; in ice_vsi_setup_q_map()
931 num_rxq_per_tc = min_t(u16, qcount_rx / vsi->tc_cfg.numtc, ICE_MAX_RXQS_PER_TC); in ice_vsi_setup_q_map()
934 num_txq_per_tc = qcount_tx / vsi->tc_cfg.numtc; in ice_vsi_setup_q_map()
953 if (!(vsi->tc_cfg.ena_tc & BIT(i))) { in ice_vsi_setup_q_map()
955 vsi->tc_cfg.tc_info[i].qoffset = 0; in ice_vsi_setup_q_map()
956 vsi->tc_cfg.tc_info[i].qcount_rx = 1; in ice_vsi_setup_q_map()
957 vsi->tc_cfg.tc_info[i].qcount_tx = 1; in ice_vsi_setup_q_map()
958 vsi->tc_cfg.tc_info[i].netdev_tc = 0; in ice_vsi_setup_q_map()
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Dice_dcb_lib.c42 if (vsi->tc_cfg.ena_tc & BIT(i)) in ice_is_pfc_causing_hung_q()
47 if (ice_find_q_in_range(vsi->tc_cfg.tc_info[tc].qoffset, in ice_is_pfc_causing_hung_q()
48 vsi->tc_cfg.tc_info[tc + 1].qoffset, in ice_is_pfc_causing_hung_q()
185 vsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg); in ice_vsi_set_dcb_tc_cfg()
186 vsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg); in ice_vsi_set_dcb_tc_cfg()
189 vsi->tc_cfg.ena_tc = BIT(ice_get_first_droptc(vsi)); in ice_vsi_set_dcb_tc_cfg()
190 vsi->tc_cfg.numtc = 1; in ice_vsi_set_dcb_tc_cfg()
195 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; in ice_vsi_set_dcb_tc_cfg()
196 vsi->tc_cfg.numtc = 1; in ice_vsi_set_dcb_tc_cfg()
235 if (!(vsi->tc_cfg.ena_tc & BIT(n))) in ice_vsi_cfg_dcb_rings()
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Dice_dcb_lib.h71 vsi->tc_cfg.ena_tc = ICE_DFLT_TRAFFIC_CLASS; in ice_vsi_set_dcb_tc_cfg()
72 vsi->tc_cfg.numtc = 1; in ice_vsi_set_dcb_tc_cfg()
Dice.h388 struct ice_tc_cfg tc_cfg; member
850 if (vsi->tc_cfg.numtc > ICE_CHNL_START_TC && in ice_is_adq_active()
Dice_idc.c88 status = ice_cfg_vsi_rdma(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc, in ice_add_rdma_qset()
Dice_base.c223 return ring->q_index - vsi->tc_cfg.tc_info[tc].qoffset; in ice_calc_txq_handle()
Dice_vf_lib.c1035 vsi->idx, vsi->tc_cfg.ena_tc); in ice_vf_rebuild_aggregator_node_cfg()
Dice_ethtool.c3520 if (new_rx < vsi->tc_cfg.numtc) { in ice_set_channels()
3522 vsi->tc_cfg.numtc); in ice_set_channels()
3525 if (new_tx < vsi->tc_cfg.numtc) { in ice_set_channels()
3527 vsi->tc_cfg.numtc); in ice_set_channels()
Dice_main.c2730 for (i = 0; i < vsi->tc_cfg.numtc; i++) in ice_prepare_xdp_rings()
2733 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc, in ice_prepare_xdp_rings()
2838 for (i = 0; i < vsi->tc_cfg.numtc; i++) in ice_destroy_xdp_rings()
2844 return ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc, in ice_destroy_xdp_rings()
3497 ice_vsi_cfg_netdev_tc(vsi, vsi->tc_cfg.ena_tc); in ice_cfg_netdev()
7007 ice_vsi_cfg_netdev_tc(vsi, vsi->tc_cfg.ena_tc); in ice_vsi_open()
8673 if (ena_tc_qdisc == vsi->tc_cfg.ena_tc && in ice_setup_tc_mqprio_qdisc()
Dice_dcb_nl.c1020 if (tc_map & vsi->tc_cfg.ena_tc) { in ice_dcbnl_set_all()
/drivers/counter/
Dmicrochip-tcb-capture.c26 const struct atmel_tcb_config *tc_cfg; member
101 if (!priv->tc_cfg->has_gclk) in mchp_tc_count_function_write()
110 if (!priv->tc_cfg->has_qdec) in mchp_tc_count_function_write()
372 priv->tc_cfg = tcb_config; in mchp_tc_probe()
/drivers/net/ethernet/hisilicon/hns/
Dhns_dsaf_main.c1275 u32 tc_cfg; in hns_dsaf_inode_init() local
1279 tc_cfg = HNS_DSAF_I4TC_CFG; in hns_dsaf_inode_init()
1281 tc_cfg = HNS_DSAF_I8TC_CFG; in hns_dsaf_inode_init()
1316 dsaf_write_dev(dsaf_dev, reg, tc_cfg); in hns_dsaf_inode_init()