Home
last modified time | relevance | path

Searched refs:ti_clk_get_reg_addr (Results 1 – 9 of 9) sorted by relevance

/drivers/clk/ti/
Ddpll.c254 } else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) { in _register_dpll_x2()
318 if (ti_clk_get_reg_addr(node, 0, &dd->control_reg)) in of_ti_dpll_setup()
327 if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg)) in of_ti_dpll_setup()
334 if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg)) in of_ti_dpll_setup()
337 if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg)) in of_ti_dpll_setup()
342 if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg)) in of_ti_dpll_setup()
352 if (ti_clk_get_reg_addr(node, ssc_clk_index++, in of_ti_dpll_setup()
356 if (ti_clk_get_reg_addr(node, ssc_clk_index++, in of_ti_dpll_setup()
Dapll.c212 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_dra7_apll_setup()
213 ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg); in of_dra7_apll_setup()
395 ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg); in of_omap2_apll_setup()
396 ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg); in of_omap2_apll_setup()
397 ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg); in of_omap2_apll_setup()
Dgate.c140 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_gate_clk_setup()
179 if (ti_clk_get_reg_addr(node, 0, &gate->enable_reg)) in _of_ti_composite_gate_clk_setup()
Dmux.c189 if (ti_clk_get_reg_addr(node, 0, &reg)) in of_mux_clk_setup()
261 if (ti_clk_get_reg_addr(node, 0, &mux->reg)) in of_ti_composite_mux_clk_setup()
Dinterface.c71 if (ti_clk_get_reg_addr(node, 0, &reg)) in _of_ti_interface_clk_setup()
Dautoidle.c201 ret = ti_clk_get_reg_addr(node, 0, &clk->reg); in of_ti_clk_autoidle_setup()
Dclock.h217 int ti_clk_get_reg_addr(struct device_node *node, int index,
Dclk.c301 int ti_clk_get_reg_addr(struct device_node *node, int index, in ti_clk_get_reg_addr() function
Ddivider.c476 ret = ti_clk_get_reg_addr(node, 0, &div->reg); in ti_clk_divider_populate()