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Searched refs:ti_clk_ll_ops (Results 1 – 14 of 14) sorted by relevance

/drivers/clk/ti/
Dclkt_dflt.c60 if ((ti_clk_ll_ops->clk_readl(reg) & mask) == ena) in _wait_idlest_generic()
95 if (!(ti_clk_ll_ops->clk_readl(&companion_reg) & in _omap2_module_wait_ready()
101 r = ti_clk_ll_ops->cm_split_idlest_reg(&idlest_reg, &prcm_mod, in _omap2_module_wait_ready()
108 ti_clk_ll_ops->cm_wait_module_ready(0, prcm_mod, idlest_reg_id, in _omap2_module_wait_ready()
209 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_dflt_clk_enable()
220 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_enable()
225 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); in omap2_dflt_clk_enable()
226 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); /* OCP barrier */ in omap2_dflt_clk_enable()
250 v = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in omap2_dflt_clk_disable()
255 ti_clk_ll_ops->clk_writel(v, &clk->enable_reg); in omap2_dflt_clk_disable()
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Ddpll3xxx.c54 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in _omap3_dpll_write_clken()
57 ti_clk_ll_ops->clk_writel(v, &dd->control_reg); in _omap3_dpll_write_clken()
73 while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) in _omap3_wait_dpll_status()
151 if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) == in _omap3_noncore_dpll_lock()
308 ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap3_noncore_dpll_ssc_program()
334 v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg); in omap3_noncore_dpll_ssc_program()
338 ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg); in omap3_noncore_dpll_ssc_program()
364 v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program()
368 ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg); in omap3_noncore_dpll_ssc_program()
373 ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg); in omap3_noncore_dpll_ssc_program()
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Dapll.c50 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
55 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_enable()
58 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_enable()
63 v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg); in dra7_apll_enable()
94 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_disable()
97 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in dra7_apll_disable()
108 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in dra7_apll_is_enabled()
241 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_is_enabled()
267 v = ti_clk_ll_ops->clk_readl(&ad->control_reg); in omap2_apll_enable()
270 ti_clk_ll_ops->clk_writel(v, &ad->control_reg); in omap2_apll_enable()
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Ddpll44xx.c49 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
52 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_allow_gatectrl()
67 v = ti_clk_ll_ops->clk_readl(&clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
70 ti_clk_ll_ops->clk_writel(v, &clk->clksel_reg); in omap4_dpllmx_deny_gatectrl()
129 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap4_dpll_regm4xen_recalc()
Dclkt_iclk.c36 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_allow_idle()
38 ti_clk_ll_ops->clk_writel(v, &r); in omap2_clkt_iclk_allow_idle()
51 v = ti_clk_ll_ops->clk_readl(&r); in omap2_clkt_iclk_deny_idle()
53 ti_clk_ll_ops->clk_writel(v, &r); in omap2_clkt_iclk_deny_idle()
Dclk.c28 struct ti_clk_ll_ops *ti_clk_ll_ops; variable
99 int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops) in ti_clk_setup_ll_ops()
101 if (ti_clk_ll_ops) { in ti_clk_setup_ll_ops()
106 ti_clk_ll_ops = ops; in ti_clk_setup_ll_ops()
345 ti_clk_ll_ops->clk_rmw(latch, latch, reg); in ti_clk_latch()
346 ti_clk_ll_ops->clk_rmw(0, latch, reg); in ti_clk_latch()
347 ti_clk_ll_ops->clk_readl(reg); /* OCP barrier */ in ti_clk_latch()
Dclkctrl.c137 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_enable()
150 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_enable()
155 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_enable()
161 while (!_omap4_is_ready(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_enable()
180 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_disable()
184 ti_clk_ll_ops->clk_writel(val, &clk->enable_reg); in _omap4_clkctrl_clk_disable()
190 while (!_omap4_is_idle(ti_clk_ll_ops->clk_readl(&clk->enable_reg))) { in _omap4_clkctrl_clk_disable()
200 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in _omap4_clkctrl_clk_disable()
208 val = ti_clk_ll_ops->clk_readl(&clk->enable_reg); in _omap4_clkctrl_clk_is_enabled()
742 val = ti_clk_ll_ops->clk_readl(&hwclk->enable_reg); in ti_clk_is_in_standby()
Dautoidle.c121 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _allow_autoidle()
128 ti_clk_ll_ops->clk_writel(val, &clk->reg); in _allow_autoidle()
135 val = ti_clk_ll_ops->clk_readl(&clk->reg); in _deny_autoidle()
142 ti_clk_ll_ops->clk_writel(val, &clk->reg); in _deny_autoidle()
Dclockdomain.c53 ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk); in omap2_clkops_enable_clkdm()
87 ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk); in omap2_clkops_disable_clkdm()
109 clkdm = ti_clk_ll_ops->clkdm_lookup(clk->clkdm_name); in omap2_init_clk_clkdm()
Ddivider.c99 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in ti_clk_divider_recalc_rate()
256 val = ti_clk_ll_ops->clk_readl(&divider->reg); in ti_clk_divider_set_rate()
259 ti_clk_ll_ops->clk_writel(val, &divider->reg); in ti_clk_divider_set_rate()
277 val = ti_clk_ll_ops->clk_readl(&divider->reg) >> divider->shift; in clk_divider_save_context()
294 val = ti_clk_ll_ops->clk_readl(&divider->reg); in clk_divider_restore_context()
297 ti_clk_ll_ops->clk_writel(val, &divider->reg); in clk_divider_restore_context()
Dgate.c74 orig_v = ti_clk_ll_ops->clk_readl(&parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
79 ti_clk_ll_ops->clk_writel(dummy_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
82 ti_clk_ll_ops->clk_writel(orig_v, &parent->reg); in omap36xx_gate_clk_enable_with_hsdiv_restore()
Dclkt_dpll.c213 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_init_dpll_parent()
249 v = ti_clk_ll_ops->clk_readl(&dd->control_reg); in omap2_get_dpll_rate()
256 v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); in omap2_get_dpll_rate()
Dmux.c34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent()
76 val = ti_clk_ll_ops->clk_readl(&mux->reg); in ti_clk_mux_set_parent()
80 ti_clk_ll_ops->clk_writel(val, &mux->reg); in ti_clk_mux_set_parent()
Dclock.h305 extern struct ti_clk_ll_ops *ti_clk_ll_ops;