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Searched refs:tx_mask (Results 1 – 17 of 17) sorted by relevance

/drivers/net/wireless/marvell/mwifiex/
Dpcie.h127 u32 tx_mask; member
245 if (((card->txbd_wrptr & reg->tx_mask) == in mwifiex_pcie_txbd_empty()
246 (rdptr & reg->tx_mask)) && in mwifiex_pcie_txbd_empty()
253 if (((card->txbd_wrptr & reg->tx_mask) == in mwifiex_pcie_txbd_empty()
254 (rdptr & reg->tx_mask)) && in mwifiex_pcie_txbd_empty()
271 if (((card->txbd_wrptr & reg->tx_mask) != in mwifiex_pcie_txbd_not_full()
272 (card->txbd_rdptr & reg->tx_mask)) || in mwifiex_pcie_txbd_not_full()
279 if (((card->txbd_wrptr & reg->tx_mask) != in mwifiex_pcie_txbd_not_full()
280 (card->txbd_rdptr & reg->tx_mask)) || in mwifiex_pcie_txbd_not_full()
Dpcie.c41 .tx_mask = MWIFIEX_TXBD_MASK,
73 .tx_mask = 0x03FF0000,
110 .tx_mask = 0x0FFF0000,
1353 while (((card->txbd_rdptr & reg->tx_mask) != in mwifiex_pcie_send_data_complete()
1354 (rdptr & reg->tx_mask)) || in mwifiex_pcie_send_data_complete()
1357 wrdoneidx = (card->txbd_rdptr & reg->tx_mask) >> in mwifiex_pcie_send_data_complete()
1399 if ((card->txbd_rdptr & reg->tx_mask) == num_tx_buffs) in mwifiex_pcie_send_data_complete()
1463 wrindx = (card->txbd_wrptr & reg->tx_mask) >> reg->tx_start_ptr; in mwifiex_pcie_send_data()
1494 if ((card->txbd_wrptr & reg->tx_mask) == num_tx_buffs) in mwifiex_pcie_send_data()
/drivers/net/wireless/mediatek/mt76/mt7615/
Deeprom.c142 u8 tx_mask, max_nss; in mt7615_eeprom_parse_hw_cap() local
148 tx_mask = FIELD_GET(MT_EE_HW_CONF1_TX_MASK, in mt7615_eeprom_parse_hw_cap()
157 tx_mask = FIELD_GET(MT_EE_NIC_CONF_TX_MASK, in mt7615_eeprom_parse_hw_cap()
160 if (!tx_mask || tx_mask > max_nss) in mt7615_eeprom_parse_hw_cap()
161 tx_mask = max_nss; in mt7615_eeprom_parse_hw_cap()
163 dev->chainmask = BIT(tx_mask) - 1; in mt7615_eeprom_parse_hw_cap()
/drivers/media/rc/
Dene_ir.c859 static int ene_set_tx_mask(struct rc_dev *rdev, u32 tx_mask) in ene_set_tx_mask() argument
862 dbg("TX: attempt to set transmitter mask %02x", tx_mask); in ene_set_tx_mask()
865 if (!tx_mask || tx_mask & ~0x03) { in ene_set_tx_mask()
871 dev->transmitter_mask = tx_mask; in ene_set_tx_mask()
Dmceusb.c495 unsigned char tx_mask; member
942 cmdbuf[2] = ir->tx_mask; in mceusb_tx_ir()
1023 ir->tx_mask = mask; in mceusb_set_tx_mask()
1025 ir->tx_mask = (mask != MCE_DEFAULT_TX_MASK ? in mceusb_set_tx_mask()
1242 ir->tx_mask = *hi; in mceusb_handle_command()
/drivers/usb/serial/
Dxr_serial.c562 u16 tx_mask, rx_mask; in xr21v141x_set_baudrate() local
572 tx_mask = xr21v141x_txrx_clk_masks[idx].tx; in xr21v141x_set_baudrate()
601 tx_mask & 0xff); in xr21v141x_set_baudrate()
606 (tx_mask >> 8) & 0xff); in xr21v141x_set_baudrate()
/drivers/net/can/flexcan/
Dflexcan.h97 u64 tx_mask; member
Dflexcan-core.c924 return flexcan_read64_mask(priv, &priv->regs->iflag1, priv->tx_mask); in flexcan_read_reg_iflag_tx()
1075 if (reg_iflag_tx & priv->tx_mask) { in flexcan_irq()
1087 flexcan_write64(priv, priv->tx_mask, &regs->iflag1); in flexcan_irq()
1365 priv->tx_mask = FLEXCAN_IFLAG_MB(priv->tx_mb_idx); in flexcan_rx_offload_setup()
1394 reg_imask = priv->rx_mask | priv->tx_mask; in flexcan_chip_interrupts_enable()
/drivers/net/wireless/ath/carl9170/
Deeprom.h137 u8 tx_mask; member
Dmac.c505 if (ar->eeprom.tx_mask != 1) in carl9170_set_mac_tpc()
Dphy.c1651 if (ar->eeprom.tx_mask != 1) in carl9170_set_channel()
Dtx.c752 if (ar->eeprom.tx_mask == 1) { in carl9170_tx_rate_tpc_chains()
Dmain.c1889 tx_streams = hweight8(ar->eeprom.tx_mask); in carl9170_parse_eeprom()
/drivers/tty/
Dmoxa.c2171 u16 head, tail, tx_mask, spage, epage; in MoxaPortWriteData() local
2176 tx_mask = readw(ofsAddr + TX_mask); in MoxaPortWriteData()
2181 c = (head > tail) ? (head - tail - 1) : (head - tail + tx_mask); in MoxaPortWriteData()
2193 len = tx_mask + 1 - tail; in MoxaPortWriteData()
2198 tail = (tail + len) & tx_mask; in MoxaPortWriteData()
2217 tail = (tail + total) & tx_mask; in MoxaPortWriteData()
/drivers/atm/
Dsolos-pci.c109 int tx_mask; member
1040 card->tx_mask |= (1 << port); in fpga_queue()
1068 tx_pending = card->tx_mask & ~card_flags; in fpga_tx()
1081 card->tx_mask &= ~(1 << port); in fpga_tx()
/drivers/net/ipa/
Dipa_endpoint.c1848 u32 tx_mask; in ipa_endpoint_config() local
1886 tx_mask = GENMASK(max - 1, 0); in ipa_endpoint_config()
1888 ipa->available = rx_mask | tx_mask; in ipa_endpoint_config()
/drivers/net/ethernet/freescale/
Dgianfar.c237 unsigned long tx_mask, unsigned long rx_mask) in gfar_configure_coalescing() argument
246 for_each_set_bit(i, &tx_mask, priv->num_tx_queues) { in gfar_configure_coalescing()