Searched refs:uclk (Results 1 – 19 of 19) sorted by relevance
37 struct clk *uclk; member54 clk_prepare_enable(atmel_ehci->uclk); in atmel_start_clock()65 clk_disable_unprepare(atmel_ehci->uclk); in atmel_stop_clock()142 atmel_ehci->uclk = devm_clk_get(&pdev->dev, "usb_clk"); in ehci_atmel_drv_probe()143 if (IS_ERR(atmel_ehci->uclk)) { in ehci_atmel_drv_probe()145 retval = PTR_ERR(atmel_ehci->uclk); in ehci_atmel_drv_probe()
148 struct clk *uclk; member1277 hsudc->uclk = devm_clk_get(&pdev->dev, "usb-device"); in s3c_hsudc_probe()1278 if (IS_ERR(hsudc->uclk)) { in s3c_hsudc_probe()1280 ret = PTR_ERR(hsudc->uclk); in s3c_hsudc_probe()1283 clk_enable(hsudc->uclk); in s3c_hsudc_probe()1298 clk_disable(hsudc->uclk); in s3c_hsudc_probe()
342 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()359 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v12_0_get_vbios_bootup_values()
293 clock_limit = smu->smu_table.boot_values.uclk; in renoir_get_dpm_ultimate_freq()
640 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()654 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()669 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz; in smu_v13_0_get_vbios_bootup_values()928 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_init_max_sustainable_clocks()1598 clock_limit = smu->smu_table.boot_values.uclk; in smu_v13_0_get_dpm_ultimate_freq()
732 clock_limit = smu->smu_table.boot_values.uclk; in smu_v13_0_5_get_dpm_ultimate_freq()
733 clock_limit = smu->smu_table.boot_values.uclk; in smu_v13_0_4_get_dpm_ultimate_freq()
858 clock_limit = smu->smu_table.boot_values.uclk; in yellow_carp_get_dpm_ultimate_freq()
606 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_7_set_default_dpm_table()
586 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in smu_v13_0_0_set_default_dpm_table()
362 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in aldebaran_set_default_dpm_table()
581 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()598 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz; in smu_v11_0_get_vbios_bootup_values()862 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100; in smu_v11_0_init_max_sustainable_clocks()1724 clock_limit = smu->smu_table.boot_values.uclk; in smu_v11_0_get_dpm_ultimate_freq()
931 clock_limit = smu->smu_table.boot_values.uclk; in vangogh_get_dpm_ultimate_freq()
382 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in arcturus_set_default_dpm_table()
1017 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in navi10_set_default_dpm_table()
991 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100; in sienna_cichlid_set_default_dpm_table()
357 unsigned int uclk; member
586 VPD_ENTRY(uclk, 6); /* uP clk */671 ret = vpdstrtouint(vpd.uclk_data, vpd.uclk_len, 10, &p->uclk); in get_vpd_params()3364 t3_write_reg(adapter, A_CIM_HOST_ACC_DATA, vpd->uclk | fw_params); in t3_init_hw()
289 uint32_t uclk; member