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Searched refs:v3 (Results 1 – 25 of 57) sorted by relevance

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/drivers/pci/controller/
Dpci-v3-semi.c315 struct v3_pci *v3 = bus->sysdata; in v3_map_bus() local
367 writel(v3_addr_to_lb_base(v3->non_pre_mem) | in v3_map_bus()
369 v3->base + V3_LB_BASE0); in v3_map_bus()
375 writel(v3_addr_to_lb_base(v3->config_mem) | in v3_map_bus()
377 v3->base + V3_LB_BASE1); in v3_map_bus()
378 writew(mapaddress, v3->base + V3_LB_MAP1); in v3_map_bus()
380 return v3->config_base + address + offset; in v3_map_bus()
383 static void v3_unmap_bus(struct v3_pci *v3) in v3_unmap_bus() argument
388 writel(v3_addr_to_lb_base(v3->pre_mem) | in v3_unmap_bus()
391 v3->base + V3_LB_BASE1); in v3_unmap_bus()
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/drivers/char/mwave/
Dmwavedd.h89 #define PRINTK_4(f,s,v1,v2,v3) \ argument
91 printk(s,v1,v2,v3); \
94 #define PRINTK_5(f,s,v1,v2,v3,v4) \ argument
96 printk(s,v1,v2,v3,v4); \
99 #define PRINTK_6(f,s,v1,v2,v3,v4,v5) \ argument
101 printk(s,v1,v2,v3,v4,v5); \
104 #define PRINTK_7(f,s,v1,v2,v3,v4,v5,v6) \ argument
106 printk(s,v1,v2,v3,v4,v5,v6); \
109 #define PRINTK_8(f,s,v1,v2,v3,v4,v5,v6,v7) \ argument
111 printk(s,v1,v2,v3,v4,v5,v6,v7); \
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/drivers/gpu/drm/amd/display/dc/inc/
Dreg_helper.h72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
76 FN(reg, f3), v3)
78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
82 FN(reg, f3), v3,\
85 #define REG_SET_5(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
90 FN(reg, f3), v3,\
94 #define REG_SET_6(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
99 FN(reg, f3), v3,\
104 #define REG_SET_7(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4, \ argument
109 FN(reg, f3), v3,\
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Dbw_fixed.h56 struct bw_fixed v3) in bw_min3() argument
58 return bw_min2(bw_min2(v1, v2), v3); in bw_min3()
63 struct bw_fixed v3) in bw_max3() argument
65 return bw_max2(bw_max2(v1, v2), v3); in bw_max3()
Ddcn_calc_math.h37 float dcn_bw_max3(float v1, float v2, float v3);
38 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5);
/drivers/gpu/drm/amd/amdgpu/
Datombios_crtc.c238 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; member
278 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); in amdgpu_atombios_crtc_program_ss()
279 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in amdgpu_atombios_crtc_program_ss()
282 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; in amdgpu_atombios_crtc_program_ss()
285 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; in amdgpu_atombios_crtc_program_ss()
288 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; in amdgpu_atombios_crtc_program_ss()
293 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in amdgpu_atombios_crtc_program_ss()
294 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in amdgpu_atombios_crtc_program_ss()
295 args.v3.ucEnable = enable; in amdgpu_atombios_crtc_program_ss()
302 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; member
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Datombios_encoders.c555 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
602 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
634 args.v3.ucAction = action; in amdgpu_atombios_encoder_setup_dig_encoder()
635 args.v3.usPixelClock = cpu_to_le16(amdgpu_encoder->pixel_clock / 10); in amdgpu_atombios_encoder_setup_dig_encoder()
637 args.v3.ucPanelMode = panel_mode; in amdgpu_atombios_encoder_setup_dig_encoder()
639 args.v3.ucEncoderMode = amdgpu_atombios_encoder_get_encoder_mode(encoder); in amdgpu_atombios_encoder_setup_dig_encoder()
641 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) in amdgpu_atombios_encoder_setup_dig_encoder()
642 args.v3.ucLaneNum = dp_lane_count; in amdgpu_atombios_encoder_setup_dig_encoder()
644 args.v3.ucLaneNum = 8; in amdgpu_atombios_encoder_setup_dig_encoder()
646 args.v3.ucLaneNum = 4; in amdgpu_atombios_encoder_setup_dig_encoder()
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Damdgpu_atombios.c877 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; member
955 if ((ss_assign->v3.ucClockIndication == id) && in amdgpu_atombios_get_asic_ss_info()
956 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { in amdgpu_atombios_get_asic_ss_info()
958 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); in amdgpu_atombios_get_asic_ss_info()
959 ss->type = ss_assign->v3.ucSpreadSpectrumMode; in amdgpu_atombios_get_asic_ss_info()
960 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); in amdgpu_atombios_get_asic_ss_info()
961 if (ss_assign->v3.ucSpreadSpectrumMode & in amdgpu_atombios_get_asic_ss_info()
989 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; member
1019 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in amdgpu_atombios_get_clock_dividers()
1023 dividers->post_div = args.v3.ucPostDiv; in amdgpu_atombios_get_clock_dividers()
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/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.h70 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument
74 FN(reg, f3), v3)
76 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
80 FN(reg, f3), v3, \
97 #define REG_UPDATE_3(reg, f1, v1, f2, v2, f3, v3) \ argument
101 FN(reg, f3), v3)
103 #define REG_UPDATE_4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \ argument
107 FN(reg, f3), v3, \
/drivers/gpu/drm/amd/display/dc/dml/calcs/
Ddcn_calc_math.c94 float dcn_bw_max3(float v1, float v2, float v3) in dcn_bw_max3() argument
96 return v3 > dcn_bw_max2(v1, v2) ? v3 : dcn_bw_max2(v1, v2); in dcn_bw_max3()
99 float dcn_bw_max5(float v1, float v2, float v3, float v4, float v5) in dcn_bw_max5() argument
101 …return dcn_bw_max3(v1, v2, v3) > dcn_bw_max2(v4, v5) ? dcn_bw_max3(v1, v2, v3) : dcn_bw_max2(v4, v… in dcn_bw_max5()
/drivers/clocksource/
Dacpi_pm.c42 u32 v1 = 0, v2 = 0, v3 = 0; in acpi_pm_read_verified() local
53 v3 = read_pmtmr(); in acpi_pm_read_verified()
54 } while (unlikely((v1 > v2 && v1 < v3) || (v2 > v3 && v2 < v1) in acpi_pm_read_verified()
55 || (v3 > v1 && v3 < v2))); in acpi_pm_read_verified()
/drivers/gpu/drm/radeon/
Datombios_encoders.c824 DIG_ENCODER_CONTROL_PARAMETERS_V3 v3; member
878 args.v3.ucPanelMode = panel_mode; in atombios_dig_encoder_setup2()
912 args.v3.ucAction = action; in atombios_dig_encoder_setup2()
913 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10); in atombios_dig_encoder_setup2()
915 args.v3.ucPanelMode = panel_mode; in atombios_dig_encoder_setup2()
917 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder); in atombios_dig_encoder_setup2()
919 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode)) in atombios_dig_encoder_setup2()
920 args.v3.ucLaneNum = dp_lane_count; in atombios_dig_encoder_setup2()
922 args.v3.ucLaneNum = 8; in atombios_dig_encoder_setup2()
924 args.v3.ucLaneNum = 4; in atombios_dig_encoder_setup2()
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Datombios_crtc.c441 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3; member
482 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0); in atombios_crtc_program_ss()
483 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK; in atombios_crtc_program_ss()
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL; in atombios_crtc_program_ss()
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL; in atombios_crtc_program_ss()
492 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL; in atombios_crtc_program_ss()
497 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount); in atombios_crtc_program_ss()
498 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step); in atombios_crtc_program_ss()
499 args.v3.ucEnable = enable; in atombios_crtc_program_ss()
555 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3; member
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Dradeon_atombios.c1497 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; member
1575 if ((ss_assign->v3.ucClockIndication == id) && in radeon_atombios_get_asic_ss_info()
1576 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { in radeon_atombios_get_asic_ss_info()
1578 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); in radeon_atombios_get_asic_ss_info()
1579 ss->type = ss_assign->v3.ucSpreadSpectrumMode; in radeon_atombios_get_asic_ss_info()
1580 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); in radeon_atombios_get_asic_ss_info()
1581 if (ss_assign->v3.ucSpreadSpectrumMode & in radeon_atombios_get_asic_ss_info()
2822 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; member
2878 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); in radeon_atom_get_clock_dividers()
2882 dividers->post_div = args.v3.ucPostDiv; in radeon_atom_get_clock_dividers()
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/drivers/gpu/ipu-v3/
DMakefile2 obj-$(CONFIG_IMX_IPUV3_CORE) += imx-ipu-v3.o
4 imx-ipu-v3-objs := ipu-common.o ipu-cpmem.o ipu-csi.o ipu-dc.o ipu-di.o \
9 imx-ipu-v3-objs += ipu-pre.o ipu-prg.o
/drivers/gpu/drm/amd/amdkfd/
Dcwsr_trap_handler_gfx8.asm355 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
396 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid
397 v_mul_i32_i24 v2, v3, 8 // tid*8
398 v_mov_b32 v3, 256*2
409 v_add_u32 v2, vcc[0:1], v2, v3
448 v_mov_b32 v3, v3 //v0 = v[0+m0]
453 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
550 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
555 v_mov_b32 v3, v3
565 …buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:256…
Dcwsr_trap_handler_gfx10.asm457 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
470 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
708 v_movrels_b32 v3, v3 //v3 = v[3+m0]
713 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:128*3
734 v_movrels_b32 v3, v3 //v3 = v[3+m0]
739 buffer_store_dword v3, v0, s_save_buf_rsrc0, s_save_mem_offset slc:1 glc:1 offset:256*3
880 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:128*3
885 v_movreld_b32 v3, v3
895 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset_save slc:1 glc:1 offset:128*3
914 buffer_load_dword v3, v0, s_restore_buf_rsrc0, s_restore_mem_offset slc:1 glc:1 offset:256*3
[all …]
Dcwsr_trap_handler_gfx9.asm527 v_mbcnt_hi_u32_b32 v3, 0xffffffff, v2 // tid
533 v_lshlrev_b32 v2, 2, v3
549 v_mul_i32_i24 v2, v3, 8 // tid*8
550 v_mov_b32 v3, 256*2
562 v_add_u32 v2, v2, v3
614 v_mov_b32 v3, v3 //v0 = v[0+m0]
755 v_mov_b32 v3, v3
960 buffer_store_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
967 buffer_load_dword v3, v0, s_rsrc, s_mem_offset slc:1 glc:1 offset:256*3
/drivers/iommu/arm/arm-smmu-v3/
DMakefile3 arm_smmu_v3-objs-y += arm-smmu-v3.o
4 arm_smmu_v3-objs-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
/drivers/irqchip/
DMakefile34 obj-$(CONFIG_ARM_GIC_V3) += irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
35 obj-$(CONFIG_ARM_GIC_V3_ITS) += irq-gic-v3-its.o irq-gic-v3-its-platform-msi.o irq-gic-v4.o
36 obj-$(CONFIG_ARM_GIC_V3_ITS_PCI) += irq-gic-v3-its-pci-msi.o
37 obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC) += irq-gic-v3-its-fsl-mc-msi.o
/drivers/staging/r8188eu/hal/
DHalHWImg8188E_BB.c711 u32 v3 = array[i + 2]; in ODM_ReadAndConfig_PHY_REG_PG_8188E() local
715 odm_ConfigBB_PHY_REG_PG_8188E(dm_odm, v1, v2, v3); in ODM_ReadAndConfig_PHY_REG_PG_8188E()
723 v3 = array[i + 2]; in ODM_ReadAndConfig_PHY_REG_PG_8188E()
728 v3 = array[i + 1]; in ODM_ReadAndConfig_PHY_REG_PG_8188E()
/drivers/net/wireless/realtek/rtl818x/
DKconfig17 Belkin F5D6020 v3
18 Belkin F5D6020 v3
78 (v1 = rt73usb; v3 is rt2070-based,
/drivers/media/platform/nxp/
DKconfig16 v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
/drivers/ufs/host/
Dufs-mediatek.h219 unsigned long v3; member
229 s.cmd, s.v1, s.v2, s.v3, s.v4, s.v5, s.v6, s.res); in _ufs_mtk_smc()
/drivers/iommu/arm/
DMakefile2 obj-y += arm-smmu/ arm-smmu-v3/

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