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Searched refs:vline (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/nouveau/nvkm/engine/disp/
Dnv04.c44 nv04_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline) in nv04_head_rgpos() argument
49 *vline = (data & 0x0000ffff); in nv04_head_rgpos()
Dhead.h39 void (*rgpos)(struct nvkm_head *, u16 *hline, u16 *vline);
Dhead.c72 head->func->rgpos(head, &args->v0.hline, &args->v0.vline); in nvkm_head_mthd_scanoutpos()
Dgv100.c237 gv100_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline) in gv100_head_rgpos() argument
242 *vline = nvkm_rd32(device, 0x616330 + hoff) & 0x0000ffff; in gv100_head_rgpos()
Dnv50.c361 nv50_head_rgpos(struct nvkm_head *head, u16 *hline, u16 *vline) in nv50_head_rgpos() argument
367 *vline = nvkm_rd32(device, 0x616340 + hoff) & 0x0000ffff; in nv50_head_rgpos()
/drivers/gpu/drm/nouveau/include/nvif/
Dcl0046.h23 __u16 vline; member
Dcl5070.h22 __u16 vline; member
/drivers/gpu/drm/nouveau/
Dnouveau_display.c104 if (args.scan.vline) { in nouveau_display_scanoutpos_head()
114 args.scan.vtotal, args.scan.vline); in nouveau_display_scanoutpos_head()
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c87 uint32_t vline; member
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3074 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v8_0_crtc_irq()
Ddce_v6_0.c90 uint32_t vline; member
96 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
101 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
106 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
111 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
116 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
121 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
2981 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v6_0_crtc_irq()
Ddce_v10_0.c87 uint32_t vline; member
93 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
98 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
103 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
108 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
113 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
118 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3259 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v10_0_crtc_irq()
Ddce_v11_0.c89 uint32_t vline; member
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
3383 if (disp_int & interrupt_status_offsets[crtc].vline) in dce_v11_0_crtc_irq()