| /drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 31 unsigned int hsw, hfp, hbp, vsw, vfp, vbp; in adv7511_dsi_config_timing_gen() local
37 vsw = mode->vsync_end - mode->vsync_start; in adv7511_dsi_config_timing_gen()
58 regmap_write(adv->regmap_cec, 0x32, vsw >> 4); in adv7511_dsi_config_timing_gen()
59 regmap_write(adv->regmap_cec, 0x33, (vsw << 4) & 0xff); in adv7511_dsi_config_timing_gen()
|
| /drivers/video/fbdev/ |
| D | carminefb.c | 68 u32 vsw; member
111 .vsw = 2,
123 .vsw = 2,
372 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
385 vsw = par->res->vsw - 1; in set_display_parameters()
392 (vsw << CARMINE_DISP_VSW_SHIFT) | in set_display_parameters()
|
| /drivers/net/ethernet/sun/ |
| D | sunvnet_common.h | 67 unsigned vsw:1; member
130 ((__port)->vsw ? (__port)->dev : (__port)->vp->dev)
|
| /drivers/gpu/drm/tilcdc/ |
| D | tilcdc_crtc.c | 279 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_set_mode() local
320 vsw = mode->vsync_end - mode->vsync_start; in tilcdc_crtc_set_mode()
323 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_set_mode()
354 (((vsw-1) & 0x3f) << 10); in tilcdc_crtc_set_mode()
776 uint32_t hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_mode_valid() local
801 vsw = mode->vsync_end - mode->vsync_start; in tilcdc_crtc_mode_valid()
828 if ((vsw-1) & ~0x3f) { in tilcdc_crtc_mode_valid()
|
| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_wp.c | 177 timing_v |= FLD_VAL(timings->vsw, 7, 0); in hdmi_wp_video_config_timing()
197 timings->vsw = param->timings.vsw; in hdmi_wp_init_vid_fmt_timings()
|
| D | display.c | 272 ovt->vsw = vm->vsync_len; in videomode_to_omap_video_timings()
305 vm->vsync_len = ovt->vsw; in omap_video_timings_to_videomode()
|
| D | display-sysfs.c | 99 t.y_res, t.vfp, t.vbp, t.vsw); in display_timings_show()
124 &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9) in display_timings_store()
|
| D | hdmi5_core.c | 295 video_cfg->v_fc_config.timings.vsw = cfg->timings.vsw; in hdmi_core_init()
299 video_cfg->vblank = cfg->timings.vsw + in hdmi_core_init()
364 cfg->v_fc_config.timings.vsw, 5, 0); in hdmi_core_video_config()
|
| D | dispc.c | 2974 int vsw, int vfp, int vbp) in _dispc_lcd_timings_ok() argument
2979 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
3010 timings->hbp, timings->vsw, timings->vfp, in dispc_mgr_timings_ok()
3019 int hfp, int hbp, int vsw, int vfp, int vbp, in _dispc_mgr_set_lcd_timings() argument
3033 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3147 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, in dispc_mgr_set_timings()
3152 ytot = t.y_res + t.vfp + t.vsw + t.vbp; in dispc_mgr_set_timings()
3159 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); in dispc_mgr_set_timings()
|
| /drivers/gpu/drm/hisilicon/kirin/ |
| D | dw_drm_dsi.c | 453 u32 hfp, hbp, hsw, vfp, vbp, vsw; in dsi_set_mode_timing() local
484 vsw = mode->vsync_end - mode->vsync_start; in dsi_set_mode_timing()
485 if (vsw > 15) { in dsi_set_mode_timing()
487 vsw = 15; in dsi_set_mode_timing()
500 writel(vsw, base + VID_VSA_LINES); in dsi_set_mode_timing()
509 vtot, vfp, vbp, vsw); in dsi_set_mode_timing()
|
| D | kirin_drm_ade.c | 177 u32 hfp, hbp, hsw, vfp, vbp, vsw; in ade_ldi_set_mode() local
187 vsw = mode->vsync_end - mode->vsync_start; in ade_ldi_set_mode()
188 if (vsw > 15) { in ade_ldi_set_mode()
190 vsw = 15; in ade_ldi_set_mode()
198 writel(vsw - 1, base + LDI_VRT_CTRL1); in ade_ldi_set_mode()
|
| /drivers/video/fbdev/omap/ |
| D | hwa742.c | 792 int hsw, vsw; in setup_tearsync() local
799 vsw = hwa742_read_reg(HWA742_VS_W_REG); in setup_tearsync()
801 vs_pol_inv = !(vsw & 0x80); in setup_tearsync()
803 vsw = vsw & 0x3f; in setup_tearsync()
859 vs = vsw; in setup_tearsync()
|
| D | lcd_htcherald.c | 37 .vsw = 3,
|
| D | lcd_palmte.c | 29 .vsw = 1,
|
| D | lcd_palmtt.c | 40 .vsw = 1,
|
| D | lcd_palmz71.c | 34 .vsw = 1,
|
| D | lcd_osk.c | 60 .vsw = 1,
|
| D | lcd_inn1510.c | 42 .vsw = 1,
|
| D | lcd_h3.c | 56 .vsw = 1,
|
| D | lcd_inn1610.c | 71 .vsw = 1,
|
| D | lcd_ams_delta.c | 115 .vsw = 1,
|
| D | omapfb.h | 70 int vsw; /* Vertical synchronization member
|
| /drivers/gpu/drm/pl111/ |
| D | pl111_display.c | 134 u32 lpp, vsw, vfp, vbp; in pl111_display_enable() local
153 vsw = mode->vsync_end - mode->vsync_start - 1; in pl111_display_enable()
165 (vsw << 10) | in pl111_display_enable()
|
| /drivers/gpu/drm/mcde/ |
| D | mcde_display.c | 978 u32 vsw, vfp, vbp; in mcde_setup_dpi() local
985 vsw = mode->vsync_end - mode->vsync_start; in mcde_setup_dpi()
992 hsw, hfp, hbp, vsw, vfp, vbp); in mcde_setup_dpi()
1033 val = (vsw << MCDE_TVBL1_BEL1_SHIFT); in mcde_setup_dpi()
|
| /drivers/gpu/drm/tidss/ |
| D | tidss_dispc.c | 972 u32 hsw, hfp, hbp, vsw, vfp, vbp; in dispc_vp_enable() local
987 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_enable()
996 FLD_VAL(vsw - 1, 7, 0) | in dispc_vp_enable()
1118 u32 hsw, hfp, hbp, vsw, vfp, vbp; in dispc_vp_mode_valid() local
1161 vsw = mode->vsync_end - mode->vsync_start; in dispc_vp_mode_valid()
1169 if (vsw < 1 || vsw > 256 || in dispc_vp_mode_valid()
|