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Searched refs:wp (Results 1 – 25 of 72) sorted by relevance

123

/drivers/gpu/drm/omapdrm/dss/
Dhdmi_wp.c20 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
22 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
44 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
46 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
49 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
51 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
53 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
56 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
58 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
61 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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Dhdmi.h239 struct hdmi_wp_data *wp; member
261 struct hdmi_wp_data *wp; member
296 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
297 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
298 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
299 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
300 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
301 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
302 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
303 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
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Dhdmi5.c68 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
71 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
72 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
84 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
96 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
99 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
104 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
106 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
172 hdmi_wp_clear_irqenable(&hdmi->wp, 0xffffffff); in hdmi_power_on_full()
173 hdmi_wp_set_irqstatus(&hdmi->wp, in hdmi_power_on_full()
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Dhdmi4.c67 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_irq_handler() local
70 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
71 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
83 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
86 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
88 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
90 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
150 struct hdmi_wp_data *wp = &hdmi->wp; in hdmi_power_on_full() local
159 hdmi_wp_clear_irqenable(wp, ~HDMI_IRQ_CORE); in hdmi_power_on_full()
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Dhdmi_pll.c42 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
50 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
60 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
63 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
147 if (hpll->wp->version == 4) in hdmi_init_pll_data()
162 struct hdmi_pll_data *pll, struct hdmi_wp_data *wp) in hdmi_pll_init() argument
167 pll->wp = wp; in hdmi_pll_init()
Dhdmi4_cec.c164 hdmi_wp_clear_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
165 hdmi_wp_set_irqstatus(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
166 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
178 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0x18, 5, 0); in hdmi_cec_adap_enable()
201 hdmi_wp_set_irqenable(core->wp, HDMI_IRQ_CORE); in hdmi_cec_adap_enable()
238 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi_cec_adap_enable()
326 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
337 core->wp = wp; in hdmi4_cec_init()
340 REG_FLD_MOD(core->wp->base, HDMI_WP_CLK, 0, 5, 0); in hdmi4_cec_init()
Dhdmi4_core.h255 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
264 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
265 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
266 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
Dhdmi4_core.c257 struct hdmi_wp_data *wp, struct hdmi_config *cfg) in hdmi4_configure() argument
270 hdmi_wp_video_config_timing(wp, &vm); in hdmi4_configure()
275 hdmi_wp_video_config_format(wp, &video_format); in hdmi4_configure()
277 hdmi_wp_video_config_interface(wp, &vm); in hdmi4_configure()
632 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi4_audio_config() argument
802 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi4_audio_config()
803 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi4_audio_config()
814 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_start() argument
819 hdmi_wp_audio_core_req_enable(wp, true); in hdmi4_audio_start()
824 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_stop() argument
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Dhdmi4_cec.h20 struct hdmi_wp_data *wp);
33 struct hdmi_wp_data *wp) in hdmi4_cec_init() argument
/drivers/video/fbdev/omap2/omapfb/dss/
Dhdmi_wp.c21 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s) in hdmi_wp_dump() argument
23 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump()
45 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp) in hdmi_wp_get_irqstatus() argument
47 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus()
50 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus) in hdmi_wp_set_irqstatus() argument
52 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus()
54 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus()
57 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_set_irqenable() argument
59 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable()
62 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask) in hdmi_wp_clear_irqenable() argument
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Dhdmi.h233 struct hdmi_wp_data *wp; member
277 int hdmi_wp_video_start(struct hdmi_wp_data *wp);
278 void hdmi_wp_video_stop(struct hdmi_wp_data *wp);
279 void hdmi_wp_dump(struct hdmi_wp_data *wp, struct seq_file *s);
280 u32 hdmi_wp_get_irqstatus(struct hdmi_wp_data *wp);
281 void hdmi_wp_set_irqstatus(struct hdmi_wp_data *wp, u32 irqstatus);
282 void hdmi_wp_set_irqenable(struct hdmi_wp_data *wp, u32 mask);
283 void hdmi_wp_clear_irqenable(struct hdmi_wp_data *wp, u32 mask);
284 int hdmi_wp_set_phy_pwr(struct hdmi_wp_data *wp, enum hdmi_phy_pwr val);
285 int hdmi_wp_set_pll_pwr(struct hdmi_wp_data *wp, enum hdmi_pll_pwr val);
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Dhdmi5.c64 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
67 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
68 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
80 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
92 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
95 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
100 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
102 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
177 hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff); in hdmi_power_on_full()
178 hdmi_wp_set_irqstatus(&hdmi.wp, in hdmi_power_on_full()
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Dhdmi4.c60 struct hdmi_wp_data *wp = data; in hdmi_irq_handler() local
63 irqstatus = hdmi_wp_get_irqstatus(wp); in hdmi_irq_handler()
64 hdmi_wp_set_irqstatus(wp, irqstatus); in hdmi_irq_handler()
74 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); in hdmi_irq_handler()
76 hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | in hdmi_irq_handler()
79 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
81 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); in hdmi_irq_handler()
83 hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); in hdmi_irq_handler()
147 struct hdmi_wp_data *wp = &hdmi.wp; in hdmi_power_on_full() local
155 hdmi_wp_clear_irqenable(wp, 0xffffffff); in hdmi_power_on_full()
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Dhdmi_pll.c102 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_enable() local
106 return hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS); in hdmi_pll_enable()
112 struct hdmi_wp_data *wp = pll->wp; in hdmi_pll_disable() local
114 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF); in hdmi_pll_disable()
209 struct hdmi_wp_data *wp) in hdmi_pll_init() argument
213 pll->wp = wp; in hdmi_pll_init()
Dhdmi4_core.h253 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
258 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
259 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp);
260 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
Dhdmi4_core.c299 struct hdmi_wp_data *wp, struct hdmi_config *cfg) in hdmi4_configure() argument
312 hdmi_wp_video_config_timing(wp, &video_timing); in hdmi4_configure()
317 hdmi_wp_video_config_format(wp, &video_format); in hdmi4_configure()
319 hdmi_wp_video_config_interface(wp, &video_timing); in hdmi4_configure()
676 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, in hdmi4_audio_config() argument
846 hdmi_wp_audio_config_dma(wp, &audio_dma); in hdmi4_audio_config()
847 hdmi_wp_audio_config_format(wp, &audio_format); in hdmi4_audio_config()
858 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_start() argument
863 hdmi_wp_audio_core_req_enable(wp, true); in hdmi4_audio_start()
868 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp) in hdmi4_audio_stop() argument
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/drivers/gpu/drm/i915/display/
Dskl_watermark.c697 u32 plane_pixel_rate, struct skl_wm_params *wp,
704 const struct skl_wm_params *wp,
717 struct skl_wm_params wp; in skl_cursor_allocation() local
723 crtc_state->pixel_rate, &wp, 0); in skl_cursor_allocation()
729 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); in skl_cursor_allocation()
1695 u32 plane_pixel_rate, struct skl_wm_params *wp, in skl_compute_wm_params() argument
1710 wp->y_tiled = modifier == I915_FORMAT_MOD_Y_TILED || in skl_compute_wm_params()
1721 wp->x_tiled = modifier == I915_FORMAT_MOD_X_TILED; in skl_compute_wm_params()
1722 wp->rc_surface = modifier == I915_FORMAT_MOD_Y_TILED_CCS || in skl_compute_wm_params()
1730 wp->is_planar = intel_format_info_is_yuv_semiplanar(format, modifier); in skl_compute_wm_params()
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/drivers/block/null_blk/
Dzoned.c130 zone->wp = zone->start + zone->len; in null_init_zoned_dev()
141 zone->start = zone->wp = sector; in null_init_zoned_dev()
218 blkz.wp = zone->wp; in null_report_zones()
245 sector + nr_sectors <= zone->wp) in null_zone_valid_read_len()
248 if (sector > zone->wp) in null_zone_valid_read_len()
251 return (zone->wp - sector) << SECTOR_SHIFT; in null_zone_valid_read_len()
273 if (zone->wp == zone->start) { in __null_close_zone()
400 sector = zone->wp; in null_zone_write()
405 } else if (sector != zone->wp) { in null_zone_write()
410 if (zone->wp + nr_sectors > zone->start + zone->capacity) { in null_zone_write()
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/drivers/net/wireless/realtek/rtw88/
Dpci.h154 static inline int avail_desc(u32 wp, u32 rp, u32 len) in avail_desc() argument
156 if (rp > wp) in avail_desc()
157 return rp - wp - 1; in avail_desc()
159 return len - wp + rp - 1; in avail_desc()
183 u32 wp; member
275 buf_desc = ring->r.head + ring->r.wp * size; in get_tx_buffer_desc()
Dpci.c208 tx_ring->r.wp = 0; in rtw_pci_init_tx_ring()
298 rx_ring->r.wp = 0; in rtw_pci_init_rx_ring()
417 rtwpci->tx_rings[RTW_TX_QUEUE_H2C].r.wp = 0; in rtw_pci_reset_buf_desc()
425 rtwpci->tx_rings[RTW_TX_QUEUE_BK].r.wp = 0; in rtw_pci_reset_buf_desc()
432 rtwpci->tx_rings[RTW_TX_QUEUE_BE].r.wp = 0; in rtw_pci_reset_buf_desc()
439 rtwpci->tx_rings[RTW_TX_QUEUE_VO].r.wp = 0; in rtw_pci_reset_buf_desc()
446 rtwpci->tx_rings[RTW_TX_QUEUE_VI].r.wp = 0; in rtw_pci_reset_buf_desc()
453 rtwpci->tx_rings[RTW_TX_QUEUE_MGMT].r.wp = 0; in rtw_pci_reset_buf_desc()
460 rtwpci->tx_rings[RTW_TX_QUEUE_HI0].r.wp = 0; in rtw_pci_reset_buf_desc()
467 rtwpci->rx_rings[RTW_RX_QUEUE_MPDU].r.wp = 0; in rtw_pci_reset_buf_desc()
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/drivers/media/pci/saa7164/
Dsaa7164-core.c355 u32 wp, mcb, rp, cnt = 0; in saa7164_work_enchandler() local
382 wp = saa7164_readl(port->bufcounter); in saa7164_work_enchandler()
383 if (wp > (port->hwcfg.buffercount - 1)) { in saa7164_work_enchandler()
384 printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); in saa7164_work_enchandler()
389 if (wp == 0) in saa7164_work_enchandler()
392 mcb = wp - 1; in saa7164_work_enchandler()
432 u32 wp, mcb, rp, cnt = 0; in saa7164_work_vbihandler() local
458 wp = saa7164_readl(port->bufcounter); in saa7164_work_vbihandler()
459 if (wp > (port->hwcfg.buffercount - 1)) { in saa7164_work_vbihandler()
460 printk(KERN_ERR "%s() illegal buf count %d\n", __func__, wp); in saa7164_work_vbihandler()
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/drivers/bus/mhi/host/
Dmain.c127 db = ring->iommu_base + (ring->wp - ring->base); in mhi_ring_cmd_db()
138 db = ring->iommu_base + (ring->wp - ring->base); in mhi_ring_chan_db()
233 if (ring->wp < ring->rp) { in get_nr_avail_ring_elements()
234 nr_el = ((ring->rp - ring->wp) / ring->el_size) - 1; in get_nr_avail_ring_elements()
237 nr_el += ((ring->base + ring->len - ring->wp) / in get_nr_avail_ring_elements()
252 ring->wp += ring->el_size; in mhi_add_ring_element()
253 if (ring->wp >= (ring->base + ring->len)) in mhi_add_ring_element()
254 ring->wp = ring->base; in mhi_add_ring_element()
552 ring->wp += ring->el_size; in mhi_recycle_ev_ring_element()
554 if (ring->wp >= (ring->base + ring->len)) in mhi_recycle_ev_ring_element()
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Dpm.c224 ring->wp = ring->base + ring->len - ring->el_size; in mhi_ready_state_transition()
285 if (mhi_cmd->ring.rp != mhi_cmd->ring.wp) in mhi_pm_m0_transition()
304 if (tre_ring->base && tre_ring->wp != tre_ring->rp && in mhi_pm_m0_transition()
427 ring->wp = ring->base + ring->len - ring->el_size; in mhi_pm_mission_mode_transition()
534 ring->wp = ring->base; in mhi_pm_disable_transition()
536 cmd_ctxt->wp = cmd_ctxt->rbase; in mhi_pm_disable_transition()
550 ring->wp = ring->base; in mhi_pm_disable_transition()
552 er_ctxt->wp = er_ctxt->rbase; in mhi_pm_disable_transition()
667 ring->wp = ring->base; in mhi_pm_sys_error_transition()
669 cmd_ctxt->wp = cmd_ctxt->rbase; in mhi_pm_sys_error_transition()
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/drivers/dma/qcom/
Dgpi.c459 void *wp; member
542 static int gpi_ring_add_element(struct gpi_ring *ring, void **wp);
733 struct gpi_ring *ring, void *wp) in gpi_write_ch_db() argument
738 p_wp = to_physical(ring, wp); in gpi_write_ch_db()
744 struct gpi_ring *ring, void *wp) in gpi_write_ev_db() argument
748 p_wp = ring->phys_addr + (wp - ring->base); in gpi_write_ev_db()
1137 gpi_write_ev_db(gpii, ev_ring, ev_ring->wp); in gpi_process_events()
1213 ch_ring->wp = ch_ring->base; in gpi_reset_chan()
1336 ring->wp = (ring->base + ring->len - ring->el_size); in gpi_alloc_ev_chan()
1345 gpi_write_ev_db(gpii, ring, ring->wp); in gpi_alloc_ev_chan()
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/drivers/net/wireless/realtek/rtlwifi/
Dpci.h295 static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size) in calc_fifo_space() argument
297 if (rp <= wp) in calc_fifo_space()
298 return size - 1 + rp - wp; in calc_fifo_space()
299 return rp - wp - 1; in calc_fifo_space()

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