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Searched refs:write_csr (Results 1 – 18 of 18) sorted by relevance

/drivers/infiniband/hw/hfi1/
Dfirmware.c237 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in __read_8051_data()
239 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, in __read_8051_data()
274 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in read_8051_data()
283 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in read_8051_data()
306 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg); in write_8051()
311 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg); in write_8051()
325 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg); in write_8051()
342 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0); in write_8051()
343 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0); in write_8051()
745 write_csr(dd, what + (8 * i), *ptr); in write_rsa_data()
[all …]
Dchip.c1321 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value) in write_csr() function
1358 write_csr(dd, csr, value); in read_write_csr()
5683 write_csr(dd, SEND_EGRESS_ERR_INFO, info); in handle_send_egress_err_info()
6099 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6135 write_csr(dd, dd->hfi1_id ? ASIC_QSFP2_INVERT : in handle_qsfp_int()
6190 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_host_lcb_access()
6201 write_csr(dd, DC_DC8051_CFG_CSR_ACCESS_SEL, in set_8051_lcb_access()
6324 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, in hreq_response()
6346 write_csr(dd, DC_DC8051_CFG_EXT_DEV_0, 0); in handle_8051_request()
6367 write_csr(dd, DCC_CFG_RESET, LCB_RX_FPE_TX_FPE_INTO_RESET); in handle_8051_request()
[all …]
Deprom.c51 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_READ_DATA(offset)); in read_page()
54 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_NOP); /* close open page */ in read_page()
152 write_csr(dd, ASIC_EEP_CTL_STAT, ASIC_EEP_CTL_STAT_EP_RESET_SMASK); in eprom_init()
154 write_csr(dd, ASIC_EEP_CTL_STAT, in eprom_init()
158 write_csr(dd, ASIC_EEP_ADDR_CMD, CMD_RELEASE_POWERDOWN_NOID); in eprom_init()
Dpcie.c833 write_csr(dd, ASIC_PCIE_SD_INTRPT_LIST + (index * 8), in write_gasket_interrupt()
852 write_csr(dd, ASIC_PCIE_SD_HOST_CMD, reg); in arm_gasket_logic()
927 write_csr(dd, CCE_PCIE_CTRL, pcie_ctrl); in write_xmt_margin()
1024 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x0); in do_pcie_gen3_transition()
1250 write_csr(dd, CCE_DC_CTRL, CCE_DC_CTRL_DC_RESET_SMASK); in do_pcie_gen3_transition()
1305 write_csr(dd, MISC_CFG_FW_CTRL, fw_ctrl); in do_pcie_gen3_transition()
1327 write_csr(dd, CCE_DC_CTRL, 0); in do_pcie_gen3_transition()
1383 write_csr(dd, ASIC_CFG_THERM_POLL_EN, 0x1); in do_pcie_gen3_transition()
Dchip.h576 void write_csr(const struct hfi1_devdata *dd, u32 offset, u64 value);
594 write_csr(dd, offset0 + (0x100 * ctxt), value); in write_kctxt_csr()
629 write_csr(dd, offset0 + (0x1000 * ctxt), value); in write_uctxt_csr()
Dpio.c23 write_csr(dd, SEND_CTRL, sendctrl | SEND_CTRL_CM_RESET_SMASK); in __cm_reset()
81 write_csr(dd, SEND_CTRL, reg); in pio_send_control()
1226 write_csr(dd, SEND_PIO_ERR_CLEAR, in pio_reset_all()
1231 write_csr(dd, SEND_PIO_INIT_CTXT, in pio_reset_all()
1304 write_csr(dd, SEND_PIO_INIT_CTXT, pio); in sc_enable()
Dqsfp.c43 write_csr(dd, target_oe, reg); in hfi1_setsda()
67 write_csr(dd, target_oe, reg); in hfi1_setscl()
Ddebugfs.c579 write_csr(dd, ASIC_CFG_SCRATCH, scratch0); in asic_flags_write()
1040 write_csr(dd, ASIC_GPIO_OUT, gpio_val); in exprom_wp_set()
1041 write_csr(dd, ASIC_GPIO_OE, gpio_val); in exprom_wp_set()
Dhfi.h2385 write_csr(dd, DCC_CFG_LED_CNTRL, 0x1F); in setextled()
2387 write_csr(dd, DCC_CFG_LED_CNTRL, 0x10); in setextled()
Dmad.c1762 write_csr(dd, SEND_SC2VLT0, *val++); in set_sc2vlt_tables()
1763 write_csr(dd, SEND_SC2VLT1, *val++); in set_sc2vlt_tables()
1764 write_csr(dd, SEND_SC2VLT2, *val++); in set_sc2vlt_tables()
1765 write_csr(dd, SEND_SC2VLT3, *val++); in set_sc2vlt_tables()
3631 write_csr(dd, RCV_ERR_INFO, in pma_set_opa_errorinfo()
Dinit.c532 write_csr(dd, SEND_STATIC_RATE_CONTROL, src); in set_link_ipg()
Ddriver.c1313 write_csr(dd, DCC_CFG_LED_CNTRL, 0); in shutdown_led_override()
Dsdma.c3378 write_csr(sde->dd, in _sdma_engine_progress_schedule()
/drivers/net/ethernet/amd/
Dpcnet32.c243 void (*write_csr) (unsigned long, int, u16); member
383 .write_csr = pcnet32_wio_write_csr,
438 .write_csr = pcnet32_dwio_write_csr,
464 lp->a->write_csr(ioaddr, CSR3, val); in pcnet32_netif_start()
690 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND); in pcnet32_suspend()
715 lp->a->write_csr(ioaddr, CSR5, csr5 & ~CSR5_SUSPEND); in pcnet32_clr_suspend()
763 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); in pcnet32_set_link_ksettings()
776 lp->a->write_csr(ioaddr, CSR15, csr15); in pcnet32_set_link_ksettings()
893 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_set_ringparam()
989 lp->a->write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */ in pcnet32_loopback_test()
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/drivers/firewire/
Dcore.h92 void (*write_csr)(struct fw_card *card, int csr_offset, u32 value); member
Dcore-transaction.c1137 card->driver->write_csr(card, reg, be32_to_cpu(*data)); in handle_registers()
1144 card->driver->write_csr(card, CSR_STATE_CLEAR, in handle_registers()
Dcore-card.c678 .write_csr = dummy_write_csr,
Dohci.c3554 .write_csr = ohci_write_csr,