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Searched refs:AZX_PCIREG_CGCTL (Results 1 – 4 of 4) sorted by relevance

/sound/soc/intel/avs/
Dregisters.h13 #define AZX_PCIREG_CGCTL 0x48 macro
Dcore.c56 avs_hda_update_config_dword(bus, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, value); in avs_hdac_clock_gating_enable()
/sound/soc/intel/skylake/
Dskl.h29 #define AZX_PCIREG_CGCTL 0x48 macro
Dskl.c95 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_MISCBDCGE_MASK, val); in skl_enable_miscbdcge()
112 update_pci_dword(pci, AZX_PCIREG_CGCTL, AZX_CGCTL_ADSPDCGE, val); in skl_clock_power_gating()