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1  /* SPDX-License-Identifier: GPL-2.0 */
2  /*
3   * Copyright (C) 2020 MediaTek Inc.
4   * Author: Argus Lin <argus.lin@mediatek.com>
5   */
6  
7  #ifndef _MT6359_H_
8  #define _MT6359_H_
9  
10  /*************Register Bit Define*************/
11  #define MT6359_TOP0_ID                       0x0
12  #define MT6359_SMT_CON1                      0x32
13  #define MT6359_DRV_CON2                      0x3c
14  #define MT6359_DRV_CON3                      0x3e
15  #define MT6359_DRV_CON4                      0x40
16  #define MT6359_TOP_CKPDN_CON0                0x10c
17  #define MT6359_TOP_CKPDN_CON0_SET            0x10e
18  #define MT6359_TOP_CKPDN_CON0_CLR            0x110
19  #define MT6359_AUXADC_RQST0                  0x1108
20  #define MT6359_AUXADC_CON10                  0x11a0
21  #define MT6359_AUXADC_ACCDET                 0x11ba
22  #define MT6359_LDO_VUSB_OP_EN                0x1d0c
23  #define MT6359_LDO_VUSB_OP_EN_SET            0x1d0e
24  #define MT6359_LDO_VUSB_OP_EN_CLR            0x1d10
25  #define MT6359_AUD_TOP_CKPDN_CON0            0x230c
26  #define MT6359_AUD_TOP_CKPDN_CON0_SET        0x230e
27  #define MT6359_AUD_TOP_CKPDN_CON0_CLR        0x2310
28  #define MT6359_AUD_TOP_RST_CON0              0x2320
29  #define MT6359_AUD_TOP_RST_CON0_SET          0x2322
30  #define MT6359_AUD_TOP_RST_CON0_CLR          0x2324
31  #define MT6359_AUD_TOP_INT_CON0              0x2328
32  #define MT6359_AUD_TOP_INT_CON0_SET          0x232a
33  #define MT6359_AUD_TOP_INT_CON0_CLR          0x232c
34  #define MT6359_AUD_TOP_INT_MASK_CON0         0x232e
35  #define MT6359_AUD_TOP_INT_MASK_CON0_SET     0x2330
36  #define MT6359_AUD_TOP_INT_MASK_CON0_CLR     0x2332
37  #define MT6359_AUD_TOP_INT_STATUS0           0x2334
38  #define MT6359_AFE_NCP_CFG2                  0x24e2
39  #define MT6359_AUDENC_DSN_ID                 0x2500
40  #define MT6359_AUDENC_DSN_REV0               0x2502
41  #define MT6359_AUDENC_DSN_DBI                0x2504
42  #define MT6359_AUDENC_DSN_FPI                0x2506
43  #define MT6359_AUDENC_ANA_CON0               0x2508
44  #define MT6359_AUDENC_ANA_CON1               0x250a
45  #define MT6359_AUDENC_ANA_CON2               0x250c
46  #define MT6359_AUDENC_ANA_CON3               0x250e
47  #define MT6359_AUDENC_ANA_CON4               0x2510
48  #define MT6359_AUDENC_ANA_CON5               0x2512
49  #define MT6359_AUDENC_ANA_CON6               0x2514
50  #define MT6359_AUDENC_ANA_CON7               0x2516
51  #define MT6359_AUDENC_ANA_CON8               0x2518
52  #define MT6359_AUDENC_ANA_CON9               0x251a
53  #define MT6359_AUDENC_ANA_CON10              0x251c
54  #define MT6359_AUDENC_ANA_CON11              0x251e
55  #define MT6359_AUDENC_ANA_CON12              0x2520
56  #define MT6359_AUDENC_ANA_CON13              0x2522
57  #define MT6359_AUDENC_ANA_CON14              0x2524
58  #define MT6359_AUDENC_ANA_CON15              0x2526
59  #define MT6359_AUDENC_ANA_CON16              0x2528
60  #define MT6359_AUDENC_ANA_CON17              0x252a
61  #define MT6359_AUDENC_ANA_CON18              0x252c
62  #define MT6359_AUDENC_ANA_CON19              0x252e
63  #define MT6359_AUDENC_ANA_CON20              0x2530
64  #define MT6359_AUDENC_ANA_CON21              0x2532
65  #define MT6359_AUDENC_ANA_CON22              0x2534
66  #define MT6359_AUDENC_ANA_CON23              0x2536
67  #define MT6359_AUDDEC_DSN_ID                 0x2580
68  #define MT6359_AUDDEC_DSN_REV0               0x2582
69  #define MT6359_AUDDEC_DSN_DBI                0x2584
70  #define MT6359_AUDDEC_DSN_FPI                0x2586
71  #define MT6359_AUDDEC_ANA_CON0               0x2588
72  #define MT6359_AUDDEC_ANA_CON1               0x258a
73  #define MT6359_AUDDEC_ANA_CON2               0x258c
74  #define MT6359_AUDDEC_ANA_CON3               0x258e
75  #define MT6359_AUDDEC_ANA_CON4               0x2590
76  #define MT6359_AUDDEC_ANA_CON5               0x2592
77  #define MT6359_AUDDEC_ANA_CON6               0x2594
78  #define MT6359_AUDDEC_ANA_CON7               0x2596
79  #define MT6359_AUDDEC_ANA_CON8               0x2598
80  #define MT6359_AUDDEC_ANA_CON9               0x259a
81  #define MT6359_AUDDEC_ANA_CON10              0x259c
82  #define MT6359_AUDDEC_ANA_CON11              0x259e
83  #define MT6359_AUDDEC_ANA_CON12              0x25a0
84  #define MT6359_AUDDEC_ANA_CON13              0x25a2
85  #define MT6359_AUDDEC_ANA_CON14              0x25a4
86  #define MT6359_ACCDET_DSN_DIG_ID             0x2680
87  #define MT6359_ACCDET_DSN_DIG_REV0           0x2682
88  #define MT6359_ACCDET_DSN_DBI                0x2684
89  #define MT6359_ACCDET_DSN_FPI                0x2686
90  #define MT6359_ACCDET_CON0                   0x2688
91  #define MT6359_ACCDET_CON1                   0x268a
92  #define MT6359_ACCDET_CON2                   0x268c
93  #define MT6359_ACCDET_CON3                   0x268e
94  #define MT6359_ACCDET_CON4                   0x2690
95  #define MT6359_ACCDET_CON5                   0x2692
96  #define MT6359_ACCDET_CON6                   0x2694
97  #define MT6359_ACCDET_CON7                   0x2696
98  #define MT6359_ACCDET_CON8                   0x2698
99  #define MT6359_ACCDET_CON9                   0x269a
100  #define MT6359_ACCDET_CON10                  0x269c
101  #define MT6359_ACCDET_CON11                  0x269e
102  #define MT6359_ACCDET_CON12                  0x26a0
103  #define MT6359_ACCDET_CON13                  0x26a2
104  #define MT6359_ACCDET_CON14                  0x26a4
105  #define MT6359_ACCDET_CON15                  0x26a6
106  #define MT6359_ACCDET_CON16                  0x26a8
107  #define MT6359_ACCDET_CON17                  0x26aa
108  #define MT6359_ACCDET_CON18                  0x26ac
109  #define MT6359_ACCDET_CON19                  0x26ae
110  #define MT6359_ACCDET_CON20                  0x26b0
111  #define MT6359_ACCDET_CON21                  0x26b2
112  #define MT6359_ACCDET_CON22                  0x26b4
113  #define MT6359_ACCDET_CON23                  0x26b6
114  #define MT6359_ACCDET_CON24                  0x26b8
115  #define MT6359_ACCDET_CON25                  0x26ba
116  #define MT6359_ACCDET_CON26                  0x26bc
117  #define MT6359_ACCDET_CON27                  0x26be
118  #define MT6359_ACCDET_CON28                  0x26c0
119  #define MT6359_ACCDET_CON29                  0x26c2
120  #define MT6359_ACCDET_CON30                  0x26c4
121  #define MT6359_ACCDET_CON31                  0x26c6
122  #define MT6359_ACCDET_CON32                  0x26c8
123  #define MT6359_ACCDET_CON33                  0x26ca
124  #define MT6359_ACCDET_CON34                  0x26cc
125  #define MT6359_ACCDET_CON35                  0x26ce
126  #define MT6359_ACCDET_CON36                  0x26d0
127  #define MT6359_ACCDET_CON37                  0x26d2
128  #define MT6359_ACCDET_CON38                  0x26d4
129  #define MT6359_ACCDET_CON39                  0x26d6
130  #define MT6359_ACCDET_CON40                  0x26d8
131  
132  #define TOP0_ANA_ID_ADDR                               \
133  	MT6359_TOP0_ID
134  #define TOP0_ANA_ID_SFT                                0
135  #define TOP0_ANA_ID_MASK                               0xFF
136  #define TOP0_ANA_ID_MASK_SFT                           (0xFF << 0)
137  #define AUXADC_RQST_CH0_ADDR                           \
138  	MT6359_AUXADC_RQST0
139  #define AUXADC_RQST_CH0_SFT                            0
140  #define AUXADC_RQST_CH0_MASK                           0x1
141  #define AUXADC_RQST_CH0_MASK_SFT                       (0x1 << 0)
142  #define AUXADC_ACCDET_ANASWCTRL_EN_ADDR                \
143  	MT6359_AUXADC_CON15
144  #define AUXADC_ACCDET_ANASWCTRL_EN_SFT                 6
145  #define AUXADC_ACCDET_ANASWCTRL_EN_MASK                0x1
146  #define AUXADC_ACCDET_ANASWCTRL_EN_MASK_SFT            (0x1 << 6)
147  
148  #define AUXADC_ACCDET_AUTO_SPL_ADDR                    \
149  	MT6359_AUXADC_ACCDET
150  #define AUXADC_ACCDET_AUTO_SPL_SFT                     0
151  #define AUXADC_ACCDET_AUTO_SPL_MASK                    0x1
152  #define AUXADC_ACCDET_AUTO_SPL_MASK_SFT                (0x1 << 0)
153  #define AUXADC_ACCDET_AUTO_RQST_CLR_ADDR               \
154  	MT6359_AUXADC_ACCDET
155  #define AUXADC_ACCDET_AUTO_RQST_CLR_SFT                1
156  #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK               0x1
157  #define AUXADC_ACCDET_AUTO_RQST_CLR_MASK_SFT           (0x1 << 1)
158  #define AUXADC_ACCDET_DIG1_RSV0_ADDR                   \
159  	MT6359_AUXADC_ACCDET
160  #define AUXADC_ACCDET_DIG1_RSV0_SFT                    2
161  #define AUXADC_ACCDET_DIG1_RSV0_MASK                   0x3F
162  #define AUXADC_ACCDET_DIG1_RSV0_MASK_SFT               (0x3F << 2)
163  #define AUXADC_ACCDET_DIG0_RSV0_ADDR                   \
164  	MT6359_AUXADC_ACCDET
165  #define AUXADC_ACCDET_DIG0_RSV0_SFT                    8
166  #define AUXADC_ACCDET_DIG0_RSV0_MASK                   0xFF
167  #define AUXADC_ACCDET_DIG0_RSV0_MASK_SFT               (0xFF << 8)
168  
169  #define RG_ACCDET_CK_PDN_ADDR                          \
170  	MT6359_AUD_TOP_CKPDN_CON0
171  #define RG_ACCDET_CK_PDN_SFT                           0
172  #define RG_ACCDET_CK_PDN_MASK                          0x1
173  #define RG_ACCDET_CK_PDN_MASK_SFT                      (0x1 << 0)
174  
175  #define RG_ACCDET_RST_ADDR                             \
176  	MT6359_AUD_TOP_RST_CON0
177  #define RG_ACCDET_RST_SFT                              1
178  #define RG_ACCDET_RST_MASK                             0x1
179  #define RG_ACCDET_RST_MASK_SFT                         (0x1 << 1)
180  #define BANK_ACCDET_SWRST_ADDR                         \
181  	MT6359_AUD_TOP_RST_BANK_CON0
182  #define BANK_ACCDET_SWRST_SFT                          0
183  #define BANK_ACCDET_SWRST_MASK                         0x1
184  #define BANK_ACCDET_SWRST_MASK_SFT                     (0x1 << 0)
185  
186  #define RG_INT_EN_ACCDET_ADDR                          \
187  	MT6359_AUD_TOP_INT_CON0
188  #define RG_INT_EN_ACCDET_SFT                           5
189  #define RG_INT_EN_ACCDET_MASK                          0x1
190  #define RG_INT_EN_ACCDET_MASK_SFT                      (0x1 << 5)
191  #define RG_INT_EN_ACCDET_EINT0_ADDR                    \
192  	MT6359_AUD_TOP_INT_CON0
193  #define RG_INT_EN_ACCDET_EINT0_SFT                     6
194  #define RG_INT_EN_ACCDET_EINT0_MASK                    0x1
195  #define RG_INT_EN_ACCDET_EINT0_MASK_SFT                (0x1 << 6)
196  #define RG_INT_EN_ACCDET_EINT1_ADDR                    \
197  	MT6359_AUD_TOP_INT_CON0
198  #define RG_INT_EN_ACCDET_EINT1_SFT                     7
199  #define RG_INT_EN_ACCDET_EINT1_MASK                    0x1
200  #define RG_INT_EN_ACCDET_EINT1_MASK_SFT                (0x1 << 7)
201  
202  #define RG_INT_MASK_ACCDET_ADDR                        \
203  	MT6359_AUD_TOP_INT_MASK_CON0
204  #define RG_INT_MASK_ACCDET_SFT                         5
205  #define RG_INT_MASK_ACCDET_MASK                        0x1
206  #define RG_INT_MASK_ACCDET_MASK_SFT                    (0x1 << 5)
207  #define RG_INT_MASK_ACCDET_EINT0_ADDR                  \
208  	MT6359_AUD_TOP_INT_MASK_CON0
209  #define RG_INT_MASK_ACCDET_EINT0_SFT                   6
210  #define RG_INT_MASK_ACCDET_EINT0_MASK                  0x1
211  #define RG_INT_MASK_ACCDET_EINT0_MASK_SFT              (0x1 << 6)
212  #define RG_INT_MASK_ACCDET_EINT1_ADDR                  \
213  	MT6359_AUD_TOP_INT_MASK_CON0
214  #define RG_INT_MASK_ACCDET_EINT1_SFT                   7
215  #define RG_INT_MASK_ACCDET_EINT1_MASK                  0x1
216  #define RG_INT_MASK_ACCDET_EINT1_MASK_SFT              (0x1 << 7)
217  
218  #define RG_INT_STATUS_ACCDET_ADDR                      \
219  	MT6359_AUD_TOP_INT_STATUS0
220  #define RG_INT_STATUS_ACCDET_SFT                       5
221  #define RG_INT_STATUS_ACCDET_MASK                      0x1
222  #define RG_INT_STATUS_ACCDET_MASK_SFT                  (0x1 << 5)
223  #define RG_INT_STATUS_ACCDET_EINT0_ADDR                \
224  	MT6359_AUD_TOP_INT_STATUS0
225  #define RG_INT_STATUS_ACCDET_EINT0_SFT                 6
226  #define RG_INT_STATUS_ACCDET_EINT0_MASK                0x1
227  #define RG_INT_STATUS_ACCDET_EINT0_MASK_SFT            (0x1 << 6)
228  #define RG_INT_STATUS_ACCDET_EINT1_ADDR                \
229  	MT6359_AUD_TOP_INT_STATUS0
230  #define RG_INT_STATUS_ACCDET_EINT1_SFT                 7
231  #define RG_INT_STATUS_ACCDET_EINT1_MASK                0x1
232  #define RG_INT_STATUS_ACCDET_EINT1_MASK_SFT            (0x1 << 7)
233  
234  #define RG_INT_RAW_STATUS_ACCDET_ADDR                  \
235  	MT6359_AUD_TOP_INT_RAW_STATUS0
236  #define RG_INT_RAW_STATUS_ACCDET_SFT                   5
237  #define RG_INT_RAW_STATUS_ACCDET_MASK                  0x1
238  #define RG_INT_RAW_STATUS_ACCDET_MASK_SFT              (0x1 << 5)
239  #define RG_INT_RAW_STATUS_ACCDET_EINT0_ADDR            \
240  	MT6359_AUD_TOP_INT_RAW_STATUS0
241  #define RG_INT_RAW_STATUS_ACCDET_EINT0_SFT             6
242  #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK            0x1
243  #define RG_INT_RAW_STATUS_ACCDET_EINT0_MASK_SFT        (0x1 << 6)
244  #define RG_INT_RAW_STATUS_ACCDET_EINT1_ADDR            \
245  	MT6359_AUD_TOP_INT_RAW_STATUS0
246  #define RG_INT_RAW_STATUS_ACCDET_EINT1_SFT             7
247  #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK            0x1
248  #define RG_INT_RAW_STATUS_ACCDET_EINT1_MASK_SFT        (0x1 << 7)
249  
250  #define RG_AUDACCDETMICBIAS0PULLLOW_ADDR               \
251  	MT6359_AUDENC_ANA_CON18
252  #define RG_AUDACCDETMICBIAS0PULLLOW_SFT                0
253  #define RG_AUDACCDETMICBIAS0PULLLOW_MASK               0x1
254  #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT           (0x1 << 0)
255  #define RG_AUDACCDETMICBIAS1PULLLOW_ADDR               \
256  	MT6359_AUDENC_ANA_CON18
257  #define RG_AUDACCDETMICBIAS1PULLLOW_SFT                1
258  #define RG_AUDACCDETMICBIAS1PULLLOW_MASK               0x1
259  #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT           (0x1 << 1)
260  #define RG_AUDACCDETMICBIAS2PULLLOW_ADDR               \
261  	MT6359_AUDENC_ANA_CON18
262  #define RG_AUDACCDETMICBIAS2PULLLOW_SFT                2
263  #define RG_AUDACCDETMICBIAS2PULLLOW_MASK               0x1
264  #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT           (0x1 << 2)
265  #define RG_AUDACCDETVIN1PULLLOW_ADDR                   \
266  	MT6359_AUDENC_ANA_CON18
267  #define RG_AUDACCDETVIN1PULLLOW_SFT                    3
268  #define RG_AUDACCDETVIN1PULLLOW_MASK                   0x1
269  #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT               (0x1 << 3)
270  #define RG_AUDACCDETVTHACAL_ADDR                       \
271  	MT6359_AUDENC_ANA_CON18
272  #define RG_AUDACCDETVTHACAL_SFT                        4
273  #define RG_AUDACCDETVTHACAL_MASK                       0x1
274  #define RG_AUDACCDETVTHACAL_MASK_SFT                   (0x1 << 4)
275  #define RG_AUDACCDETVTHBCAL_ADDR                       \
276  	MT6359_AUDENC_ANA_CON18
277  #define RG_AUDACCDETVTHBCAL_SFT                        5
278  #define RG_AUDACCDETVTHBCAL_MASK                       0x1
279  #define RG_AUDACCDETVTHBCAL_MASK_SFT                   (0x1 << 5)
280  #define RG_AUDACCDETTVDET_ADDR                         \
281  	MT6359_AUDENC_ANA_CON18
282  #define RG_AUDACCDETTVDET_SFT                          6
283  #define RG_AUDACCDETTVDET_MASK                         0x1
284  #define RG_AUDACCDETTVDET_MASK_SFT                     (0x1 << 6)
285  #define RG_ACCDETSEL_ADDR                              \
286  	MT6359_AUDENC_ANA_CON18
287  #define RG_ACCDETSEL_SFT                               7
288  #define RG_ACCDETSEL_MASK                              0x1
289  #define RG_ACCDETSEL_MASK_SFT                          (0x1 << 7)
290  
291  #define RG_AUDPWDBMICBIAS1_ADDR                        \
292  	MT6359_AUDENC_ANA_CON16
293  #define RG_AUDPWDBMICBIAS1_SFT                         0
294  #define RG_AUDPWDBMICBIAS1_MASK                        0x1
295  #define RG_AUDPWDBMICBIAS1_MASK_SFT                    (0x1 << 0)
296  #define RG_AUDMICBIAS1BYPASSEN_ADDR                    \
297  	MT6359_AUDENC_ANA_CON16
298  #define RG_AUDMICBIAS1BYPASSEN_SFT                     1
299  #define RG_AUDMICBIAS1BYPASSEN_MASK                    0x1
300  #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT                (0x1 << 1)
301  #define RG_AUDMICBIAS1LOWPEN_ADDR                      \
302  	MT6359_AUDENC_ANA_CON16
303  #define RG_AUDMICBIAS1LOWPEN_SFT                       2
304  #define RG_AUDMICBIAS1LOWPEN_MASK                      0x1
305  #define RG_AUDMICBIAS1LOWPEN_MASK_SFT                  (0x1 << 2)
306  #define RG_AUDMICBIAS1VREF_ADDR                        \
307  	MT6359_AUDENC_ANA_CON16
308  #define RG_AUDMICBIAS1VREF_SFT                         4
309  #define RG_AUDMICBIAS1VREF_MASK                        0x7
310  #define RG_AUDMICBIAS1VREF_MASK_SFT                    (0x7 << 4)
311  #define RG_AUDMICBIAS1DCSW1PEN_ADDR                    \
312  	MT6359_AUDENC_ANA_CON16
313  #define RG_AUDMICBIAS1DCSW1PEN_SFT                     8
314  #define RG_AUDMICBIAS1DCSW1PEN_MASK                    0x1
315  #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT                (0x1 << 8)
316  #define RG_AUDMICBIAS1DCSW1NEN_ADDR                    \
317  	MT6359_AUDENC_ANA_CON16
318  #define RG_AUDMICBIAS1DCSW1NEN_SFT                     9
319  #define RG_AUDMICBIAS1DCSW1NEN_MASK                    0x1
320  #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT                (0x1 << 9)
321  #define RG_BANDGAPGEN_ADDR                             \
322  	MT6359_AUDENC_ANA_CON16
323  #define RG_BANDGAPGEN_SFT                              10
324  #define RG_BANDGAPGEN_MASK                             0x1
325  #define RG_BANDGAPGEN_MASK_SFT                         (0x1 << 10)
326  #define RG_AUDMICBIAS1HVEN_ADDR                        \
327  	MT6359_AUDENC_ANA_CON16
328  #define RG_AUDMICBIAS1HVEN_SFT                         12
329  #define RG_AUDMICBIAS1HVEN_MASK                        0x1
330  #define RG_AUDMICBIAS1HVEN_MASK_SFT                    (0x1 << 12)
331  #define RG_AUDMICBIAS1HVVREF_ADDR                      \
332  	MT6359_AUDENC_ANA_CON16
333  #define RG_AUDMICBIAS1HVVREF_SFT                       13
334  #define RG_AUDMICBIAS1HVVREF_MASK                      0x1
335  #define RG_AUDMICBIAS1HVVREF_MASK_SFT                  (0x1 << 13)
336  
337  #define RG_EINT0NOHYS_ADDR                             \
338  	MT6359_AUDENC_ANA_CON18
339  #define RG_EINT0NOHYS_SFT                              10
340  #define RG_EINT0NOHYS_MASK                             0x1
341  #define RG_EINT0NOHYS_MASK_SFT                         (0x1 << 10)
342  #define RG_EINT0CONFIGACCDET_ADDR                      \
343  	MT6359_AUDENC_ANA_CON18
344  #define RG_EINT0CONFIGACCDET_SFT                       11
345  #define RG_EINT0CONFIGACCDET_MASK                      0x1
346  #define RG_EINT0CONFIGACCDET_MASK_SFT                  (0x1 << 11)
347  #define RG_EINT0HIRENB_ADDR                            \
348  	MT6359_AUDENC_ANA_CON18
349  #define RG_EINT0HIRENB_SFT                             12
350  #define RG_EINT0HIRENB_MASK                            0x1
351  #define RG_EINT0HIRENB_MASK_SFT                        (0x1 << 12)
352  #define RG_ACCDET2AUXRESBYPASS_ADDR                    \
353  	MT6359_AUDENC_ANA_CON18
354  #define RG_ACCDET2AUXRESBYPASS_SFT                     13
355  #define RG_ACCDET2AUXRESBYPASS_MASK                    0x1
356  #define RG_ACCDET2AUXRESBYPASS_MASK_SFT                (0x1 << 13)
357  #define RG_ACCDET2AUXSWEN_ADDR                         \
358  	MT6359_AUDENC_ANA_CON18
359  #define RG_ACCDET2AUXSWEN_SFT                          14
360  #define RG_ACCDET2AUXSWEN_MASK                         0x1
361  #define RG_ACCDET2AUXSWEN_MASK_SFT                     (0x1 << 14)
362  #define RG_AUDACCDETMICBIAS3PULLLOW_ADDR               \
363  	MT6359_AUDENC_ANA_CON18
364  #define RG_AUDACCDETMICBIAS3PULLLOW_SFT                15
365  #define RG_AUDACCDETMICBIAS3PULLLOW_MASK               0x1
366  #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT           (0x1 << 15)
367  #define RG_EINT1CONFIGACCDET_ADDR                      \
368  	MT6359_AUDENC_ANA_CON19
369  #define RG_EINT1CONFIGACCDET_SFT                       0
370  #define RG_EINT1CONFIGACCDET_MASK                      0x1
371  #define RG_EINT1CONFIGACCDET_MASK_SFT                  (0x1 << 0)
372  #define RG_EINT1HIRENB_ADDR                            \
373  	MT6359_AUDENC_ANA_CON19
374  #define RG_EINT1HIRENB_SFT                             1
375  #define RG_EINT1HIRENB_MASK                            0x1
376  #define RG_EINT1HIRENB_MASK_SFT                        (0x1 << 1)
377  #define RG_EINT1NOHYS_ADDR                             \
378  	MT6359_AUDENC_ANA_CON19
379  #define RG_EINT1NOHYS_SFT                              2
380  #define RG_EINT1NOHYS_MASK                             0x1
381  #define RG_EINT1NOHYS_MASK_SFT                         (0x1 << 2)
382  #define RG_EINTCOMPVTH_ADDR                            \
383  	MT6359_AUDENC_ANA_CON19
384  #define RG_MTEST_EN_ADDR                               \
385  	MT6359_AUDENC_ANA_CON19
386  #define RG_MTEST_EN_SFT                                8
387  #define RG_MTEST_EN_MASK                               0x1
388  #define RG_MTEST_EN_MASK_SFT                           (0x1 << 8)
389  #define RG_MTEST_SEL_ADDR                              \
390  	MT6359_AUDENC_ANA_CON19
391  #define RG_MTEST_SEL_SFT                               9
392  #define RG_MTEST_SEL_MASK                              0x1
393  #define RG_MTEST_SEL_MASK_SFT                          (0x1 << 9)
394  #define RG_MTEST_CURRENT_ADDR                          \
395  	MT6359_AUDENC_ANA_CON19
396  #define RG_MTEST_CURRENT_SFT                           10
397  #define RG_MTEST_CURRENT_MASK                          0x1
398  #define RG_MTEST_CURRENT_MASK_SFT                      (0x1 << 10)
399  #define RG_ANALOGFDEN_ADDR                             \
400  	MT6359_AUDENC_ANA_CON19
401  #define RG_ANALOGFDEN_SFT                              12
402  #define RG_ANALOGFDEN_MASK                             0x1
403  #define RG_ANALOGFDEN_MASK_SFT                         (0x1 << 12)
404  #define RG_FDVIN1PPULLLOW_ADDR                         \
405  	MT6359_AUDENC_ANA_CON19
406  #define RG_FDVIN1PPULLLOW_SFT                          13
407  #define RG_FDVIN1PPULLLOW_MASK                         0x1
408  #define RG_FDVIN1PPULLLOW_MASK_SFT                     (0x1 << 13)
409  #define RG_FDEINT0TYPE_ADDR                            \
410  	MT6359_AUDENC_ANA_CON19
411  #define RG_FDEINT0TYPE_SFT                             14
412  #define RG_FDEINT0TYPE_MASK                            0x1
413  #define RG_FDEINT0TYPE_MASK_SFT                        (0x1 << 14)
414  #define RG_FDEINT1TYPE_ADDR                            \
415  	MT6359_AUDENC_ANA_CON19
416  #define RG_FDEINT1TYPE_SFT                             15
417  #define RG_FDEINT1TYPE_MASK                            0x1
418  #define RG_FDEINT1TYPE_MASK_SFT                        (0x1 << 15)
419  #define RG_EINT0CMPEN_ADDR                             \
420  	MT6359_AUDENC_ANA_CON20
421  #define RG_EINT0CMPEN_SFT                              0
422  #define RG_EINT0CMPEN_MASK                             0x1
423  #define RG_EINT0CMPEN_MASK_SFT                         (0x1 << 0)
424  #define RG_EINT0CMPMEN_ADDR                            \
425  	MT6359_AUDENC_ANA_CON20
426  #define RG_EINT0CMPMEN_SFT                             1
427  #define RG_EINT0CMPMEN_MASK                            0x1
428  #define RG_EINT0CMPMEN_MASK_SFT                        (0x1 << 1)
429  #define RG_EINT0EN_ADDR                                \
430  	MT6359_AUDENC_ANA_CON20
431  #define RG_EINT0EN_SFT                                 2
432  #define RG_EINT0EN_MASK                                0x1
433  #define RG_EINT0EN_MASK_SFT                            (0x1 << 2)
434  #define RG_EINT0CEN_ADDR                               \
435  	MT6359_AUDENC_ANA_CON20
436  #define RG_EINT0CEN_SFT                                3
437  #define RG_EINT0CEN_MASK                               0x1
438  #define RG_EINT0CEN_MASK_SFT                           (0x1 << 3)
439  #define RG_EINT0INVEN_ADDR                             \
440  	MT6359_AUDENC_ANA_CON20
441  #define RG_EINT0INVEN_SFT                              4
442  #define RG_EINT0INVEN_MASK                             0x1
443  #define RG_EINT0INVEN_MASK_SFT                         (0x1 << 4)
444  #define RG_EINT0CTURBO_ADDR                            \
445  	MT6359_AUDENC_ANA_CON20
446  #define RG_EINT0CTURBO_SFT                             5
447  #define RG_EINT0CTURBO_MASK                            0x7
448  #define RG_EINT0CTURBO_MASK_SFT                        (0x7 << 5)
449  #define RG_EINT1CMPEN_ADDR                             \
450  	MT6359_AUDENC_ANA_CON20
451  #define RG_EINT1CMPEN_SFT                              8
452  #define RG_EINT1CMPEN_MASK                             0x1
453  #define RG_EINT1CMPEN_MASK_SFT                         (0x1 << 8)
454  #define RG_EINT1CMPMEN_ADDR                            \
455  	MT6359_AUDENC_ANA_CON20
456  #define RG_EINT1CMPMEN_SFT                             9
457  #define RG_EINT1CMPMEN_MASK                            0x1
458  #define RG_EINT1CMPMEN_MASK_SFT                        (0x1 << 9)
459  #define RG_EINT1EN_ADDR                                \
460  	MT6359_AUDENC_ANA_CON20
461  #define RG_EINT1EN_SFT                                 10
462  #define RG_EINT1EN_MASK                                0x1
463  #define RG_EINT1EN_MASK_SFT                            (0x1 << 10)
464  #define RG_EINT1CEN_ADDR                               \
465  	MT6359_AUDENC_ANA_CON20
466  #define RG_EINT1CEN_SFT                                11
467  #define RG_EINT1CEN_MASK                               0x1
468  #define RG_EINT1CEN_MASK_SFT                           (0x1 << 11)
469  #define RG_EINT1INVEN_ADDR                             \
470  	MT6359_AUDENC_ANA_CON20
471  #define RG_EINT1INVEN_SFT                              12
472  #define RG_EINT1INVEN_MASK                             0x1
473  #define RG_EINT1INVEN_MASK_SFT                         (0x1 << 12)
474  #define RG_EINT1CTURBO_ADDR                            \
475  	MT6359_AUDENC_ANA_CON20
476  #define RG_EINT1CTURBO_SFT                             13
477  #define RG_EINT1CTURBO_MASK                            0x7
478  #define RG_EINT1CTURBO_MASK_SFT                        (0x7 << 13)
479  #define RG_ACCDETSPARE_ADDR                            \
480  	MT6359_AUDENC_ANA_CON21
481  
482  #define ACCDET_ANA_ID_ADDR                             \
483  	MT6359_ACCDET_DSN_DIG_ID
484  #define ACCDET_ANA_ID_SFT                              0
485  #define ACCDET_ANA_ID_MASK                             0xFF
486  #define ACCDET_ANA_ID_MASK_SFT                         (0xFF << 0)
487  #define ACCDET_DIG_ID_ADDR                             \
488  	MT6359_ACCDET_DSN_DIG_ID
489  #define ACCDET_DIG_ID_SFT                              8
490  #define ACCDET_DIG_ID_MASK                             0xFF
491  #define ACCDET_DIG_ID_MASK_SFT                         (0xFF << 8)
492  #define ACCDET_ANA_MINOR_REV_ADDR                      \
493  	MT6359_ACCDET_DSN_DIG_REV0
494  #define ACCDET_ANA_MINOR_REV_SFT                       0
495  #define ACCDET_ANA_MINOR_REV_MASK                      0xF
496  #define ACCDET_ANA_MINOR_REV_MASK_SFT                  (0xF << 0)
497  #define ACCDET_ANA_MAJOR_REV_ADDR                      \
498  	MT6359_ACCDET_DSN_DIG_REV0
499  #define ACCDET_ANA_MAJOR_REV_SFT                       4
500  #define ACCDET_ANA_MAJOR_REV_MASK                      0xF
501  #define ACCDET_ANA_MAJOR_REV_MASK_SFT                  (0xF << 4)
502  #define ACCDET_DIG_MINOR_REV_ADDR                      \
503  	MT6359_ACCDET_DSN_DIG_REV0
504  #define ACCDET_DIG_MINOR_REV_SFT                       8
505  #define ACCDET_DIG_MINOR_REV_MASK                      0xF
506  #define ACCDET_DIG_MINOR_REV_MASK_SFT                  (0xF << 8)
507  #define ACCDET_DIG_MAJOR_REV_ADDR                      \
508  	MT6359_ACCDET_DSN_DIG_REV0
509  #define ACCDET_DIG_MAJOR_REV_SFT                       12
510  #define ACCDET_DIG_MAJOR_REV_MASK                      0xF
511  #define ACCDET_DIG_MAJOR_REV_MASK_SFT                  (0xF << 12)
512  #define ACCDET_DSN_CBS_ADDR                            \
513  	MT6359_ACCDET_DSN_DBI
514  #define ACCDET_DSN_CBS_SFT                             0
515  #define ACCDET_DSN_CBS_MASK                            0x3
516  #define ACCDET_DSN_CBS_MASK_SFT                        (0x3 << 0)
517  #define ACCDET_DSN_BIX_ADDR                            \
518  	MT6359_ACCDET_DSN_DBI
519  #define ACCDET_DSN_BIX_SFT                             2
520  #define ACCDET_DSN_BIX_MASK                            0x3
521  #define ACCDET_DSN_BIX_MASK_SFT                        (0x3 << 2)
522  #define ACCDET_ESP_ADDR                                \
523  	MT6359_ACCDET_DSN_DBI
524  #define ACCDET_ESP_SFT                                 8
525  #define ACCDET_ESP_MASK                                0xFF
526  #define ACCDET_ESP_MASK_SFT                            (0xFF << 8)
527  #define ACCDET_DSN_FPI_ADDR                            \
528  	MT6359_ACCDET_DSN_FPI
529  #define ACCDET_DSN_FPI_SFT                             0
530  #define ACCDET_DSN_FPI_MASK                            0xFF
531  #define ACCDET_DSN_FPI_MASK_SFT                        (0xFF << 0)
532  #define ACCDET_AUXADC_SEL_ADDR                         \
533  	MT6359_ACCDET_CON0
534  #define ACCDET_AUXADC_SEL_SFT                          0
535  #define ACCDET_AUXADC_SEL_MASK                         0x1
536  #define ACCDET_AUXADC_SEL_MASK_SFT                     (0x1 << 0)
537  #define ACCDET_AUXADC_SW_ADDR                          \
538  	MT6359_ACCDET_CON0
539  #define ACCDET_AUXADC_SW_SFT                           1
540  #define ACCDET_AUXADC_SW_MASK                          0x1
541  #define ACCDET_AUXADC_SW_MASK_SFT                      (0x1 << 1)
542  #define ACCDET_TEST_AUXADC_ADDR                        \
543  	MT6359_ACCDET_CON0
544  #define ACCDET_TEST_AUXADC_SFT                         2
545  #define ACCDET_TEST_AUXADC_MASK                        0x1
546  #define ACCDET_TEST_AUXADC_MASK_SFT                    (0x1 << 2)
547  #define ACCDET_AUXADC_ANASWCTRL_SEL_ADDR               \
548  	MT6359_ACCDET_CON0
549  #define ACCDET_AUXADC_ANASWCTRL_SEL_SFT                8
550  #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK               0x1
551  #define ACCDET_AUXADC_ANASWCTRL_SEL_MASK_SFT           (0x1 << 8)
552  #define AUDACCDETAUXADCSWCTRL_SEL_ADDR                 \
553  	MT6359_ACCDET_CON0
554  #define AUDACCDETAUXADCSWCTRL_SEL_SFT                  9
555  #define AUDACCDETAUXADCSWCTRL_SEL_MASK                 0x1
556  #define AUDACCDETAUXADCSWCTRL_SEL_MASK_SFT             (0x1 << 9)
557  #define AUDACCDETAUXADCSWCTRL_SW_ADDR                  \
558  	MT6359_ACCDET_CON0
559  #define AUDACCDETAUXADCSWCTRL_SW_SFT                   10
560  #define AUDACCDETAUXADCSWCTRL_SW_MASK                  0x1
561  #define AUDACCDETAUXADCSWCTRL_SW_MASK_SFT              (0x1 << 10)
562  #define ACCDET_TEST_ANA_ADDR                           \
563  	MT6359_ACCDET_CON0
564  #define ACCDET_TEST_ANA_SFT                            11
565  #define ACCDET_TEST_ANA_MASK                           0x1
566  #define ACCDET_TEST_ANA_MASK_SFT                       (0x1 << 11)
567  #define RG_AUDACCDETRSV_ADDR                           \
568  	MT6359_ACCDET_CON0
569  #define RG_AUDACCDETRSV_SFT                            13
570  #define RG_AUDACCDETRSV_MASK                           0x3
571  #define RG_AUDACCDETRSV_MASK_SFT                       (0x3 << 13)
572  #define ACCDET_SW_EN_ADDR                              \
573  	MT6359_ACCDET_CON1
574  #define ACCDET_SW_EN_SFT                               0
575  #define ACCDET_SW_EN_MASK                              0x1
576  #define ACCDET_SW_EN_MASK_SFT                          (0x1 << 0)
577  #define ACCDET_SEQ_INIT_ADDR                           \
578  	MT6359_ACCDET_CON1
579  #define ACCDET_SEQ_INIT_SFT                            1
580  #define ACCDET_SEQ_INIT_MASK                           0x1
581  #define ACCDET_SEQ_INIT_MASK_SFT                       (0x1 << 1)
582  #define ACCDET_EINT0_SW_EN_ADDR                        \
583  	MT6359_ACCDET_CON1
584  #define ACCDET_EINT0_SW_EN_SFT                         2
585  #define ACCDET_EINT0_SW_EN_MASK                        0x1
586  #define ACCDET_EINT0_SW_EN_MASK_SFT                    (0x1 << 2)
587  #define ACCDET_EINT0_SEQ_INIT_ADDR                     \
588  	MT6359_ACCDET_CON1
589  #define ACCDET_EINT0_SEQ_INIT_SFT                      3
590  #define ACCDET_EINT0_SEQ_INIT_MASK                     0x1
591  #define ACCDET_EINT0_SEQ_INIT_MASK_SFT                 (0x1 << 3)
592  #define ACCDET_EINT1_SW_EN_ADDR                        \
593  	MT6359_ACCDET_CON1
594  #define ACCDET_EINT1_SW_EN_SFT                         4
595  #define ACCDET_EINT1_SW_EN_MASK                        0x1
596  #define ACCDET_EINT1_SW_EN_MASK_SFT                    (0x1 << 4)
597  #define ACCDET_EINT1_SEQ_INIT_ADDR                     \
598  	MT6359_ACCDET_CON1
599  #define ACCDET_EINT1_SEQ_INIT_SFT                      5
600  #define ACCDET_EINT1_SEQ_INIT_MASK                     0x1
601  #define ACCDET_EINT1_SEQ_INIT_MASK_SFT                 (0x1 << 5)
602  #define ACCDET_EINT0_INVERTER_SW_EN_ADDR               \
603  	MT6359_ACCDET_CON1
604  #define ACCDET_EINT0_INVERTER_SW_EN_SFT                6
605  #define ACCDET_EINT0_INVERTER_SW_EN_MASK               0x1
606  #define ACCDET_EINT0_INVERTER_SW_EN_MASK_SFT           (0x1 << 6)
607  #define ACCDET_EINT0_INVERTER_SEQ_INIT_ADDR            \
608  	MT6359_ACCDET_CON1
609  #define ACCDET_EINT0_INVERTER_SEQ_INIT_SFT             7
610  #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK            0x1
611  #define ACCDET_EINT0_INVERTER_SEQ_INIT_MASK_SFT        (0x1 << 7)
612  #define ACCDET_EINT1_INVERTER_SW_EN_ADDR               \
613  	MT6359_ACCDET_CON1
614  #define ACCDET_EINT1_INVERTER_SW_EN_SFT                8
615  #define ACCDET_EINT1_INVERTER_SW_EN_MASK               0x1
616  #define ACCDET_EINT1_INVERTER_SW_EN_MASK_SFT           (0x1 << 8)
617  #define ACCDET_EINT1_INVERTER_SEQ_INIT_ADDR            \
618  	MT6359_ACCDET_CON1
619  #define ACCDET_EINT1_INVERTER_SEQ_INIT_SFT             9
620  #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK            0x1
621  #define ACCDET_EINT1_INVERTER_SEQ_INIT_MASK_SFT        (0x1 << 9)
622  #define ACCDET_EINT0_M_SW_EN_ADDR                      \
623  	MT6359_ACCDET_CON1
624  #define ACCDET_EINT0_M_SW_EN_SFT                       10
625  #define ACCDET_EINT0_M_SW_EN_MASK                      0x1
626  #define ACCDET_EINT0_M_SW_EN_MASK_SFT                  (0x1 << 10)
627  #define ACCDET_EINT1_M_SW_EN_ADDR                      \
628  	MT6359_ACCDET_CON1
629  #define ACCDET_EINT1_M_SW_EN_SFT                       11
630  #define ACCDET_EINT1_M_SW_EN_MASK                      0x1
631  #define ACCDET_EINT1_M_SW_EN_MASK_SFT                  (0x1 << 11)
632  #define ACCDET_EINT_M_DETECT_EN_ADDR                   \
633  	MT6359_ACCDET_CON1
634  #define ACCDET_EINT_M_DETECT_EN_SFT                    12
635  #define ACCDET_EINT_M_DETECT_EN_MASK                   0x1
636  #define ACCDET_EINT_M_DETECT_EN_MASK_SFT               (0x1 << 12)
637  #define ACCDET_CMP_PWM_EN_ADDR                         \
638  	MT6359_ACCDET_CON2
639  #define ACCDET_CMP_PWM_EN_SFT                          0
640  #define ACCDET_CMP_PWM_EN_MASK                         0x1
641  #define ACCDET_CMP_PWM_EN_MASK_SFT                     (0x1 << 0)
642  #define ACCDET_VTH_PWM_EN_ADDR                         \
643  	MT6359_ACCDET_CON2
644  #define ACCDET_VTH_PWM_EN_SFT                          1
645  #define ACCDET_VTH_PWM_EN_MASK                         0x1
646  #define ACCDET_VTH_PWM_EN_MASK_SFT                     (0x1 << 1)
647  #define ACCDET_MBIAS_PWM_EN_ADDR                       \
648  	MT6359_ACCDET_CON2
649  #define ACCDET_MBIAS_PWM_EN_SFT                        2
650  #define ACCDET_MBIAS_PWM_EN_MASK                       0x1
651  #define ACCDET_MBIAS_PWM_EN_MASK_SFT                   (0x1 << 2)
652  #define ACCDET_EINT_EN_PWM_EN_ADDR                     \
653  	MT6359_ACCDET_CON2
654  #define ACCDET_EINT_EN_PWM_EN_SFT                      3
655  #define ACCDET_EINT_EN_PWM_EN_MASK                     0x1
656  #define ACCDET_EINT_EN_PWM_EN_MASK_SFT                 (0x1 << 3)
657  #define ACCDET_EINT_CMPEN_PWM_EN_ADDR                  \
658  	MT6359_ACCDET_CON2
659  #define ACCDET_EINT_CMPEN_PWM_EN_SFT                   4
660  #define ACCDET_EINT_CMPEN_PWM_EN_MASK                  0x1
661  #define ACCDET_EINT_CMPEN_PWM_EN_MASK_SFT              (0x1 << 4)
662  #define ACCDET_EINT_CMPMEN_PWM_EN_ADDR                 \
663  	MT6359_ACCDET_CON2
664  #define ACCDET_EINT_CMPMEN_PWM_EN_SFT                  5
665  #define ACCDET_EINT_CMPMEN_PWM_EN_MASK                 0x1
666  #define ACCDET_EINT_CMPMEN_PWM_EN_MASK_SFT             (0x1 << 5)
667  #define ACCDET_EINT_CTURBO_PWM_EN_ADDR                 \
668  	MT6359_ACCDET_CON2
669  #define ACCDET_EINT_CTURBO_PWM_EN_SFT                  6
670  #define ACCDET_EINT_CTURBO_PWM_EN_MASK                 0x1
671  #define ACCDET_EINT_CTURBO_PWM_EN_MASK_SFT             (0x1 << 6)
672  #define ACCDET_CMP_PWM_IDLE_ADDR                       \
673  	MT6359_ACCDET_CON2
674  #define ACCDET_CMP_PWM_IDLE_SFT                        8
675  #define ACCDET_CMP_PWM_IDLE_MASK                       0x1
676  #define ACCDET_CMP_PWM_IDLE_MASK_SFT                   (0x1 << 8)
677  #define ACCDET_VTH_PWM_IDLE_ADDR                       \
678  	MT6359_ACCDET_CON2
679  #define ACCDET_VTH_PWM_IDLE_SFT                        9
680  #define ACCDET_VTH_PWM_IDLE_MASK                       0x1
681  #define ACCDET_VTH_PWM_IDLE_MASK_SFT                   (0x1 << 9)
682  #define ACCDET_MBIAS_PWM_IDLE_ADDR                     \
683  	MT6359_ACCDET_CON2
684  #define ACCDET_MBIAS_PWM_IDLE_SFT                      10
685  #define ACCDET_MBIAS_PWM_IDLE_MASK                     0x1
686  #define ACCDET_MBIAS_PWM_IDLE_MASK_SFT                 (0x1 << 10)
687  #define ACCDET_EINT0_CMPEN_PWM_IDLE_ADDR               \
688  	MT6359_ACCDET_CON2
689  #define ACCDET_EINT0_CMPEN_PWM_IDLE_SFT                11
690  #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK               0x1
691  #define ACCDET_EINT0_CMPEN_PWM_IDLE_MASK_SFT           (0x1 << 11)
692  #define ACCDET_EINT1_CMPEN_PWM_IDLE_ADDR               \
693  	MT6359_ACCDET_CON2
694  #define ACCDET_EINT1_CMPEN_PWM_IDLE_SFT                12
695  #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK               0x1
696  #define ACCDET_EINT1_CMPEN_PWM_IDLE_MASK_SFT           (0x1 << 12)
697  #define ACCDET_PWM_EN_SW_ADDR                          \
698  	MT6359_ACCDET_CON2
699  #define ACCDET_PWM_EN_SW_SFT                           13
700  #define ACCDET_PWM_EN_SW_MASK                          0x1
701  #define ACCDET_PWM_EN_SW_MASK_SFT                      (0x1 << 13)
702  #define ACCDET_PWM_EN_SEL_ADDR                         \
703  	MT6359_ACCDET_CON2
704  #define ACCDET_PWM_EN_SEL_SFT                          14
705  #define ACCDET_PWM_EN_SEL_MASK                         0x3
706  #define ACCDET_PWM_EN_SEL_MASK_SFT                     (0x3 << 14)
707  #define ACCDET_PWM_WIDTH_ADDR                          \
708  	MT6359_ACCDET_CON3
709  #define ACCDET_PWM_WIDTH_SFT                           0
710  #define ACCDET_PWM_WIDTH_MASK                          0xFFFF
711  #define ACCDET_PWM_WIDTH_MASK_SFT                      (0xFFFF << 0)
712  #define ACCDET_PWM_THRESH_ADDR                         \
713  	MT6359_ACCDET_CON4
714  #define ACCDET_PWM_THRESH_SFT                          0
715  #define ACCDET_PWM_THRESH_MASK                         0xFFFF
716  #define ACCDET_PWM_THRESH_MASK_SFT                     (0xFFFF << 0)
717  #define ACCDET_RISE_DELAY_ADDR                         \
718  	MT6359_ACCDET_CON5
719  #define ACCDET_RISE_DELAY_SFT                          0
720  #define ACCDET_RISE_DELAY_MASK                         0x7FFF
721  #define ACCDET_RISE_DELAY_MASK_SFT                     (0x7FFF << 0)
722  #define ACCDET_FALL_DELAY_ADDR                         \
723  	MT6359_ACCDET_CON5
724  #define ACCDET_FALL_DELAY_SFT                          15
725  #define ACCDET_FALL_DELAY_MASK                         0x1
726  #define ACCDET_FALL_DELAY_MASK_SFT                     (0x1 << 15)
727  #define ACCDET_EINT_CMPMEN_PWM_THRESH_ADDR             \
728  	MT6359_ACCDET_CON6
729  #define ACCDET_EINT_CMPMEN_PWM_THRESH_SFT              0
730  #define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK             0x7
731  #define ACCDET_EINT_CMPMEN_PWM_THRESH_MASK_SFT         (0x7 << 0)
732  #define ACCDET_EINT_CMPMEN_PWM_WIDTH_ADDR              \
733  	MT6359_ACCDET_CON6
734  #define ACCDET_EINT_CMPMEN_PWM_WIDTH_SFT               4
735  #define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK              0x7
736  #define ACCDET_EINT_CMPMEN_PWM_WIDTH_MASK_SFT          (0x7 << 4)
737  #define ACCDET_EINT_EN_PWM_THRESH_ADDR                 \
738  	MT6359_ACCDET_CON7
739  #define ACCDET_EINT_EN_PWM_THRESH_SFT                  0
740  #define ACCDET_EINT_EN_PWM_THRESH_MASK                 0x7
741  #define ACCDET_EINT_EN_PWM_THRESH_MASK_SFT             (0x7 << 0)
742  #define ACCDET_EINT_EN_PWM_WIDTH_ADDR                  \
743  	MT6359_ACCDET_CON7
744  #define ACCDET_EINT_EN_PWM_WIDTH_SFT                   4
745  #define ACCDET_EINT_EN_PWM_WIDTH_MASK                  0x3
746  #define ACCDET_EINT_EN_PWM_WIDTH_MASK_SFT              (0x3 << 4)
747  #define ACCDET_EINT_CMPEN_PWM_THRESH_ADDR              \
748  	MT6359_ACCDET_CON7
749  #define ACCDET_EINT_CMPEN_PWM_THRESH_SFT               8
750  #define ACCDET_EINT_CMPEN_PWM_THRESH_MASK              0x7
751  #define ACCDET_EINT_CMPEN_PWM_THRESH_MASK_SFT          (0x7 << 8)
752  #define ACCDET_EINT_CMPEN_PWM_WIDTH_ADDR               \
753  	MT6359_ACCDET_CON7
754  #define ACCDET_EINT_CMPEN_PWM_WIDTH_SFT                12
755  #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK               0x3
756  #define ACCDET_EINT_CMPEN_PWM_WIDTH_MASK_SFT           (0x3 << 12)
757  #define ACCDET_DEBOUNCE0_ADDR                          \
758  	MT6359_ACCDET_CON8
759  #define ACCDET_DEBOUNCE0_SFT                           0
760  #define ACCDET_DEBOUNCE0_MASK                          0xFFFF
761  #define ACCDET_DEBOUNCE0_MASK_SFT                      (0xFFFF << 0)
762  #define ACCDET_DEBOUNCE1_ADDR                          \
763  	MT6359_ACCDET_CON9
764  #define ACCDET_DEBOUNCE1_SFT                           0
765  #define ACCDET_DEBOUNCE1_MASK                          0xFFFF
766  #define ACCDET_DEBOUNCE1_MASK_SFT                      (0xFFFF << 0)
767  #define ACCDET_DEBOUNCE2_ADDR                          \
768  	MT6359_ACCDET_CON10
769  #define ACCDET_DEBOUNCE2_SFT                           0
770  #define ACCDET_DEBOUNCE2_MASK                          0xFFFF
771  #define ACCDET_DEBOUNCE2_MASK_SFT                      (0xFFFF << 0)
772  #define ACCDET_DEBOUNCE3_ADDR                          \
773  	MT6359_ACCDET_CON11
774  #define ACCDET_DEBOUNCE3_SFT                           0
775  #define ACCDET_DEBOUNCE3_MASK                          0xFFFF
776  #define ACCDET_DEBOUNCE3_MASK_SFT                      (0xFFFF << 0)
777  #define ACCDET_CONNECT_AUXADC_TIME_DIG_ADDR            \
778  	MT6359_ACCDET_CON12
779  #define ACCDET_CONNECT_AUXADC_TIME_DIG_SFT             0
780  #define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK            0xFFFF
781  #define ACCDET_CONNECT_AUXADC_TIME_DIG_MASK_SFT        (0xFFFF << 0)
782  #define ACCDET_CONNECT_AUXADC_TIME_ANA_ADDR            \
783  	MT6359_ACCDET_CON13
784  #define ACCDET_CONNECT_AUXADC_TIME_ANA_SFT             0
785  #define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK            0xFFFF
786  #define ACCDET_CONNECT_AUXADC_TIME_ANA_MASK_SFT        (0xFFFF << 0)
787  #define ACCDET_EINT_DEBOUNCE0_ADDR                     \
788  	MT6359_ACCDET_CON14
789  #define ACCDET_EINT_DEBOUNCE0_SFT                      0
790  #define ACCDET_EINT_DEBOUNCE0_MASK                     0xF
791  #define ACCDET_EINT_DEBOUNCE0_MASK_SFT                 (0xF << 0)
792  #define ACCDET_EINT_DEBOUNCE1_ADDR                     \
793  	MT6359_ACCDET_CON14
794  #define ACCDET_EINT_DEBOUNCE1_SFT                      4
795  #define ACCDET_EINT_DEBOUNCE1_MASK                     0xF
796  #define ACCDET_EINT_DEBOUNCE1_MASK_SFT                 (0xF << 4)
797  #define ACCDET_EINT_DEBOUNCE2_ADDR                     \
798  	MT6359_ACCDET_CON14
799  #define ACCDET_EINT_DEBOUNCE2_SFT                      8
800  #define ACCDET_EINT_DEBOUNCE2_MASK                     0xF
801  #define ACCDET_EINT_DEBOUNCE2_MASK_SFT                 (0xF << 8)
802  #define ACCDET_EINT_DEBOUNCE3_ADDR                     \
803  	MT6359_ACCDET_CON14
804  #define ACCDET_EINT_DEBOUNCE3_SFT                      12
805  #define ACCDET_EINT_DEBOUNCE3_MASK                     0xF
806  #define ACCDET_EINT_DEBOUNCE3_MASK_SFT                 (0xF << 12)
807  #define ACCDET_EINT_INVERTER_DEBOUNCE_ADDR             \
808  	MT6359_ACCDET_CON15
809  #define ACCDET_EINT_INVERTER_DEBOUNCE_SFT              0
810  #define ACCDET_EINT_INVERTER_DEBOUNCE_MASK             0xF
811  #define ACCDET_EINT_INVERTER_DEBOUNCE_MASK_SFT         (0xF << 0)
812  #define ACCDET_IVAL_CUR_IN_ADDR                        \
813  	MT6359_ACCDET_CON16
814  #define ACCDET_IVAL_CUR_IN_SFT                         0
815  #define ACCDET_IVAL_CUR_IN_MASK                        0x3
816  #define ACCDET_IVAL_CUR_IN_MASK_SFT                    (0x3 << 0)
817  #define ACCDET_IVAL_SAM_IN_ADDR                        \
818  	MT6359_ACCDET_CON16
819  #define ACCDET_IVAL_SAM_IN_SFT                         2
820  #define ACCDET_IVAL_SAM_IN_MASK                        0x3
821  #define ACCDET_IVAL_SAM_IN_MASK_SFT                    (0x3 << 2)
822  #define ACCDET_IVAL_MEM_IN_ADDR                        \
823  	MT6359_ACCDET_CON16
824  #define ACCDET_IVAL_MEM_IN_SFT                         4
825  #define ACCDET_IVAL_MEM_IN_MASK                        0x3
826  #define ACCDET_IVAL_MEM_IN_MASK_SFT                    (0x3 << 4)
827  #define ACCDET_EINT_IVAL_CUR_IN_ADDR                   \
828  	MT6359_ACCDET_CON16
829  #define ACCDET_EINT_IVAL_CUR_IN_SFT                    6
830  #define ACCDET_EINT_IVAL_CUR_IN_MASK                   0x3
831  #define ACCDET_EINT_IVAL_CUR_IN_MASK_SFT               (0x3 << 6)
832  #define ACCDET_EINT_IVAL_SAM_IN_ADDR                   \
833  	MT6359_ACCDET_CON16
834  #define ACCDET_EINT_IVAL_SAM_IN_SFT                    8
835  #define ACCDET_EINT_IVAL_SAM_IN_MASK                   0x3
836  #define ACCDET_EINT_IVAL_SAM_IN_MASK_SFT               (0x3 << 8)
837  #define ACCDET_EINT_IVAL_MEM_IN_ADDR                   \
838  	MT6359_ACCDET_CON16
839  #define ACCDET_EINT_IVAL_MEM_IN_SFT                    10
840  #define ACCDET_EINT_IVAL_MEM_IN_MASK                   0x3
841  #define ACCDET_EINT_IVAL_MEM_IN_MASK_SFT               (0x3 << 10)
842  #define ACCDET_IVAL_SEL_ADDR                           \
843  	MT6359_ACCDET_CON16
844  #define ACCDET_IVAL_SEL_SFT                            12
845  #define ACCDET_IVAL_SEL_MASK                           0x1
846  #define ACCDET_IVAL_SEL_MASK_SFT                       (0x1 << 12)
847  #define ACCDET_EINT_IVAL_SEL_ADDR                      \
848  	MT6359_ACCDET_CON16
849  #define ACCDET_EINT_IVAL_SEL_SFT                       13
850  #define ACCDET_EINT_IVAL_SEL_MASK                      0x1
851  #define ACCDET_EINT_IVAL_SEL_MASK_SFT                  (0x1 << 13)
852  #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_ADDR          \
853  	MT6359_ACCDET_CON17
854  #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_SFT           0
855  #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK          0x1
856  #define ACCDET_EINT_INVERTER_IVAL_CUR_IN_MASK_SFT      (0x1 << 0)
857  #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_ADDR          \
858  	MT6359_ACCDET_CON17
859  #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_SFT           1
860  #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK          0x1
861  #define ACCDET_EINT_INVERTER_IVAL_SAM_IN_MASK_SFT      (0x1 << 1)
862  #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_ADDR          \
863  	MT6359_ACCDET_CON17
864  #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_SFT           2
865  #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK          0x1
866  #define ACCDET_EINT_INVERTER_IVAL_MEM_IN_MASK_SFT      (0x1 << 2)
867  #define ACCDET_EINT_INVERTER_IVAL_SEL_ADDR             \
868  	MT6359_ACCDET_CON17
869  #define ACCDET_EINT_INVERTER_IVAL_SEL_SFT              3
870  #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK             0x1
871  #define ACCDET_EINT_INVERTER_IVAL_SEL_MASK_SFT         (0x1 << 3)
872  #define ACCDET_IRQ_ADDR                                \
873  	MT6359_ACCDET_CON18
874  #define ACCDET_IRQ_SFT                                 0
875  #define ACCDET_IRQ_MASK                                0x1
876  #define ACCDET_IRQ_MASK_SFT                            (0x1 << 0)
877  #define ACCDET_EINT0_IRQ_ADDR                          \
878  	MT6359_ACCDET_CON18
879  #define ACCDET_EINT0_IRQ_SFT                           2
880  #define ACCDET_EINT0_IRQ_MASK                          0x1
881  #define ACCDET_EINT0_IRQ_MASK_SFT                      (0x1 << 2)
882  #define ACCDET_EINT1_IRQ_ADDR                          \
883  	MT6359_ACCDET_CON18
884  #define ACCDET_EINT1_IRQ_SFT                           3
885  #define ACCDET_EINT1_IRQ_MASK                          0x1
886  #define ACCDET_EINT1_IRQ_MASK_SFT                      (0x1 << 3)
887  #define ACCDET_EINT_IN_INVERSE_ADDR                    \
888  	MT6359_ACCDET_CON18
889  #define ACCDET_EINT_IN_INVERSE_SFT                     4
890  #define ACCDET_EINT_IN_INVERSE_MASK                    0x1
891  #define ACCDET_EINT_IN_INVERSE_MASK_SFT                (0x1 << 4)
892  #define ACCDET_IRQ_CLR_ADDR                            \
893  	MT6359_ACCDET_CON18
894  #define ACCDET_IRQ_CLR_SFT                             8
895  #define ACCDET_IRQ_CLR_MASK                            0x1
896  #define ACCDET_IRQ_CLR_MASK_SFT                        (0x1 << 8)
897  #define ACCDET_EINT0_IRQ_CLR_ADDR                      \
898  	MT6359_ACCDET_CON18
899  #define ACCDET_EINT0_IRQ_CLR_SFT                       10
900  #define ACCDET_EINT0_IRQ_CLR_MASK                      0x1
901  #define ACCDET_EINT0_IRQ_CLR_MASK_SFT                  (0x1 << 10)
902  #define ACCDET_EINT1_IRQ_CLR_ADDR                      \
903  	MT6359_ACCDET_CON18
904  #define ACCDET_EINT1_IRQ_CLR_SFT                       11
905  #define ACCDET_EINT1_IRQ_CLR_MASK                      0x1
906  #define ACCDET_EINT1_IRQ_CLR_MASK_SFT                  (0x1 << 11)
907  #define ACCDET_EINT_M_PLUG_IN_NUM_ADDR                 \
908  	MT6359_ACCDET_CON18
909  #define ACCDET_EINT_M_PLUG_IN_NUM_SFT                  12
910  #define ACCDET_EINT_M_PLUG_IN_NUM_MASK                 0x7
911  #define ACCDET_EINT_M_PLUG_IN_NUM_MASK_SFT             (0x7 << 12)
912  #define ACCDET_DA_STABLE_ADDR                          \
913  	MT6359_ACCDET_CON19
914  #define ACCDET_DA_STABLE_SFT                           0
915  #define ACCDET_DA_STABLE_MASK                          0x1
916  #define ACCDET_DA_STABLE_MASK_SFT                      (0x1 << 0)
917  #define ACCDET_EINT0_EN_STABLE_ADDR                    \
918  	MT6359_ACCDET_CON19
919  #define ACCDET_EINT0_EN_STABLE_SFT                     1
920  #define ACCDET_EINT0_EN_STABLE_MASK                    0x1
921  #define ACCDET_EINT0_EN_STABLE_MASK_SFT                (0x1 << 1)
922  #define ACCDET_EINT0_CMPEN_STABLE_ADDR                 \
923  	MT6359_ACCDET_CON19
924  #define ACCDET_EINT0_CMPEN_STABLE_SFT                  2
925  #define ACCDET_EINT0_CMPEN_STABLE_MASK                 0x1
926  #define ACCDET_EINT0_CMPEN_STABLE_MASK_SFT             (0x1 << 2)
927  #define ACCDET_EINT0_CMPMEN_STABLE_ADDR                \
928  	MT6359_ACCDET_CON19
929  #define ACCDET_EINT0_CMPMEN_STABLE_SFT                 3
930  #define ACCDET_EINT0_CMPMEN_STABLE_MASK                0x1
931  #define ACCDET_EINT0_CMPMEN_STABLE_MASK_SFT            (0x1 << 3)
932  #define ACCDET_EINT0_CTURBO_STABLE_ADDR                \
933  	MT6359_ACCDET_CON19
934  #define ACCDET_EINT0_CTURBO_STABLE_SFT                 4
935  #define ACCDET_EINT0_CTURBO_STABLE_MASK                0x1
936  #define ACCDET_EINT0_CTURBO_STABLE_MASK_SFT            (0x1 << 4)
937  #define ACCDET_EINT0_CEN_STABLE_ADDR                   \
938  	MT6359_ACCDET_CON19
939  #define ACCDET_EINT0_CEN_STABLE_SFT                    5
940  #define ACCDET_EINT0_CEN_STABLE_MASK                   0x1
941  #define ACCDET_EINT0_CEN_STABLE_MASK_SFT               (0x1 << 5)
942  #define ACCDET_EINT1_EN_STABLE_ADDR                    \
943  	MT6359_ACCDET_CON19
944  #define ACCDET_EINT1_EN_STABLE_SFT                     6
945  #define ACCDET_EINT1_EN_STABLE_MASK                    0x1
946  #define ACCDET_EINT1_EN_STABLE_MASK_SFT                (0x1 << 6)
947  #define ACCDET_EINT1_CMPEN_STABLE_ADDR                 \
948  	MT6359_ACCDET_CON19
949  #define ACCDET_EINT1_CMPEN_STABLE_SFT                  7
950  #define ACCDET_EINT1_CMPEN_STABLE_MASK                 0x1
951  #define ACCDET_EINT1_CMPEN_STABLE_MASK_SFT             (0x1 << 7)
952  #define ACCDET_EINT1_CMPMEN_STABLE_ADDR                \
953  	MT6359_ACCDET_CON19
954  #define ACCDET_EINT1_CMPMEN_STABLE_SFT                 8
955  #define ACCDET_EINT1_CMPMEN_STABLE_MASK                0x1
956  #define ACCDET_EINT1_CMPMEN_STABLE_MASK_SFT            (0x1 << 8)
957  #define ACCDET_EINT1_CTURBO_STABLE_ADDR                \
958  	MT6359_ACCDET_CON19
959  #define ACCDET_EINT1_CTURBO_STABLE_SFT                 9
960  #define ACCDET_EINT1_CTURBO_STABLE_MASK                0x1
961  #define ACCDET_EINT1_CTURBO_STABLE_MASK_SFT            (0x1 << 9)
962  #define ACCDET_EINT1_CEN_STABLE_ADDR                   \
963  	MT6359_ACCDET_CON19
964  #define ACCDET_EINT1_CEN_STABLE_SFT                    10
965  #define ACCDET_EINT1_CEN_STABLE_MASK                   0x1
966  #define ACCDET_EINT1_CEN_STABLE_MASK_SFT               (0x1 << 10)
967  #define ACCDET_HWMODE_EN_ADDR                          \
968  	MT6359_ACCDET_CON20
969  #define ACCDET_HWMODE_EN_SFT                           0
970  #define ACCDET_HWMODE_EN_MASK                          0x1
971  #define ACCDET_HWMODE_EN_MASK_SFT                      (0x1 << 0)
972  #define ACCDET_HWMODE_SEL_ADDR                         \
973  	MT6359_ACCDET_CON20
974  #define ACCDET_HWMODE_SEL_SFT                          1
975  #define ACCDET_HWMODE_SEL_MASK                         0x3
976  #define ACCDET_HWMODE_SEL_MASK_SFT                     (0x3 << 1)
977  #define ACCDET_PLUG_OUT_DETECT_ADDR                    \
978  	MT6359_ACCDET_CON20
979  #define ACCDET_PLUG_OUT_DETECT_SFT                     3
980  #define ACCDET_PLUG_OUT_DETECT_MASK                    0x1
981  #define ACCDET_PLUG_OUT_DETECT_MASK_SFT                (0x1 << 3)
982  #define ACCDET_EINT0_REVERSE_ADDR                      \
983  	MT6359_ACCDET_CON20
984  #define ACCDET_EINT0_REVERSE_SFT                       4
985  #define ACCDET_EINT0_REVERSE_MASK                      0x1
986  #define ACCDET_EINT0_REVERSE_MASK_SFT                  (0x1 << 4)
987  #define ACCDET_EINT1_REVERSE_ADDR                      \
988  	MT6359_ACCDET_CON20
989  #define ACCDET_EINT1_REVERSE_SFT                       5
990  #define ACCDET_EINT1_REVERSE_MASK                      0x1
991  #define ACCDET_EINT1_REVERSE_MASK_SFT                  (0x1 << 5)
992  #define ACCDET_EINT_HWMODE_EN_ADDR                     \
993  	MT6359_ACCDET_CON20
994  #define ACCDET_EINT_HWMODE_EN_SFT                      8
995  #define ACCDET_EINT_HWMODE_EN_MASK                     0x1
996  #define ACCDET_EINT_HWMODE_EN_MASK_SFT                 (0x1 << 8)
997  #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_ADDR           \
998  	MT6359_ACCDET_CON20
999  #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_SFT            9
1000  #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK           0x1
1001  #define ACCDET_EINT_PLUG_OUT_BYPASS_DEB_MASK_SFT       (0x1 << 9)
1002  #define ACCDET_EINT_M_PLUG_IN_EN_ADDR                  \
1003  	MT6359_ACCDET_CON20
1004  #define ACCDET_EINT_M_PLUG_IN_EN_SFT                   10
1005  #define ACCDET_EINT_M_PLUG_IN_EN_MASK                  0x1
1006  #define ACCDET_EINT_M_PLUG_IN_EN_MASK_SFT              (0x1 << 10)
1007  #define ACCDET_EINT_M_HWMODE_EN_ADDR                   \
1008  	MT6359_ACCDET_CON20
1009  #define ACCDET_EINT_M_HWMODE_EN_SFT                    11
1010  #define ACCDET_EINT_M_HWMODE_EN_MASK                   0x1
1011  #define ACCDET_EINT_M_HWMODE_EN_MASK_SFT               (0x1 << 11)
1012  #define ACCDET_TEST_CMPEN_ADDR                         \
1013  	MT6359_ACCDET_CON21
1014  #define ACCDET_TEST_CMPEN_SFT                          0
1015  #define ACCDET_TEST_CMPEN_MASK                         0x1
1016  #define ACCDET_TEST_CMPEN_MASK_SFT                     (0x1 << 0)
1017  #define ACCDET_TEST_VTHEN_ADDR                         \
1018  	MT6359_ACCDET_CON21
1019  #define ACCDET_TEST_VTHEN_SFT                          1
1020  #define ACCDET_TEST_VTHEN_MASK                         0x1
1021  #define ACCDET_TEST_VTHEN_MASK_SFT                     (0x1 << 1)
1022  #define ACCDET_TEST_MBIASEN_ADDR                       \
1023  	MT6359_ACCDET_CON21
1024  #define ACCDET_TEST_MBIASEN_SFT                        2
1025  #define ACCDET_TEST_MBIASEN_MASK                       0x1
1026  #define ACCDET_TEST_MBIASEN_MASK_SFT                   (0x1 << 2)
1027  #define ACCDET_EINT_TEST_EN_ADDR                       \
1028  	MT6359_ACCDET_CON21
1029  #define ACCDET_EINT_TEST_EN_SFT                        3
1030  #define ACCDET_EINT_TEST_EN_MASK                       0x1
1031  #define ACCDET_EINT_TEST_EN_MASK_SFT                   (0x1 << 3)
1032  #define ACCDET_EINT_TEST_INVEN_ADDR                    \
1033  	MT6359_ACCDET_CON21
1034  #define ACCDET_EINT_TEST_INVEN_SFT                     4
1035  #define ACCDET_EINT_TEST_INVEN_MASK                    0x1
1036  #define ACCDET_EINT_TEST_INVEN_MASK_SFT                (0x1 << 4)
1037  #define ACCDET_EINT_TEST_CMPEN_ADDR                    \
1038  	MT6359_ACCDET_CON21
1039  #define ACCDET_EINT_TEST_CMPEN_SFT                     5
1040  #define ACCDET_EINT_TEST_CMPEN_MASK                    0x1
1041  #define ACCDET_EINT_TEST_CMPEN_MASK_SFT                (0x1 << 5)
1042  #define ACCDET_EINT_TEST_CMPMEN_ADDR                   \
1043  	MT6359_ACCDET_CON21
1044  #define ACCDET_EINT_TEST_CMPMEN_SFT                    6
1045  #define ACCDET_EINT_TEST_CMPMEN_MASK                   0x1
1046  #define ACCDET_EINT_TEST_CMPMEN_MASK_SFT               (0x1 << 6)
1047  #define ACCDET_EINT_TEST_CTURBO_ADDR                   \
1048  	MT6359_ACCDET_CON21
1049  #define ACCDET_EINT_TEST_CTURBO_SFT                    7
1050  #define ACCDET_EINT_TEST_CTURBO_MASK                   0x1
1051  #define ACCDET_EINT_TEST_CTURBO_MASK_SFT               (0x1 << 7)
1052  #define ACCDET_EINT_TEST_CEN_ADDR                      \
1053  	MT6359_ACCDET_CON21
1054  #define ACCDET_EINT_TEST_CEN_SFT                       8
1055  #define ACCDET_EINT_TEST_CEN_MASK                      0x1
1056  #define ACCDET_EINT_TEST_CEN_MASK_SFT                  (0x1 << 8)
1057  #define ACCDET_TEST_B_ADDR                             \
1058  	MT6359_ACCDET_CON21
1059  #define ACCDET_TEST_B_SFT                              9
1060  #define ACCDET_TEST_B_MASK                             0x1
1061  #define ACCDET_TEST_B_MASK_SFT                         (0x1 << 9)
1062  #define ACCDET_TEST_A_ADDR                             \
1063  	MT6359_ACCDET_CON21
1064  #define ACCDET_TEST_A_SFT                              10
1065  #define ACCDET_TEST_A_MASK                             0x1
1066  #define ACCDET_TEST_A_MASK_SFT                         (0x1 << 10)
1067  #define ACCDET_EINT_TEST_CMPOUT_ADDR                   \
1068  	MT6359_ACCDET_CON21
1069  #define ACCDET_EINT_TEST_CMPOUT_SFT                    11
1070  #define ACCDET_EINT_TEST_CMPOUT_MASK                   0x1
1071  #define ACCDET_EINT_TEST_CMPOUT_MASK_SFT               (0x1 << 11)
1072  #define ACCDET_EINT_TEST_CMPMOUT_ADDR                  \
1073  	MT6359_ACCDET_CON21
1074  #define ACCDET_EINT_TEST_CMPMOUT_SFT                   12
1075  #define ACCDET_EINT_TEST_CMPMOUT_MASK                  0x1
1076  #define ACCDET_EINT_TEST_CMPMOUT_MASK_SFT              (0x1 << 12)
1077  #define ACCDET_EINT_TEST_INVOUT_ADDR                   \
1078  	MT6359_ACCDET_CON21
1079  #define ACCDET_EINT_TEST_INVOUT_SFT                    13
1080  #define ACCDET_EINT_TEST_INVOUT_MASK                   0x1
1081  #define ACCDET_EINT_TEST_INVOUT_MASK_SFT               (0x1 << 13)
1082  #define ACCDET_CMPEN_SEL_ADDR                          \
1083  	MT6359_ACCDET_CON22
1084  #define ACCDET_CMPEN_SEL_SFT                           0
1085  #define ACCDET_CMPEN_SEL_MASK                          0x1
1086  #define ACCDET_CMPEN_SEL_MASK_SFT                      (0x1 << 0)
1087  #define ACCDET_VTHEN_SEL_ADDR                          \
1088  	MT6359_ACCDET_CON22
1089  #define ACCDET_VTHEN_SEL_SFT                           1
1090  #define ACCDET_VTHEN_SEL_MASK                          0x1
1091  #define ACCDET_VTHEN_SEL_MASK_SFT                      (0x1 << 1)
1092  #define ACCDET_MBIASEN_SEL_ADDR                        \
1093  	MT6359_ACCDET_CON22
1094  #define ACCDET_MBIASEN_SEL_SFT                         2
1095  #define ACCDET_MBIASEN_SEL_MASK                        0x1
1096  #define ACCDET_MBIASEN_SEL_MASK_SFT                    (0x1 << 2)
1097  #define ACCDET_EINT_EN_SEL_ADDR                        \
1098  	MT6359_ACCDET_CON22
1099  #define ACCDET_EINT_EN_SEL_SFT                         3
1100  #define ACCDET_EINT_EN_SEL_MASK                        0x1
1101  #define ACCDET_EINT_EN_SEL_MASK_SFT                    (0x1 << 3)
1102  #define ACCDET_EINT_INVEN_SEL_ADDR                     \
1103  	MT6359_ACCDET_CON22
1104  #define ACCDET_EINT_INVEN_SEL_SFT                      4
1105  #define ACCDET_EINT_INVEN_SEL_MASK                     0x1
1106  #define ACCDET_EINT_INVEN_SEL_MASK_SFT                 (0x1 << 4)
1107  #define ACCDET_EINT_CMPEN_SEL_ADDR                     \
1108  	MT6359_ACCDET_CON22
1109  #define ACCDET_EINT_CMPEN_SEL_SFT                      5
1110  #define ACCDET_EINT_CMPEN_SEL_MASK                     0x1
1111  #define ACCDET_EINT_CMPEN_SEL_MASK_SFT                 (0x1 << 5)
1112  #define ACCDET_EINT_CMPMEN_SEL_ADDR                    \
1113  	MT6359_ACCDET_CON22
1114  #define ACCDET_EINT_CMPMEN_SEL_SFT                     6
1115  #define ACCDET_EINT_CMPMEN_SEL_MASK                    0x1
1116  #define ACCDET_EINT_CMPMEN_SEL_MASK_SFT                (0x1 << 6)
1117  #define ACCDET_EINT_CTURBO_SEL_ADDR                    \
1118  	MT6359_ACCDET_CON22
1119  #define ACCDET_EINT_CTURBO_SEL_SFT                     7
1120  #define ACCDET_EINT_CTURBO_SEL_MASK                    0x1
1121  #define ACCDET_EINT_CTURBO_SEL_MASK_SFT                (0x1 << 7)
1122  #define ACCDET_B_SEL_ADDR                              \
1123  	MT6359_ACCDET_CON22
1124  #define ACCDET_B_SEL_SFT                               9
1125  #define ACCDET_B_SEL_MASK                              0x1
1126  #define ACCDET_B_SEL_MASK_SFT                          (0x1 << 9)
1127  #define ACCDET_A_SEL_ADDR                              \
1128  	MT6359_ACCDET_CON22
1129  #define ACCDET_A_SEL_SFT                               10
1130  #define ACCDET_A_SEL_MASK                              0x1
1131  #define ACCDET_A_SEL_MASK_SFT                          (0x1 << 10)
1132  #define ACCDET_EINT_CMPOUT_SEL_ADDR                    \
1133  	MT6359_ACCDET_CON22
1134  #define ACCDET_EINT_CMPOUT_SEL_SFT                     11
1135  #define ACCDET_EINT_CMPOUT_SEL_MASK                    0x1
1136  #define ACCDET_EINT_CMPOUT_SEL_MASK_SFT                (0x1 << 11)
1137  #define ACCDET_EINT_CMPMOUT_SEL_ADDR                   \
1138  	MT6359_ACCDET_CON22
1139  #define ACCDET_EINT_CMPMOUT_SEL_SFT                    12
1140  #define ACCDET_EINT_CMPMOUT_SEL_MASK                   0x1
1141  #define ACCDET_EINT_CMPMOUT_SEL_MASK_SFT               (0x1 << 12)
1142  #define ACCDET_EINT_INVOUT_SEL_ADDR                    \
1143  	MT6359_ACCDET_CON22
1144  #define ACCDET_EINT_INVOUT_SEL_SFT                     13
1145  #define ACCDET_EINT_INVOUT_SEL_MASK                    0x1
1146  #define ACCDET_EINT_INVOUT_SEL_MASK_SFT                (0x1 << 13)
1147  #define ACCDET_CMPEN_SW_ADDR                           \
1148  	MT6359_ACCDET_CON23
1149  #define ACCDET_CMPEN_SW_SFT                            0
1150  #define ACCDET_CMPEN_SW_MASK                           0x1
1151  #define ACCDET_CMPEN_SW_MASK_SFT                       (0x1 << 0)
1152  #define ACCDET_VTHEN_SW_ADDR                           \
1153  	MT6359_ACCDET_CON23
1154  #define ACCDET_VTHEN_SW_SFT                            1
1155  #define ACCDET_VTHEN_SW_MASK                           0x1
1156  #define ACCDET_VTHEN_SW_MASK_SFT                       (0x1 << 1)
1157  #define ACCDET_MBIASEN_SW_ADDR                         \
1158  	MT6359_ACCDET_CON23
1159  #define ACCDET_MBIASEN_SW_SFT                          2
1160  #define ACCDET_MBIASEN_SW_MASK                         0x1
1161  #define ACCDET_MBIASEN_SW_MASK_SFT                     (0x1 << 2)
1162  #define ACCDET_EINT0_EN_SW_ADDR                        \
1163  	MT6359_ACCDET_CON23
1164  #define ACCDET_EINT0_EN_SW_SFT                         3
1165  #define ACCDET_EINT0_EN_SW_MASK                        0x1
1166  #define ACCDET_EINT0_EN_SW_MASK_SFT                    (0x1 << 3)
1167  #define ACCDET_EINT0_INVEN_SW_ADDR                     \
1168  	MT6359_ACCDET_CON23
1169  #define ACCDET_EINT0_INVEN_SW_SFT                      4
1170  #define ACCDET_EINT0_INVEN_SW_MASK                     0x1
1171  #define ACCDET_EINT0_INVEN_SW_MASK_SFT                 (0x1 << 4)
1172  #define ACCDET_EINT0_CMPEN_SW_ADDR                     \
1173  	MT6359_ACCDET_CON23
1174  #define ACCDET_EINT0_CMPEN_SW_SFT                      5
1175  #define ACCDET_EINT0_CMPEN_SW_MASK                     0x1
1176  #define ACCDET_EINT0_CMPEN_SW_MASK_SFT                 (0x1 << 5)
1177  #define ACCDET_EINT0_CMPMEN_SW_ADDR                    \
1178  	MT6359_ACCDET_CON23
1179  #define ACCDET_EINT0_CMPMEN_SW_SFT                     6
1180  #define ACCDET_EINT0_CMPMEN_SW_MASK                    0x1
1181  #define ACCDET_EINT0_CMPMEN_SW_MASK_SFT                (0x1 << 6)
1182  #define ACCDET_EINT0_CTURBO_SW_ADDR                    \
1183  	MT6359_ACCDET_CON23
1184  #define ACCDET_EINT0_CTURBO_SW_SFT                     7
1185  #define ACCDET_EINT0_CTURBO_SW_MASK                    0x1
1186  #define ACCDET_EINT0_CTURBO_SW_MASK_SFT                (0x1 << 7)
1187  #define ACCDET_EINT1_EN_SW_ADDR                        \
1188  	MT6359_ACCDET_CON23
1189  #define ACCDET_EINT1_EN_SW_SFT                         8
1190  #define ACCDET_EINT1_EN_SW_MASK                        0x1
1191  #define ACCDET_EINT1_EN_SW_MASK_SFT                    (0x1 << 8)
1192  #define ACCDET_EINT1_INVEN_SW_ADDR                     \
1193  	MT6359_ACCDET_CON23
1194  #define ACCDET_EINT1_INVEN_SW_SFT                      9
1195  #define ACCDET_EINT1_INVEN_SW_MASK                     0x1
1196  #define ACCDET_EINT1_INVEN_SW_MASK_SFT                 (0x1 << 9)
1197  #define ACCDET_EINT1_CMPEN_SW_ADDR                     \
1198  	MT6359_ACCDET_CON23
1199  #define ACCDET_EINT1_CMPEN_SW_SFT                      10
1200  #define ACCDET_EINT1_CMPEN_SW_MASK                     0x1
1201  #define ACCDET_EINT1_CMPEN_SW_MASK_SFT                 (0x1 << 10)
1202  #define ACCDET_EINT1_CMPMEN_SW_ADDR                    \
1203  	MT6359_ACCDET_CON23
1204  #define ACCDET_EINT1_CMPMEN_SW_SFT                     11
1205  #define ACCDET_EINT1_CMPMEN_SW_MASK                    0x1
1206  #define ACCDET_EINT1_CMPMEN_SW_MASK_SFT                (0x1 << 11)
1207  #define ACCDET_EINT1_CTURBO_SW_ADDR                    \
1208  	MT6359_ACCDET_CON23
1209  #define ACCDET_EINT1_CTURBO_SW_SFT                     12
1210  #define ACCDET_EINT1_CTURBO_SW_MASK                    0x1
1211  #define ACCDET_EINT1_CTURBO_SW_MASK_SFT                (0x1 << 12)
1212  #define ACCDET_B_SW_ADDR                               \
1213  	MT6359_ACCDET_CON24
1214  #define ACCDET_B_SW_SFT                                0
1215  #define ACCDET_B_SW_MASK                               0x1
1216  #define ACCDET_B_SW_MASK_SFT                           (0x1 << 0)
1217  #define ACCDET_A_SW_ADDR                               \
1218  	MT6359_ACCDET_CON24
1219  #define ACCDET_A_SW_SFT                                1
1220  #define ACCDET_A_SW_MASK                               0x1
1221  #define ACCDET_A_SW_MASK_SFT                           (0x1 << 1)
1222  #define ACCDET_EINT0_CMPOUT_SW_ADDR                    \
1223  	MT6359_ACCDET_CON24
1224  #define ACCDET_EINT0_CMPOUT_SW_SFT                     2
1225  #define ACCDET_EINT0_CMPOUT_SW_MASK                    0x1
1226  #define ACCDET_EINT0_CMPOUT_SW_MASK_SFT                (0x1 << 2)
1227  #define ACCDET_EINT0_CMPMOUT_SW_ADDR                   \
1228  	MT6359_ACCDET_CON24
1229  #define ACCDET_EINT0_CMPMOUT_SW_SFT                    3
1230  #define ACCDET_EINT0_CMPMOUT_SW_MASK                   0x1
1231  #define ACCDET_EINT0_CMPMOUT_SW_MASK_SFT               (0x1 << 3)
1232  #define ACCDET_EINT0_INVOUT_SW_ADDR                    \
1233  	MT6359_ACCDET_CON24
1234  #define ACCDET_EINT0_INVOUT_SW_SFT                     4
1235  #define ACCDET_EINT0_INVOUT_SW_MASK                    0x1
1236  #define ACCDET_EINT0_INVOUT_SW_MASK_SFT                (0x1 << 4)
1237  #define ACCDET_EINT1_CMPOUT_SW_ADDR                    \
1238  	MT6359_ACCDET_CON24
1239  #define ACCDET_EINT1_CMPOUT_SW_SFT                     5
1240  #define ACCDET_EINT1_CMPOUT_SW_MASK                    0x1
1241  #define ACCDET_EINT1_CMPOUT_SW_MASK_SFT                (0x1 << 5)
1242  #define ACCDET_EINT1_CMPMOUT_SW_ADDR                   \
1243  	MT6359_ACCDET_CON24
1244  #define ACCDET_EINT1_CMPMOUT_SW_SFT                    6
1245  #define ACCDET_EINT1_CMPMOUT_SW_MASK                   0x1
1246  #define ACCDET_EINT1_CMPMOUT_SW_MASK_SFT               (0x1 << 6)
1247  #define ACCDET_EINT1_INVOUT_SW_ADDR                    \
1248  	MT6359_ACCDET_CON24
1249  #define ACCDET_EINT1_INVOUT_SW_SFT                     7
1250  #define ACCDET_EINT1_INVOUT_SW_MASK                    0x1
1251  #define ACCDET_EINT1_INVOUT_SW_MASK_SFT                (0x1 << 7)
1252  #define AD_AUDACCDETCMPOB_ADDR                         \
1253  	MT6359_ACCDET_CON25
1254  #define AD_AUDACCDETCMPOB_SFT                          0
1255  #define AD_AUDACCDETCMPOB_MASK                         0x1
1256  #define AD_AUDACCDETCMPOB_MASK_SFT                     (0x1 << 0)
1257  #define AD_AUDACCDETCMPOA_ADDR                         \
1258  	MT6359_ACCDET_CON25
1259  #define AD_AUDACCDETCMPOA_SFT                          1
1260  #define AD_AUDACCDETCMPOA_MASK                         0x1
1261  #define AD_AUDACCDETCMPOA_MASK_SFT                     (0x1 << 1)
1262  #define ACCDET_CUR_IN_ADDR                             \
1263  	MT6359_ACCDET_CON25
1264  #define ACCDET_CUR_IN_SFT                              2
1265  #define ACCDET_CUR_IN_MASK                             0x3
1266  #define ACCDET_CUR_IN_MASK_SFT                         (0x3 << 2)
1267  #define ACCDET_SAM_IN_ADDR                             \
1268  	MT6359_ACCDET_CON25
1269  #define ACCDET_SAM_IN_SFT                              4
1270  #define ACCDET_SAM_IN_MASK                             0x3
1271  #define ACCDET_SAM_IN_MASK_SFT                         (0x3 << 4)
1272  #define ACCDET_MEM_IN_ADDR                             \
1273  	MT6359_ACCDET_CON25
1274  #define ACCDET_MEM_IN_SFT                              6
1275  #define ACCDET_MEM_IN_MASK                             0x3
1276  #define ACCDET_MEM_IN_MASK_SFT                         (0x3 << 6)
1277  #define ACCDET_STATE_ADDR                              \
1278  	MT6359_ACCDET_CON25
1279  #define ACCDET_STATE_SFT                               8
1280  #define ACCDET_STATE_MASK                              0x7
1281  #define ACCDET_STATE_MASK_SFT                          (0x7 << 8)
1282  #define DA_AUDACCDETMBIASCLK_ADDR                      \
1283  	MT6359_ACCDET_CON25
1284  #define DA_AUDACCDETMBIASCLK_SFT                       12
1285  #define DA_AUDACCDETMBIASCLK_MASK                      0x1
1286  #define DA_AUDACCDETMBIASCLK_MASK_SFT                  (0x1 << 12)
1287  #define DA_AUDACCDETVTHCLK_ADDR                        \
1288  	MT6359_ACCDET_CON25
1289  #define DA_AUDACCDETVTHCLK_SFT                         13
1290  #define DA_AUDACCDETVTHCLK_MASK                        0x1
1291  #define DA_AUDACCDETVTHCLK_MASK_SFT                    (0x1 << 13)
1292  #define DA_AUDACCDETCMPCLK_ADDR                        \
1293  	MT6359_ACCDET_CON25
1294  #define DA_AUDACCDETCMPCLK_SFT                         14
1295  #define DA_AUDACCDETCMPCLK_MASK                        0x1
1296  #define DA_AUDACCDETCMPCLK_MASK_SFT                    (0x1 << 14)
1297  #define DA_AUDACCDETAUXADCSWCTRL_ADDR                  \
1298  	MT6359_ACCDET_CON25
1299  #define DA_AUDACCDETAUXADCSWCTRL_SFT                   15
1300  #define DA_AUDACCDETAUXADCSWCTRL_MASK                  0x1
1301  #define DA_AUDACCDETAUXADCSWCTRL_MASK_SFT              (0x1 << 15)
1302  #define AD_EINT0CMPMOUT_ADDR                           \
1303  	MT6359_ACCDET_CON26
1304  #define AD_EINT0CMPMOUT_SFT                            0
1305  #define AD_EINT0CMPMOUT_MASK                           0x1
1306  #define AD_EINT0CMPMOUT_MASK_SFT                       (0x1 << 0)
1307  #define AD_EINT0CMPOUT_ADDR                            \
1308  	MT6359_ACCDET_CON26
1309  #define AD_EINT0CMPOUT_SFT                             1
1310  #define AD_EINT0CMPOUT_MASK                            0x1
1311  #define AD_EINT0CMPOUT_MASK_SFT                        (0x1 << 1)
1312  #define ACCDET_EINT0_CUR_IN_ADDR                       \
1313  	MT6359_ACCDET_CON26
1314  #define ACCDET_EINT0_CUR_IN_SFT                        2
1315  #define ACCDET_EINT0_CUR_IN_MASK                       0x3
1316  #define ACCDET_EINT0_CUR_IN_MASK_SFT                   (0x3 << 2)
1317  #define ACCDET_EINT0_SAM_IN_ADDR                       \
1318  	MT6359_ACCDET_CON26
1319  #define ACCDET_EINT0_SAM_IN_SFT                        4
1320  #define ACCDET_EINT0_SAM_IN_MASK                       0x3
1321  #define ACCDET_EINT0_SAM_IN_MASK_SFT                   (0x3 << 4)
1322  #define ACCDET_EINT0_MEM_IN_ADDR                       \
1323  	MT6359_ACCDET_CON26
1324  #define ACCDET_EINT0_MEM_IN_SFT                        6
1325  #define ACCDET_EINT0_MEM_IN_MASK                       0x3
1326  #define ACCDET_EINT0_MEM_IN_MASK_SFT                   (0x3 << 6)
1327  #define ACCDET_EINT0_STATE_ADDR                        \
1328  	MT6359_ACCDET_CON26
1329  #define ACCDET_EINT0_STATE_SFT                         8
1330  #define ACCDET_EINT0_STATE_MASK                        0x7
1331  #define ACCDET_EINT0_STATE_MASK_SFT                    (0x7 << 8)
1332  #define DA_EINT0CMPEN_ADDR                             \
1333  	MT6359_ACCDET_CON26
1334  #define DA_EINT0CMPEN_SFT                              13
1335  #define DA_EINT0CMPEN_MASK                             0x1
1336  #define DA_EINT0CMPEN_MASK_SFT                         (0x1 << 13)
1337  #define DA_EINT0CMPMEN_ADDR                            \
1338  	MT6359_ACCDET_CON26
1339  #define DA_EINT0CMPMEN_SFT                             14
1340  #define DA_EINT0CMPMEN_MASK                            0x1
1341  #define DA_EINT0CMPMEN_MASK_SFT                        (0x1 << 14)
1342  #define DA_EINT0CTURBO_ADDR                            \
1343  	MT6359_ACCDET_CON26
1344  #define DA_EINT0CTURBO_SFT                             15
1345  #define DA_EINT0CTURBO_MASK                            0x1
1346  #define DA_EINT0CTURBO_MASK_SFT                        (0x1 << 15)
1347  #define AD_EINT1CMPMOUT_ADDR                           \
1348  	MT6359_ACCDET_CON27
1349  #define AD_EINT1CMPMOUT_SFT                            0
1350  #define AD_EINT1CMPMOUT_MASK                           0x1
1351  #define AD_EINT1CMPMOUT_MASK_SFT                       (0x1 << 0)
1352  #define AD_EINT1CMPOUT_ADDR                            \
1353  	MT6359_ACCDET_CON27
1354  #define AD_EINT1CMPOUT_SFT                             1
1355  #define AD_EINT1CMPOUT_MASK                            0x1
1356  #define AD_EINT1CMPOUT_MASK_SFT                        (0x1 << 1)
1357  #define ACCDET_EINT1_CUR_IN_ADDR                       \
1358  	MT6359_ACCDET_CON27
1359  #define ACCDET_EINT1_CUR_IN_SFT                        2
1360  #define ACCDET_EINT1_CUR_IN_MASK                       0x3
1361  #define ACCDET_EINT1_CUR_IN_MASK_SFT                   (0x3 << 2)
1362  #define ACCDET_EINT1_SAM_IN_ADDR                       \
1363  	MT6359_ACCDET_CON27
1364  #define ACCDET_EINT1_SAM_IN_SFT                        4
1365  #define ACCDET_EINT1_SAM_IN_MASK                       0x3
1366  #define ACCDET_EINT1_SAM_IN_MASK_SFT                   (0x3 << 4)
1367  #define ACCDET_EINT1_MEM_IN_ADDR                       \
1368  	MT6359_ACCDET_CON27
1369  #define ACCDET_EINT1_MEM_IN_SFT                        6
1370  #define ACCDET_EINT1_MEM_IN_MASK                       0x3
1371  #define ACCDET_EINT1_MEM_IN_MASK_SFT                   (0x3 << 6)
1372  #define ACCDET_EINT1_STATE_ADDR                        \
1373  	MT6359_ACCDET_CON27
1374  #define ACCDET_EINT1_STATE_SFT                         8
1375  #define ACCDET_EINT1_STATE_MASK                        0x7
1376  #define ACCDET_EINT1_STATE_MASK_SFT                    (0x7 << 8)
1377  #define DA_EINT1CMPEN_ADDR                             \
1378  	MT6359_ACCDET_CON27
1379  #define DA_EINT1CMPEN_SFT                              13
1380  #define DA_EINT1CMPEN_MASK                             0x1
1381  #define DA_EINT1CMPEN_MASK_SFT                         (0x1 << 13)
1382  #define DA_EINT1CMPMEN_ADDR                            \
1383  	MT6359_ACCDET_CON27
1384  #define DA_EINT1CMPMEN_SFT                             14
1385  #define DA_EINT1CMPMEN_MASK                            0x1
1386  #define DA_EINT1CMPMEN_MASK_SFT                        (0x1 << 14)
1387  #define DA_EINT1CTURBO_ADDR                            \
1388  	MT6359_ACCDET_CON27
1389  #define DA_EINT1CTURBO_SFT                             15
1390  #define DA_EINT1CTURBO_MASK                            0x1
1391  #define DA_EINT1CTURBO_MASK_SFT                        (0x1 << 15)
1392  #define AD_EINT0INVOUT_ADDR                            \
1393  	MT6359_ACCDET_CON28
1394  #define AD_EINT0INVOUT_SFT                             0
1395  #define AD_EINT0INVOUT_MASK                            0x1
1396  #define AD_EINT0INVOUT_MASK_SFT                        (0x1 << 0)
1397  #define ACCDET_EINT0_INVERTER_CUR_IN_ADDR              \
1398  	MT6359_ACCDET_CON28
1399  #define ACCDET_EINT0_INVERTER_CUR_IN_SFT               1
1400  #define ACCDET_EINT0_INVERTER_CUR_IN_MASK              0x1
1401  #define ACCDET_EINT0_INVERTER_CUR_IN_MASK_SFT          (0x1 << 1)
1402  #define ACCDET_EINT0_INVERTER_SAM_IN_ADDR              \
1403  	MT6359_ACCDET_CON28
1404  #define ACCDET_EINT0_INVERTER_SAM_IN_SFT               2
1405  #define ACCDET_EINT0_INVERTER_SAM_IN_MASK              0x1
1406  #define ACCDET_EINT0_INVERTER_SAM_IN_MASK_SFT          (0x1 << 2)
1407  #define ACCDET_EINT0_INVERTER_MEM_IN_ADDR              \
1408  	MT6359_ACCDET_CON28
1409  #define ACCDET_EINT0_INVERTER_MEM_IN_SFT               3
1410  #define ACCDET_EINT0_INVERTER_MEM_IN_MASK              0x1
1411  #define ACCDET_EINT0_INVERTER_MEM_IN_MASK_SFT          (0x1 << 3)
1412  #define ACCDET_EINT0_INVERTER_STATE_ADDR               \
1413  	MT6359_ACCDET_CON28
1414  #define ACCDET_EINT0_INVERTER_STATE_SFT                8
1415  #define ACCDET_EINT0_INVERTER_STATE_MASK               0x7
1416  #define ACCDET_EINT0_INVERTER_STATE_MASK_SFT           (0x7 << 8)
1417  #define DA_EINT0EN_ADDR                                \
1418  	MT6359_ACCDET_CON28
1419  #define DA_EINT0EN_SFT                                 12
1420  #define DA_EINT0EN_MASK                                0x1
1421  #define DA_EINT0EN_MASK_SFT                            (0x1 << 12)
1422  #define DA_EINT0INVEN_ADDR                             \
1423  	MT6359_ACCDET_CON28
1424  #define DA_EINT0INVEN_SFT                              13
1425  #define DA_EINT0INVEN_MASK                             0x1
1426  #define DA_EINT0INVEN_MASK_SFT                         (0x1 << 13)
1427  #define DA_EINT0CEN_ADDR                               \
1428  	MT6359_ACCDET_CON28
1429  #define DA_EINT0CEN_SFT                                14
1430  #define DA_EINT0CEN_MASK                               0x1
1431  #define DA_EINT0CEN_MASK_SFT                           (0x1 << 14)
1432  #define AD_EINT1INVOUT_ADDR                            \
1433  	MT6359_ACCDET_CON29
1434  #define AD_EINT1INVOUT_SFT                             0
1435  #define AD_EINT1INVOUT_MASK                            0x1
1436  #define AD_EINT1INVOUT_MASK_SFT                        (0x1 << 0)
1437  #define ACCDET_EINT1_INVERTER_CUR_IN_ADDR              \
1438  	MT6359_ACCDET_CON29
1439  #define ACCDET_EINT1_INVERTER_CUR_IN_SFT               1
1440  #define ACCDET_EINT1_INVERTER_CUR_IN_MASK              0x1
1441  #define ACCDET_EINT1_INVERTER_CUR_IN_MASK_SFT          (0x1 << 1)
1442  #define ACCDET_EINT1_INVERTER_SAM_IN_ADDR              \
1443  	MT6359_ACCDET_CON29
1444  #define ACCDET_EINT1_INVERTER_SAM_IN_SFT               2
1445  #define ACCDET_EINT1_INVERTER_SAM_IN_MASK              0x1
1446  #define ACCDET_EINT1_INVERTER_SAM_IN_MASK_SFT          (0x1 << 2)
1447  #define ACCDET_EINT1_INVERTER_MEM_IN_ADDR              \
1448  	MT6359_ACCDET_CON29
1449  #define ACCDET_EINT1_INVERTER_MEM_IN_SFT               3
1450  #define ACCDET_EINT1_INVERTER_MEM_IN_MASK              0x1
1451  #define ACCDET_EINT1_INVERTER_MEM_IN_MASK_SFT          (0x1 << 3)
1452  #define ACCDET_EINT1_INVERTER_STATE_ADDR               \
1453  	MT6359_ACCDET_CON29
1454  #define ACCDET_EINT1_INVERTER_STATE_SFT                8
1455  #define ACCDET_EINT1_INVERTER_STATE_MASK               0x7
1456  #define ACCDET_EINT1_INVERTER_STATE_MASK_SFT           (0x7 << 8)
1457  #define DA_EINT1EN_ADDR                                \
1458  	MT6359_ACCDET_CON29
1459  #define DA_EINT1EN_SFT                                 12
1460  #define DA_EINT1EN_MASK                                0x1
1461  #define DA_EINT1EN_MASK_SFT                            (0x1 << 12)
1462  #define DA_EINT1INVEN_ADDR                             \
1463  	MT6359_ACCDET_CON29
1464  #define DA_EINT1INVEN_SFT                              13
1465  #define DA_EINT1INVEN_MASK                             0x1
1466  #define DA_EINT1INVEN_MASK_SFT                         (0x1 << 13)
1467  #define DA_EINT1CEN_ADDR                               \
1468  	MT6359_ACCDET_CON29
1469  #define DA_EINT1CEN_SFT                                14
1470  #define DA_EINT1CEN_MASK                               0x1
1471  #define DA_EINT1CEN_MASK_SFT                           (0x1 << 14)
1472  #define ACCDET_EN_ADDR                                 \
1473  	MT6359_ACCDET_CON30
1474  #define ACCDET_EN_SFT                                  0
1475  #define ACCDET_EN_MASK                                 0x1
1476  #define ACCDET_EN_MASK_SFT                             (0x1 << 0)
1477  #define ACCDET_EINT0_EN_ADDR                           \
1478  	MT6359_ACCDET_CON30
1479  #define ACCDET_EINT0_EN_SFT                            1
1480  #define ACCDET_EINT0_EN_MASK                           0x1
1481  #define ACCDET_EINT0_EN_MASK_SFT                       (0x1 << 1)
1482  #define ACCDET_EINT1_EN_ADDR                           \
1483  	MT6359_ACCDET_CON30
1484  #define ACCDET_EINT1_EN_SFT                            2
1485  #define ACCDET_EINT1_EN_MASK                           0x1
1486  #define ACCDET_EINT1_EN_MASK_SFT                       (0x1 << 2)
1487  #define ACCDET_EINT0_M_EN_ADDR                         \
1488  	MT6359_ACCDET_CON30
1489  #define ACCDET_EINT0_M_EN_SFT                          3
1490  #define ACCDET_EINT0_M_EN_MASK                         0x1
1491  #define ACCDET_EINT0_M_EN_MASK_SFT                     (0x1 << 3)
1492  #define ACCDET_EINT0_DETECT_MOISTURE_ADDR              \
1493  	MT6359_ACCDET_CON30
1494  #define ACCDET_EINT0_DETECT_MOISTURE_SFT               4
1495  #define ACCDET_EINT0_DETECT_MOISTURE_MASK              0x1
1496  #define ACCDET_EINT0_DETECT_MOISTURE_MASK_SFT          (0x1 << 4)
1497  #define ACCDET_EINT0_PLUG_IN_ADDR                      \
1498  	MT6359_ACCDET_CON30
1499  #define ACCDET_EINT0_PLUG_IN_SFT                       5
1500  #define ACCDET_EINT0_PLUG_IN_MASK                      0x1
1501  #define ACCDET_EINT0_PLUG_IN_MASK_SFT                  (0x1 << 5)
1502  #define ACCDET_EINT0_M_PLUG_IN_ADDR                    \
1503  	MT6359_ACCDET_CON30
1504  #define ACCDET_EINT0_M_PLUG_IN_SFT                     6
1505  #define ACCDET_EINT0_M_PLUG_IN_MASK                    0x1
1506  #define ACCDET_EINT0_M_PLUG_IN_MASK_SFT                (0x1 << 6)
1507  #define ACCDET_EINT1_M_EN_ADDR                         \
1508  	MT6359_ACCDET_CON30
1509  #define ACCDET_EINT1_M_EN_SFT                          7
1510  #define ACCDET_EINT1_M_EN_MASK                         0x1
1511  #define ACCDET_EINT1_M_EN_MASK_SFT                     (0x1 << 7)
1512  #define ACCDET_EINT1_DETECT_MOISTURE_ADDR              \
1513  	MT6359_ACCDET_CON30
1514  #define ACCDET_EINT1_DETECT_MOISTURE_SFT               8
1515  #define ACCDET_EINT1_DETECT_MOISTURE_MASK              0x1
1516  #define ACCDET_EINT1_DETECT_MOISTURE_MASK_SFT          (0x1 << 8)
1517  #define ACCDET_EINT1_PLUG_IN_ADDR                      \
1518  	MT6359_ACCDET_CON30
1519  #define ACCDET_EINT1_PLUG_IN_SFT                       9
1520  #define ACCDET_EINT1_PLUG_IN_MASK                      0x1
1521  #define ACCDET_EINT1_PLUG_IN_MASK_SFT                  (0x1 << 9)
1522  #define ACCDET_EINT1_M_PLUG_IN_ADDR                    \
1523  	MT6359_ACCDET_CON30
1524  #define ACCDET_EINT1_M_PLUG_IN_SFT                     10
1525  #define ACCDET_EINT1_M_PLUG_IN_MASK                    0x1
1526  #define ACCDET_EINT1_M_PLUG_IN_MASK_SFT                (0x1 << 10)
1527  #define ACCDET_CUR_DEB_ADDR                            \
1528  	MT6359_ACCDET_CON31
1529  #define ACCDET_CUR_DEB_SFT                             0
1530  #define ACCDET_CUR_DEB_MASK                            0xFFFF
1531  #define ACCDET_CUR_DEB_MASK_SFT                        (0xFFFF << 0)
1532  #define ACCDET_EINT0_CUR_DEB_ADDR                      \
1533  	MT6359_ACCDET_CON32
1534  #define ACCDET_EINT0_CUR_DEB_SFT                       0
1535  #define ACCDET_EINT0_CUR_DEB_MASK                      0x7FFF
1536  #define ACCDET_EINT0_CUR_DEB_MASK_SFT                  (0x7FFF << 0)
1537  #define ACCDET_EINT1_CUR_DEB_ADDR                      \
1538  	MT6359_ACCDET_CON33
1539  #define ACCDET_EINT1_CUR_DEB_SFT                       0
1540  #define ACCDET_EINT1_CUR_DEB_MASK                      0x7FFF
1541  #define ACCDET_EINT1_CUR_DEB_MASK_SFT                  (0x7FFF << 0)
1542  #define ACCDET_EINT0_INVERTER_CUR_DEB_ADDR             \
1543  	MT6359_ACCDET_CON34
1544  #define ACCDET_EINT0_INVERTER_CUR_DEB_SFT              0
1545  #define ACCDET_EINT0_INVERTER_CUR_DEB_MASK             0x7FFF
1546  #define ACCDET_EINT0_INVERTER_CUR_DEB_MASK_SFT         (0x7FFF << 0)
1547  #define ACCDET_EINT1_INVERTER_CUR_DEB_ADDR             \
1548  	MT6359_ACCDET_CON35
1549  #define ACCDET_EINT1_INVERTER_CUR_DEB_SFT              0
1550  #define ACCDET_EINT1_INVERTER_CUR_DEB_MASK             0x7FFF
1551  #define ACCDET_EINT1_INVERTER_CUR_DEB_MASK_SFT         (0x7FFF << 0)
1552  #define AD_AUDACCDETCMPOB_MON_ADDR                     \
1553  	MT6359_ACCDET_CON36
1554  #define AD_AUDACCDETCMPOB_MON_SFT                      0
1555  #define AD_AUDACCDETCMPOB_MON_MASK                     0x1
1556  #define AD_AUDACCDETCMPOB_MON_MASK_SFT                 (0x1 << 0)
1557  #define AD_AUDACCDETCMPOA_MON_ADDR                     \
1558  	MT6359_ACCDET_CON36
1559  #define AD_AUDACCDETCMPOA_MON_SFT                      1
1560  #define AD_AUDACCDETCMPOA_MON_MASK                     0x1
1561  #define AD_AUDACCDETCMPOA_MON_MASK_SFT                 (0x1 << 1)
1562  #define AD_EINT0CMPMOUT_MON_ADDR                       \
1563  	MT6359_ACCDET_CON36
1564  #define AD_EINT0CMPMOUT_MON_SFT                        2
1565  #define AD_EINT0CMPMOUT_MON_MASK                       0x1
1566  #define AD_EINT0CMPMOUT_MON_MASK_SFT                   (0x1 << 2)
1567  #define AD_EINT0CMPOUT_MON_ADDR                        \
1568  	MT6359_ACCDET_CON36
1569  #define AD_EINT0CMPOUT_MON_SFT                         3
1570  #define AD_EINT0CMPOUT_MON_MASK                        0x1
1571  #define AD_EINT0CMPOUT_MON_MASK_SFT                    (0x1 << 3)
1572  #define AD_EINT0INVOUT_MON_ADDR                        \
1573  	MT6359_ACCDET_CON36
1574  #define AD_EINT0INVOUT_MON_SFT                         4
1575  #define AD_EINT0INVOUT_MON_MASK                        0x1
1576  #define AD_EINT0INVOUT_MON_MASK_SFT                    (0x1 << 4)
1577  #define AD_EINT1CMPMOUT_MON_ADDR                       \
1578  	MT6359_ACCDET_CON36
1579  #define AD_EINT1CMPMOUT_MON_SFT                        5
1580  #define AD_EINT1CMPMOUT_MON_MASK                       0x1
1581  #define AD_EINT1CMPMOUT_MON_MASK_SFT                   (0x1 << 5)
1582  #define AD_EINT1CMPOUT_MON_ADDR                        \
1583  	MT6359_ACCDET_CON36
1584  #define AD_EINT1CMPOUT_MON_SFT                         6
1585  #define AD_EINT1CMPOUT_MON_MASK                        0x1
1586  #define AD_EINT1CMPOUT_MON_MASK_SFT                    (0x1 << 6)
1587  #define AD_EINT1INVOUT_MON_ADDR                        \
1588  	MT6359_ACCDET_CON36
1589  #define AD_EINT1INVOUT_MON_SFT                         7
1590  #define AD_EINT1INVOUT_MON_MASK                        0x1
1591  #define AD_EINT1INVOUT_MON_MASK_SFT                    (0x1 << 7)
1592  #define DA_AUDACCDETCMPCLK_MON_ADDR                    \
1593  	MT6359_ACCDET_CON37
1594  #define DA_AUDACCDETCMPCLK_MON_SFT                     0
1595  #define DA_AUDACCDETCMPCLK_MON_MASK                    0x1
1596  #define DA_AUDACCDETCMPCLK_MON_MASK_SFT                (0x1 << 0)
1597  #define DA_AUDACCDETVTHCLK_MON_ADDR                    \
1598  	MT6359_ACCDET_CON37
1599  #define DA_AUDACCDETVTHCLK_MON_SFT                     1
1600  #define DA_AUDACCDETVTHCLK_MON_MASK                    0x1
1601  #define DA_AUDACCDETVTHCLK_MON_MASK_SFT                (0x1 << 1)
1602  #define DA_AUDACCDETMBIASCLK_MON_ADDR                  \
1603  	MT6359_ACCDET_CON37
1604  #define DA_AUDACCDETMBIASCLK_MON_SFT                   2
1605  #define DA_AUDACCDETMBIASCLK_MON_MASK                  0x1
1606  #define DA_AUDACCDETMBIASCLK_MON_MASK_SFT              (0x1 << 2)
1607  #define DA_AUDACCDETAUXADCSWCTRL_MON_ADDR              \
1608  	MT6359_ACCDET_CON37
1609  #define DA_AUDACCDETAUXADCSWCTRL_MON_SFT               3
1610  #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK              0x1
1611  #define DA_AUDACCDETAUXADCSWCTRL_MON_MASK_SFT          (0x1 << 3)
1612  #define DA_EINT0CTURBO_MON_ADDR                        \
1613  	MT6359_ACCDET_CON38
1614  #define DA_EINT0CTURBO_MON_SFT                         0
1615  #define DA_EINT0CTURBO_MON_MASK                        0x1
1616  #define DA_EINT0CTURBO_MON_MASK_SFT                    (0x1 << 0)
1617  #define DA_EINT0CMPMEN_MON_ADDR                        \
1618  	MT6359_ACCDET_CON38
1619  #define DA_EINT0CMPMEN_MON_SFT                         1
1620  #define DA_EINT0CMPMEN_MON_MASK                        0x1
1621  #define DA_EINT0CMPMEN_MON_MASK_SFT                    (0x1 << 1)
1622  #define DA_EINT0CMPEN_MON_ADDR                         \
1623  	MT6359_ACCDET_CON38
1624  #define DA_EINT0CMPEN_MON_SFT                          2
1625  #define DA_EINT0CMPEN_MON_MASK                         0x1
1626  #define DA_EINT0CMPEN_MON_MASK_SFT                     (0x1 << 2)
1627  #define DA_EINT0INVEN_MON_ADDR                         \
1628  	MT6359_ACCDET_CON38
1629  #define DA_EINT0INVEN_MON_SFT                          3
1630  #define DA_EINT0INVEN_MON_MASK                         0x1
1631  #define DA_EINT0INVEN_MON_MASK_SFT                     (0x1 << 3)
1632  #define DA_EINT0CEN_MON_ADDR                           \
1633  	MT6359_ACCDET_CON38
1634  #define DA_EINT0CEN_MON_SFT                            4
1635  #define DA_EINT0CEN_MON_MASK                           0x1
1636  #define DA_EINT0CEN_MON_MASK_SFT                       (0x1 << 4)
1637  #define DA_EINT0EN_MON_ADDR                            \
1638  	MT6359_ACCDET_CON38
1639  #define DA_EINT0EN_MON_SFT                             5
1640  #define DA_EINT0EN_MON_MASK                            0x1
1641  #define DA_EINT0EN_MON_MASK_SFT                        (0x1 << 5)
1642  #define DA_EINT1CTURBO_MON_ADDR                        \
1643  	MT6359_ACCDET_CON38
1644  #define DA_EINT1CTURBO_MON_SFT                         8
1645  #define DA_EINT1CTURBO_MON_MASK                        0x1
1646  #define DA_EINT1CTURBO_MON_MASK_SFT                    (0x1 << 8)
1647  #define DA_EINT1CMPMEN_MON_ADDR                        \
1648  	MT6359_ACCDET_CON38
1649  #define DA_EINT1CMPMEN_MON_SFT                         9
1650  #define DA_EINT1CMPMEN_MON_MASK                        0x1
1651  #define DA_EINT1CMPMEN_MON_MASK_SFT                    (0x1 << 9)
1652  #define DA_EINT1CMPEN_MON_ADDR                         \
1653  	MT6359_ACCDET_CON38
1654  #define DA_EINT1CMPEN_MON_SFT                          10
1655  #define DA_EINT1CMPEN_MON_MASK                         0x1
1656  #define DA_EINT1CMPEN_MON_MASK_SFT                     (0x1 << 10)
1657  #define DA_EINT1INVEN_MON_ADDR                         \
1658  	MT6359_ACCDET_CON38
1659  #define DA_EINT1INVEN_MON_SFT                          11
1660  #define DA_EINT1INVEN_MON_MASK                         0x1
1661  #define DA_EINT1INVEN_MON_MASK_SFT                     (0x1 << 11)
1662  #define DA_EINT1CEN_MON_ADDR                           \
1663  	MT6359_ACCDET_CON38
1664  #define DA_EINT1CEN_MON_SFT                            12
1665  #define DA_EINT1CEN_MON_MASK                           0x1
1666  #define DA_EINT1CEN_MON_MASK_SFT                       (0x1 << 12)
1667  #define DA_EINT1EN_MON_ADDR                            \
1668  	MT6359_ACCDET_CON38
1669  #define DA_EINT1EN_MON_SFT                             13
1670  #define DA_EINT1EN_MON_MASK                            0x1
1671  #define DA_EINT1EN_MON_MASK_SFT                        (0x1 << 13)
1672  #define ACCDET_EINT0_M_PLUG_IN_COUNT_ADDR              \
1673  	MT6359_ACCDET_CON39
1674  #define ACCDET_EINT0_M_PLUG_IN_COUNT_SFT               0
1675  #define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK              0x7
1676  #define ACCDET_EINT0_M_PLUG_IN_COUNT_MASK_SFT          (0x7 << 0)
1677  #define ACCDET_EINT1_M_PLUG_IN_COUNT_ADDR              \
1678  	MT6359_ACCDET_CON39
1679  #define ACCDET_EINT1_M_PLUG_IN_COUNT_SFT               4
1680  #define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK              0x7
1681  #define ACCDET_EINT1_M_PLUG_IN_COUNT_MASK_SFT          (0x7 << 4)
1682  #define ACCDET_MON_FLAG_EN_ADDR                        \
1683  	MT6359_ACCDET_CON40
1684  #define ACCDET_MON_FLAG_EN_SFT                         0
1685  #define ACCDET_MON_FLAG_EN_MASK                        0x1
1686  #define ACCDET_MON_FLAG_EN_MASK_SFT                    (0x1 << 0)
1687  #define ACCDET_MON_FLAG_SEL_ADDR                       \
1688  	MT6359_ACCDET_CON40
1689  #define ACCDET_MON_FLAG_SEL_SFT                        4
1690  #define ACCDET_MON_FLAG_SEL_MASK                       0xF
1691  #define ACCDET_MON_FLAG_SEL_MASK_SFT                   (0xF << 4)
1692  
1693  #define RG_AUDPWDBMICBIAS0_ADDR                        \
1694  	MT6359_AUDENC_ANA_CON15
1695  #define RG_AUDPWDBMICBIAS0_SFT                         0
1696  #define RG_AUDPWDBMICBIAS0_MASK                        0x1
1697  #define RG_AUDPWDBMICBIAS0_MASK_SFT                    (0x1 << 0)
1698  #define RG_AUDPREAMPLON_ADDR                           \
1699  	MT6359_AUDENC_ANA_CON0
1700  #define RG_AUDPREAMPLON_SFT                            0
1701  #define RG_AUDPREAMPLON_MASK                           0x1
1702  #define RG_AUDPREAMPLON_MASK_SFT                       (0x1 << 0)
1703  #define RG_CLKSQ_EN_ADDR                               \
1704  	MT6359_AUDENC_ANA_CON23
1705  #define RG_CLKSQ_EN_SFT                                0
1706  #define RG_CLKSQ_EN_MASK                               0x1
1707  #define RG_CLKSQ_EN_MASK_SFT                           (0x1 << 0)
1708  #define RG_RTC32K_CK_PDN_ADDR                          \
1709  	MT6359_TOP_CKPDN_CON0
1710  #define RG_RTC32K_CK_PDN_SFT                           15
1711  #define RG_RTC32K_CK_PDN_MASK                          0x1
1712  #define RG_RTC32K_CK_PDN_MASK_SFT                      (0x1 << 15)
1713  #define RG_HPLOUTPUTSTBENH_VAUDP32_ADDR                \
1714  	MT6359_AUDDEC_ANA_CON2
1715  #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT                 0
1716  #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK                0x7
1717  #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT            (0x7 << 0)
1718  #define AUXADC_RQST_CH5_ADDR                           \
1719  	MT6359_AUXADC_RQST0
1720  #define AUXADC_RQST_CH5_SFT                            5
1721  #define AUXADC_RQST_CH5_MASK                           0x1
1722  #define AUXADC_RQST_CH5_MASK_SFT                       (0x1 << 5)
1723  #define RG_LDO_VUSB_HW0_OP_EN_ADDR                     \
1724  	MT6359_LDO_VUSB_OP_EN
1725  #define RG_LDO_VUSB_HW0_OP_EN_SFT                      0
1726  #define RG_LDO_VUSB_HW0_OP_EN_MASK                     0x1
1727  #define RG_LDO_VUSB_HW0_OP_EN_MASK_SFT                 (0x1 << 0)
1728  #define RG_HPROUTPUTSTBENH_VAUDP32_ADDR                \
1729  	MT6359_AUDDEC_ANA_CON2
1730  #define RG_HPROUTPUTSTBENH_VAUDP32_SFT                 4
1731  #define RG_HPROUTPUTSTBENH_VAUDP32_MASK                0x7
1732  #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT            (0x7 << 4)
1733  #define RG_NCP_PDDIS_EN_ADDR                           \
1734  	MT6359_AFE_NCP_CFG2
1735  #define RG_NCP_PDDIS_EN_SFT                            0
1736  #define RG_NCP_PDDIS_EN_MASK                           0x1
1737  #define RG_NCP_PDDIS_EN_MASK_SFT                       (0x1 << 0)
1738  #define RG_SCK32K_CK_PDN_ADDR                          \
1739  	MT6359_TOP_CKPDN_CON0
1740  #define RG_SCK32K_CK_PDN_SFT                           0
1741  #define RG_SCK32K_CK_PDN_MASK                          0x1
1742  #define RG_SCK32K_CK_PDN_MASK_SFT                      (0x1 << 0)
1743  /* AUDENC_ANA_CON18: */
1744  #define RG_ACCDET_MODE_ANA11_MODE1	(0x000F)
1745  #define RG_ACCDET_MODE_ANA11_MODE2	(0x008F)
1746  #define RG_ACCDET_MODE_ANA11_MODE6	(0x008F)
1747  
1748  /* AUXADC_ADC5:  Auxadc CH5 read data */
1749  #define AUXADC_DATA_RDY_CH5		BIT(15)
1750  #define AUXADC_DATA_PROCEED_CH5		BIT(15)
1751  #define AUXADC_DATA_MASK		(0x0FFF)
1752  
1753  /* AUXADC_RQST0_SET:  Auxadc CH5 request, relevant 0x07EC */
1754  #define AUXADC_RQST_CH5_SET		BIT(5)
1755  /* AUXADC_RQST0_CLR:  Auxadc CH5 request, relevant 0x07EC */
1756  #define AUXADC_RQST_CH5_CLR		BIT(5)
1757  
1758  #define ACCDET_CALI_MASK0		(0xFF)
1759  #define ACCDET_CALI_MASK1		(0xFF << 8)
1760  #define ACCDET_CALI_MASK2		(0xFF)
1761  #define ACCDET_CALI_MASK3		(0xFF << 8)
1762  #define ACCDET_CALI_MASK4		(0xFF)
1763  
1764  #define ACCDET_EINT_IRQ_B2_B3		(0x03 << ACCDET_EINT0_IRQ_SFT)
1765  
1766  /* ACCDET_CON25: RO, accdet FSM state,etc.*/
1767  #define ACCDET_STATE_MEM_IN_OFFSET	(ACCDET_MEM_IN_SFT)
1768  #define ACCDET_STATE_AB_MASK		(0x03)
1769  #define ACCDET_STATE_AB_00		(0x00)
1770  #define ACCDET_STATE_AB_01		(0x01)
1771  #define ACCDET_STATE_AB_10		(0x02)
1772  #define ACCDET_STATE_AB_11		(0x03)
1773  
1774  /* ACCDET_CON19 */
1775  #define ACCDET_EINT0_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \
1776  				(ACCDET_EINT0_EN_STABLE_MASK_SFT) | \
1777  				(ACCDET_EINT0_CMPEN_STABLE_MASK_SFT) | \
1778  				(ACCDET_EINT0_CEN_STABLE_MASK_SFT))
1779  
1780  #define ACCDET_EINT1_STABLE_VAL ((ACCDET_DA_STABLE_MASK_SFT) | \
1781  				(ACCDET_EINT1_EN_STABLE_MASK_SFT) | \
1782  				(ACCDET_EINT1_CMPEN_STABLE_MASK_SFT) | \
1783  				(ACCDET_EINT1_CEN_STABLE_MASK_SFT))
1784  /* The following are used for mt6359.c */
1785  /* MT6359_DCXO_CW12 */
1786  #define RG_XO_AUDIO_EN_M_SFT				13
1787  
1788  /* AUD_TOP_CKPDN_CON0 */
1789  #define RG_VOW13M_CK_PDN_SFT				13
1790  #define RG_VOW13M_CK_PDN_MASK				0x1
1791  #define RG_VOW13M_CK_PDN_MASK_SFT			(0x1 << 13)
1792  #define RG_VOW32K_CK_PDN_SFT				12
1793  #define RG_VOW32K_CK_PDN_MASK				0x1
1794  #define RG_VOW32K_CK_PDN_MASK_SFT			(0x1 << 12)
1795  #define RG_AUD_INTRP_CK_PDN_SFT				8
1796  #define RG_AUD_INTRP_CK_PDN_MASK			0x1
1797  #define RG_AUD_INTRP_CK_PDN_MASK_SFT			(0x1 << 8)
1798  #define RG_PAD_AUD_CLK_MISO_CK_PDN_SFT			7
1799  #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK			0x1
1800  #define RG_PAD_AUD_CLK_MISO_CK_PDN_MASK_SFT		(0x1 << 7)
1801  #define RG_AUDNCP_CK_PDN_SFT				6
1802  #define RG_AUDNCP_CK_PDN_MASK				0x1
1803  #define RG_AUDNCP_CK_PDN_MASK_SFT			(0x1 << 6)
1804  #define RG_ZCD13M_CK_PDN_SFT				5
1805  #define RG_ZCD13M_CK_PDN_MASK				0x1
1806  #define RG_ZCD13M_CK_PDN_MASK_SFT			(0x1 << 5)
1807  #define RG_AUDIF_CK_PDN_SFT				2
1808  #define RG_AUDIF_CK_PDN_MASK				0x1
1809  #define RG_AUDIF_CK_PDN_MASK_SFT			(0x1 << 2)
1810  #define RG_AUD_CK_PDN_SFT				1
1811  #define RG_AUD_CK_PDN_MASK				0x1
1812  #define RG_AUD_CK_PDN_MASK_SFT				(0x1 << 1)
1813  #define RG_ACCDET_CK_PDN_SFT				0
1814  #define RG_ACCDET_CK_PDN_MASK				0x1
1815  #define RG_ACCDET_CK_PDN_MASK_SFT			(0x1 << 0)
1816  
1817  /* AUD_TOP_CKPDN_CON0_SET */
1818  #define RG_AUD_TOP_CKPDN_CON0_SET_SFT			0
1819  #define RG_AUD_TOP_CKPDN_CON0_SET_MASK			0x3fff
1820  #define RG_AUD_TOP_CKPDN_CON0_SET_MASK_SFT		(0x3fff << 0)
1821  
1822  /* AUD_TOP_CKPDN_CON0_CLR */
1823  #define RG_AUD_TOP_CKPDN_CON0_CLR_SFT			0
1824  #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK			0x3fff
1825  #define RG_AUD_TOP_CKPDN_CON0_CLR_MASK_SFT		(0x3fff << 0)
1826  
1827  /* AUD_TOP_CKSEL_CON0 */
1828  #define RG_AUDIF_CK_CKSEL_SFT				3
1829  #define RG_AUDIF_CK_CKSEL_MASK				0x1
1830  #define RG_AUDIF_CK_CKSEL_MASK_SFT			(0x1 << 3)
1831  #define RG_AUD_CK_CKSEL_SFT				2
1832  #define RG_AUD_CK_CKSEL_MASK				0x1
1833  #define RG_AUD_CK_CKSEL_MASK_SFT			(0x1 << 2)
1834  
1835  /* AUD_TOP_CKSEL_CON0_SET */
1836  #define RG_AUD_TOP_CKSEL_CON0_SET_SFT			0
1837  #define RG_AUD_TOP_CKSEL_CON0_SET_MASK			0xf
1838  #define RG_AUD_TOP_CKSEL_CON0_SET_MASK_SFT		(0xf << 0)
1839  
1840  /* AUD_TOP_CKSEL_CON0_CLR */
1841  #define RG_AUD_TOP_CKSEL_CON0_CLR_SFT			0
1842  #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK			0xf
1843  #define RG_AUD_TOP_CKSEL_CON0_CLR_MASK_SFT		(0xf << 0)
1844  
1845  /* AUD_TOP_CKTST_CON0 */
1846  #define RG_VOW13M_CK_TSTSEL_SFT				9
1847  #define RG_VOW13M_CK_TSTSEL_MASK			0x1
1848  #define RG_VOW13M_CK_TSTSEL_MASK_SFT			(0x1 << 9)
1849  #define RG_VOW13M_CK_TST_DIS_SFT			8
1850  #define RG_VOW13M_CK_TST_DIS_MASK			0x1
1851  #define RG_VOW13M_CK_TST_DIS_MASK_SFT			(0x1 << 8)
1852  #define RG_AUD26M_CK_TSTSEL_SFT				4
1853  #define RG_AUD26M_CK_TSTSEL_MASK			0x1
1854  #define RG_AUD26M_CK_TSTSEL_MASK_SFT			(0x1 << 4)
1855  #define RG_AUDIF_CK_TSTSEL_SFT				3
1856  #define RG_AUDIF_CK_TSTSEL_MASK				0x1
1857  #define RG_AUDIF_CK_TSTSEL_MASK_SFT			(0x1 << 3)
1858  #define RG_AUD_CK_TSTSEL_SFT				2
1859  #define RG_AUD_CK_TSTSEL_MASK				0x1
1860  #define RG_AUD_CK_TSTSEL_MASK_SFT			(0x1 << 2)
1861  #define RG_AUD26M_CK_TST_DIS_SFT			0
1862  #define RG_AUD26M_CK_TST_DIS_MASK			0x1
1863  #define RG_AUD26M_CK_TST_DIS_MASK_SFT			(0x1 << 0)
1864  
1865  /* AUD_TOP_CLK_HWEN_CON0 */
1866  #define RG_AUD_INTRP_CK_PDN_HWEN_SFT			0
1867  #define RG_AUD_INTRP_CK_PDN_HWEN_MASK			0x1
1868  #define RG_AUD_INTRP_CK_PDN_HWEN_MASK_SFT		(0x1 << 0)
1869  
1870  /* AUD_TOP_CLK_HWEN_CON0_SET */
1871  #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_SFT		0
1872  #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK		0xffff
1873  #define RG_AUD_INTRP_CK_PND_HWEN_CON0_SET_MASK_SFT	(0xffff << 0)
1874  
1875  /* AUD_TOP_CLK_HWEN_CON0_CLR */
1876  #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_SFT		0
1877  #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK		0xffff
1878  #define RG_AUD_INTRP_CLK_PDN_HWEN_CON0_CLR_MASK_SFT	(0xffff << 0)
1879  
1880  /* AUD_TOP_RST_CON0 */
1881  #define RG_AUDNCP_RST_SFT				3
1882  #define RG_AUDNCP_RST_MASK				0x1
1883  #define RG_AUDNCP_RST_MASK_SFT				(0x1 << 3)
1884  #define RG_ZCD_RST_SFT					2
1885  #define RG_ZCD_RST_MASK					0x1
1886  #define RG_ZCD_RST_MASK_SFT				(0x1 << 2)
1887  #define RG_ACCDET_RST_SFT				1
1888  #define RG_ACCDET_RST_MASK				0x1
1889  #define RG_ACCDET_RST_MASK_SFT				(0x1 << 1)
1890  #define RG_AUDIO_RST_SFT				0
1891  #define RG_AUDIO_RST_MASK				0x1
1892  #define RG_AUDIO_RST_MASK_SFT				(0x1 << 0)
1893  
1894  /* AUD_TOP_RST_CON0_SET */
1895  #define RG_AUD_TOP_RST_CON0_SET_SFT			0
1896  #define RG_AUD_TOP_RST_CON0_SET_MASK			0xf
1897  #define RG_AUD_TOP_RST_CON0_SET_MASK_SFT		(0xf << 0)
1898  
1899  /* AUD_TOP_RST_CON0_CLR */
1900  #define RG_AUD_TOP_RST_CON0_CLR_SFT			0
1901  #define RG_AUD_TOP_RST_CON0_CLR_MASK			0xf
1902  #define RG_AUD_TOP_RST_CON0_CLR_MASK_SFT		(0xf << 0)
1903  
1904  /* AUD_TOP_RST_BANK_CON0 */
1905  #define BANK_AUDZCD_SWRST_SFT				2
1906  #define BANK_AUDZCD_SWRST_MASK				0x1
1907  #define BANK_AUDZCD_SWRST_MASK_SFT			(0x1 << 2)
1908  #define BANK_AUDIO_SWRST_SFT				1
1909  #define BANK_AUDIO_SWRST_MASK				0x1
1910  #define BANK_AUDIO_SWRST_MASK_SFT			(0x1 << 1)
1911  #define BANK_ACCDET_SWRST_SFT				0
1912  #define BANK_ACCDET_SWRST_MASK				0x1
1913  #define BANK_ACCDET_SWRST_MASK_SFT			(0x1 << 0)
1914  
1915  /* AFE_UL_DL_CON0 */
1916  #define AFE_UL_LR_SWAP_SFT				15
1917  #define AFE_UL_LR_SWAP_MASK				0x1
1918  #define AFE_UL_LR_SWAP_MASK_SFT				(0x1 << 15)
1919  #define AFE_DL_LR_SWAP_SFT				14
1920  #define AFE_DL_LR_SWAP_MASK				0x1
1921  #define AFE_DL_LR_SWAP_MASK_SFT				(0x1 << 14)
1922  #define AFE_ON_SFT					0
1923  #define AFE_ON_MASK					0x1
1924  #define AFE_ON_MASK_SFT					(0x1 << 0)
1925  
1926  /* AFE_DL_SRC2_CON0_L */
1927  #define DL_2_SRC_ON_TMP_CTL_PRE_SFT			0
1928  #define DL_2_SRC_ON_TMP_CTL_PRE_MASK			0x1
1929  #define DL_2_SRC_ON_TMP_CTL_PRE_MASK_SFT		(0x1 << 0)
1930  
1931  /* AFE_UL_SRC_CON0_H */
1932  #define C_DIGMIC_PHASE_SEL_CH1_CTL_SFT			11
1933  #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK			0x7
1934  #define C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT		(0x7 << 11)
1935  #define C_DIGMIC_PHASE_SEL_CH2_CTL_SFT			8
1936  #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK			0x7
1937  #define C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT		(0x7 << 8)
1938  #define C_TWO_DIGITAL_MIC_CTL_SFT			7
1939  #define C_TWO_DIGITAL_MIC_CTL_MASK			0x1
1940  #define C_TWO_DIGITAL_MIC_CTL_MASK_SFT			(0x1 << 7)
1941  
1942  /* AFE_UL_SRC_CON0_L */
1943  #define DMIC_LOW_POWER_MODE_CTL_SFT			14
1944  #define DMIC_LOW_POWER_MODE_CTL_MASK			0x3
1945  #define DMIC_LOW_POWER_MODE_CTL_MASK_SFT		(0x3 << 14)
1946  #define DIGMIC_4P33M_SEL_CTL_SFT			6
1947  #define DIGMIC_4P33M_SEL_CTL_MASK			0x1
1948  #define DIGMIC_4P33M_SEL_CTL_MASK_SFT			(0x1 << 6)
1949  #define DIGMIC_3P25M_1P625M_SEL_CTL_SFT			5
1950  #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK		0x1
1951  #define DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT		(0x1 << 5)
1952  #define UL_LOOP_BACK_MODE_CTL_SFT			2
1953  #define UL_LOOP_BACK_MODE_CTL_MASK			0x1
1954  #define UL_LOOP_BACK_MODE_CTL_MASK_SFT			(0x1 << 2)
1955  #define UL_SDM_3_LEVEL_CTL_SFT				1
1956  #define UL_SDM_3_LEVEL_CTL_MASK				0x1
1957  #define UL_SDM_3_LEVEL_CTL_MASK_SFT			(0x1 << 1)
1958  #define UL_SRC_ON_TMP_CTL_SFT				0
1959  #define UL_SRC_ON_TMP_CTL_MASK				0x1
1960  #define UL_SRC_ON_TMP_CTL_MASK_SFT			(0x1 << 0)
1961  
1962  /* AFE_ADDA6_L_SRC_CON0_H */
1963  #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_SFT		11
1964  #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK		0x7
1965  #define ADDA6_C_DIGMIC_PHASE_SEL_CH1_CTL_MASK_SFT	(0x7 << 11)
1966  #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_SFT		8
1967  #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK		0x7
1968  #define ADDA6_C_DIGMIC_PHASE_SEL_CH2_CTL_MASK_SFT	(0x7 << 8)
1969  #define ADDA6_C_TWO_DIGITAL_MIC_CTL_SFT			7
1970  #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK		0x1
1971  #define ADDA6_C_TWO_DIGITAL_MIC_CTL_MASK_SFT		(0x1 << 7)
1972  
1973  /* AFE_ADDA6_UL_SRC_CON0_L */
1974  #define ADDA6_DMIC_LOW_POWER_MODE_CTL_SFT		14
1975  #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK		0x3
1976  #define ADDA6_DMIC_LOW_POWER_MODE_CTL_MASK_SFT		(0x3 << 14)
1977  #define ADDA6_DIGMIC_4P33M_SEL_CTL_SFT			6
1978  #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK			0x1
1979  #define ADDA6_DIGMIC_4P33M_SEL_CTL_MASK_SFT		(0x1 << 6)
1980  #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_SFT		5
1981  #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK		0x1
1982  #define ADDA6_DIGMIC_3P25M_1P625M_SEL_CTL_MASK_SFT	(0x1 << 5)
1983  #define ADDA6_UL_LOOP_BACK_MODE_CTL_SFT			2
1984  #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK		0x1
1985  #define ADDA6_UL_LOOP_BACK_MODE_CTL_MASK_SFT		(0x1 << 2)
1986  #define ADDA6_UL_SDM_3_LEVEL_CTL_SFT			1
1987  #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK			0x1
1988  #define ADDA6_UL_SDM_3_LEVEL_CTL_MASK_SFT		(0x1 << 1)
1989  #define ADDA6_UL_SRC_ON_TMP_CTL_SFT			0
1990  #define ADDA6_UL_SRC_ON_TMP_CTL_MASK			0x1
1991  #define ADDA6_UL_SRC_ON_TMP_CTL_MASK_SFT		(0x1 << 0)
1992  
1993  /* AFE_TOP_CON0 */
1994  #define ADDA6_MTKAIF_SINE_ON_SFT			4
1995  #define ADDA6_MTKAIF_SINE_ON_MASK			0x1
1996  #define ADDA6_MTKAIF_SINE_ON_MASK_SFT			(0x1 << 4)
1997  #define ADDA6_UL_SINE_ON_SFT				3
1998  #define ADDA6_UL_SINE_ON_MASK				0x1
1999  #define ADDA6_UL_SINE_ON_MASK_SFT			(0x1 << 3)
2000  #define MTKAIF_SINE_ON_SFT				2
2001  #define MTKAIF_SINE_ON_MASK				0x1
2002  #define MTKAIF_SINE_ON_MASK_SFT				(0x1 << 2)
2003  #define UL_SINE_ON_SFT					1
2004  #define UL_SINE_ON_MASK					0x1
2005  #define UL_SINE_ON_MASK_SFT				(0x1 << 1)
2006  #define DL_SINE_ON_SFT					0
2007  #define DL_SINE_ON_MASK					0x1
2008  #define DL_SINE_ON_MASK_SFT				(0x1 << 0)
2009  
2010  /* AUDIO_TOP_CON0 */
2011  #define PDN_AFE_CTL_SFT					7
2012  #define PDN_AFE_CTL_MASK				0x1
2013  #define PDN_AFE_CTL_MASK_SFT				(0x1 << 7)
2014  #define PDN_DAC_CTL_SFT					6
2015  #define PDN_DAC_CTL_MASK				0x1
2016  #define PDN_DAC_CTL_MASK_SFT				(0x1 << 6)
2017  #define PDN_ADC_CTL_SFT					5
2018  #define PDN_ADC_CTL_MASK				0x1
2019  #define PDN_ADC_CTL_MASK_SFT				(0x1 << 5)
2020  #define PDN_ADDA6_ADC_CTL_SFT				4
2021  #define PDN_ADDA6_ADC_CTL_MASK				0x1
2022  #define PDN_ADDA6_ADC_CTL_MASK_SFT			(0x1 << 4)
2023  #define PDN_I2S_DL_CTL_SFT				3
2024  #define PDN_I2S_DL_CTL_MASK				0x1
2025  #define PDN_I2S_DL_CTL_MASK_SFT				(0x1 << 3)
2026  #define PWR_CLK_DIS_CTL_SFT				2
2027  #define PWR_CLK_DIS_CTL_MASK				0x1
2028  #define PWR_CLK_DIS_CTL_MASK_SFT			(0x1 << 2)
2029  #define PDN_AFE_TESTMODEL_CTL_SFT			1
2030  #define PDN_AFE_TESTMODEL_CTL_MASK			0x1
2031  #define PDN_AFE_TESTMODEL_CTL_MASK_SFT			(0x1 << 1)
2032  #define PDN_RESERVED_SFT				0
2033  #define PDN_RESERVED_MASK				0x1
2034  #define PDN_RESERVED_MASK_SFT				(0x1 << 0)
2035  
2036  /* AFE_MON_DEBUG0 */
2037  #define AUDIO_SYS_TOP_MON_SWAP_SFT			14
2038  #define AUDIO_SYS_TOP_MON_SWAP_MASK			0x3
2039  #define AUDIO_SYS_TOP_MON_SWAP_MASK_SFT			(0x3 << 14)
2040  #define AUDIO_SYS_TOP_MON_SEL_SFT			8
2041  #define AUDIO_SYS_TOP_MON_SEL_MASK			0x1f
2042  #define AUDIO_SYS_TOP_MON_SEL_MASK_SFT			(0x1f << 8)
2043  #define AFE_MON_SEL_SFT					0
2044  #define AFE_MON_SEL_MASK				0xff
2045  #define AFE_MON_SEL_MASK_SFT				(0xff << 0)
2046  
2047  /* AFUNC_AUD_CON0 */
2048  #define CCI_AUD_ANACK_SEL_SFT				15
2049  #define CCI_AUD_ANACK_SEL_MASK				0x1
2050  #define CCI_AUD_ANACK_SEL_MASK_SFT			(0x1 << 15)
2051  #define CCI_AUDIO_FIFO_WPTR_SFT				12
2052  #define CCI_AUDIO_FIFO_WPTR_MASK			0x7
2053  #define CCI_AUDIO_FIFO_WPTR_MASK_SFT			(0x7 << 12)
2054  #define CCI_SCRAMBLER_CG_EN_SFT				11
2055  #define CCI_SCRAMBLER_CG_EN_MASK			0x1
2056  #define CCI_SCRAMBLER_CG_EN_MASK_SFT			(0x1 << 11)
2057  #define CCI_LCH_INV_SFT					10
2058  #define CCI_LCH_INV_MASK				0x1
2059  #define CCI_LCH_INV_MASK_SFT				(0x1 << 10)
2060  #define CCI_RAND_EN_SFT					9
2061  #define CCI_RAND_EN_MASK				0x1
2062  #define CCI_RAND_EN_MASK_SFT				(0x1 << 9)
2063  #define CCI_SPLT_SCRMB_CLK_ON_SFT			8
2064  #define CCI_SPLT_SCRMB_CLK_ON_MASK			0x1
2065  #define CCI_SPLT_SCRMB_CLK_ON_MASK_SFT			(0x1 << 8)
2066  #define CCI_SPLT_SCRMB_ON_SFT				7
2067  #define CCI_SPLT_SCRMB_ON_MASK				0x1
2068  #define CCI_SPLT_SCRMB_ON_MASK_SFT			(0x1 << 7)
2069  #define CCI_AUD_IDAC_TEST_EN_SFT			6
2070  #define CCI_AUD_IDAC_TEST_EN_MASK			0x1
2071  #define CCI_AUD_IDAC_TEST_EN_MASK_SFT			(0x1 << 6)
2072  #define CCI_ZERO_PAD_DISABLE_SFT			5
2073  #define CCI_ZERO_PAD_DISABLE_MASK			0x1
2074  #define CCI_ZERO_PAD_DISABLE_MASK_SFT			(0x1 << 5)
2075  #define CCI_AUD_SPLIT_TEST_EN_SFT			4
2076  #define CCI_AUD_SPLIT_TEST_EN_MASK			0x1
2077  #define CCI_AUD_SPLIT_TEST_EN_MASK_SFT			(0x1 << 4)
2078  #define CCI_AUD_SDM_MUTEL_SFT				3
2079  #define CCI_AUD_SDM_MUTEL_MASK				0x1
2080  #define CCI_AUD_SDM_MUTEL_MASK_SFT			(0x1 << 3)
2081  #define CCI_AUD_SDM_MUTER_SFT				2
2082  #define CCI_AUD_SDM_MUTER_MASK				0x1
2083  #define CCI_AUD_SDM_MUTER_MASK_SFT			(0x1 << 2)
2084  #define CCI_AUD_SDM_7BIT_SEL_SFT			1
2085  #define CCI_AUD_SDM_7BIT_SEL_MASK			0x1
2086  #define CCI_AUD_SDM_7BIT_SEL_MASK_SFT			(0x1 << 1)
2087  #define CCI_SCRAMBLER_EN_SFT				0
2088  #define CCI_SCRAMBLER_EN_MASK				0x1
2089  #define CCI_SCRAMBLER_EN_MASK_SFT			(0x1 << 0)
2090  
2091  /* AFUNC_AUD_CON1 */
2092  #define AUD_SDM_TEST_L_SFT				8
2093  #define AUD_SDM_TEST_L_MASK				0xff
2094  #define AUD_SDM_TEST_L_MASK_SFT				(0xff << 8)
2095  #define AUD_SDM_TEST_R_SFT				0
2096  #define AUD_SDM_TEST_R_MASK				0xff
2097  #define AUD_SDM_TEST_R_MASK_SFT				(0xff << 0)
2098  
2099  /* AFUNC_AUD_CON2 */
2100  #define CCI_AUD_DAC_ANA_MUTE_SFT			7
2101  #define CCI_AUD_DAC_ANA_MUTE_MASK			0x1
2102  #define CCI_AUD_DAC_ANA_MUTE_MASK_SFT			(0x1 << 7)
2103  #define CCI_AUD_DAC_ANA_RSTB_SEL_SFT			6
2104  #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK			0x1
2105  #define CCI_AUD_DAC_ANA_RSTB_SEL_MASK_SFT		(0x1 << 6)
2106  #define CCI_AUDIO_FIFO_CLKIN_INV_SFT			4
2107  #define CCI_AUDIO_FIFO_CLKIN_INV_MASK			0x1
2108  #define CCI_AUDIO_FIFO_CLKIN_INV_MASK_SFT		(0x1 << 4)
2109  #define CCI_AUDIO_FIFO_ENABLE_SFT			3
2110  #define CCI_AUDIO_FIFO_ENABLE_MASK			0x1
2111  #define CCI_AUDIO_FIFO_ENABLE_MASK_SFT			(0x1 << 3)
2112  #define CCI_ACD_MODE_SFT				2
2113  #define CCI_ACD_MODE_MASK				0x1
2114  #define CCI_ACD_MODE_MASK_SFT				(0x1 << 2)
2115  #define CCI_AFIFO_CLK_PWDB_SFT				1
2116  #define CCI_AFIFO_CLK_PWDB_MASK				0x1
2117  #define CCI_AFIFO_CLK_PWDB_MASK_SFT			(0x1 << 1)
2118  #define CCI_ACD_FUNC_RSTB_SFT				0
2119  #define CCI_ACD_FUNC_RSTB_MASK				0x1
2120  #define CCI_ACD_FUNC_RSTB_MASK_SFT			(0x1 << 0)
2121  
2122  /* AFUNC_AUD_CON3 */
2123  #define SDM_ANA13M_TESTCK_SEL_SFT			15
2124  #define SDM_ANA13M_TESTCK_SEL_MASK			0x1
2125  #define SDM_ANA13M_TESTCK_SEL_MASK_SFT			(0x1 << 15)
2126  #define SDM_ANA13M_TESTCK_SRC_SEL_SFT			12
2127  #define SDM_ANA13M_TESTCK_SRC_SEL_MASK			0x7
2128  #define SDM_ANA13M_TESTCK_SRC_SEL_MASK_SFT		(0x7 << 12)
2129  #define SDM_TESTCK_SRC_SEL_SFT				8
2130  #define SDM_TESTCK_SRC_SEL_MASK				0x7
2131  #define SDM_TESTCK_SRC_SEL_MASK_SFT			(0x7 << 8)
2132  #define DIGMIC_TESTCK_SRC_SEL_SFT			4
2133  #define DIGMIC_TESTCK_SRC_SEL_MASK			0x7
2134  #define DIGMIC_TESTCK_SRC_SEL_MASK_SFT			(0x7 << 4)
2135  #define DIGMIC_TESTCK_SEL_SFT				0
2136  #define DIGMIC_TESTCK_SEL_MASK				0x1
2137  #define DIGMIC_TESTCK_SEL_MASK_SFT			(0x1 << 0)
2138  
2139  /* AFUNC_AUD_CON4 */
2140  #define UL_FIFO_WCLK_INV_SFT				8
2141  #define UL_FIFO_WCLK_INV_MASK				0x1
2142  #define UL_FIFO_WCLK_INV_MASK_SFT			(0x1 << 8)
2143  #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT		6
2144  #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK		0x1
2145  #define UL_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT	(0x1 << 6)
2146  #define UL_FIFO_WDATA_TESTEN_SFT			5
2147  #define UL_FIFO_WDATA_TESTEN_MASK			0x1
2148  #define UL_FIFO_WDATA_TESTEN_MASK_SFT			(0x1 << 5)
2149  #define UL_FIFO_WDATA_TESTSRC_SEL_SFT			4
2150  #define UL_FIFO_WDATA_TESTSRC_SEL_MASK			0x1
2151  #define UL_FIFO_WDATA_TESTSRC_SEL_MASK_SFT		(0x1 << 4)
2152  #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_SFT		 3
2153  #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK		0x1
2154  #define UL_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT		(0x1 << 3)
2155  #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT		0
2156  #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK		0x7
2157  #define UL_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT	(0x7 << 0)
2158  
2159  /* AFUNC_AUD_CON5 */
2160  #define R_AUD_DAC_POS_LARGE_MONO_SFT			8
2161  #define R_AUD_DAC_POS_LARGE_MONO_MASK			0xff
2162  #define R_AUD_DAC_POS_LARGE_MONO_MASK_SFT		(0xff << 8)
2163  #define R_AUD_DAC_NEG_LARGE_MONO_SFT			0
2164  #define R_AUD_DAC_NEG_LARGE_MONO_MASK			0xff
2165  #define R_AUD_DAC_NEG_LARGE_MONO_MASK_SFT		(0xff << 0)
2166  
2167  /* AFUNC_AUD_CON6 */
2168  #define R_AUD_DAC_POS_SMALL_MONO_SFT			12
2169  #define R_AUD_DAC_POS_SMALL_MONO_MASK			0xf
2170  #define R_AUD_DAC_POS_SMALL_MONO_MASK_SFT		(0xf << 12)
2171  #define R_AUD_DAC_NEG_SMALL_MONO_SFT			8
2172  #define R_AUD_DAC_NEG_SMALL_MONO_MASK			0xf
2173  #define R_AUD_DAC_NEG_SMALL_MONO_MASK_SFT		(0xf << 8)
2174  #define R_AUD_DAC_POS_TINY_MONO_SFT			6
2175  #define R_AUD_DAC_POS_TINY_MONO_MASK			0x3
2176  #define R_AUD_DAC_POS_TINY_MONO_MASK_SFT		(0x3 << 6)
2177  #define R_AUD_DAC_NEG_TINY_MONO_SFT			4
2178  #define R_AUD_DAC_NEG_TINY_MONO_MASK			0x3
2179  #define R_AUD_DAC_NEG_TINY_MONO_MASK_SFT		(0x3 << 4)
2180  #define R_AUD_DAC_MONO_SEL_SFT				3
2181  #define R_AUD_DAC_MONO_SEL_MASK				0x1
2182  #define R_AUD_DAC_MONO_SEL_MASK_SFT			(0x1 << 3)
2183  #define R_AUD_DAC_3TH_SEL_SFT				1
2184  #define R_AUD_DAC_3TH_SEL_MASK				0x1
2185  #define R_AUD_DAC_3TH_SEL_MASK_SFT			(0x1 << 1)
2186  #define R_AUD_DAC_SW_RSTB_SFT				0
2187  #define R_AUD_DAC_SW_RSTB_MASK				0x1
2188  #define R_AUD_DAC_SW_RSTB_MASK_SFT			(0x1 << 0)
2189  
2190  /* AFUNC_AUD_CON7 */
2191  #define UL2_DIGMIC_TESTCK_SRC_SEL_SFT			10
2192  #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK			0x7
2193  #define UL2_DIGMIC_TESTCK_SRC_SEL_MASK_SFT		(0x7 << 10)
2194  #define UL2_DIGMIC_TESTCK_SEL_SFT			9
2195  #define UL2_DIGMIC_TESTCK_SEL_MASK			0x1
2196  #define UL2_DIGMIC_TESTCK_SEL_MASK_SFT			(0x1 << 9)
2197  #define UL2_FIFO_WCLK_INV_SFT				8
2198  #define UL2_FIFO_WCLK_INV_MASK				0x1
2199  #define UL2_FIFO_WCLK_INV_MASK_SFT			(0x1 << 8)
2200  #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_SFT		6
2201  #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK		0x1
2202  #define UL2_FIFO_DIGMIC_WDATA_TESTSRC_SEL_MASK_SFT	(0x1 << 6)
2203  #define UL2_FIFO_WDATA_TESTEN_SFT			5
2204  #define UL2_FIFO_WDATA_TESTEN_MASK			0x1
2205  #define UL2_FIFO_WDATA_TESTEN_MASK_SFT			(0x1 << 5)
2206  #define UL2_FIFO_WDATA_TESTSRC_SEL_SFT			4
2207  #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK			0x1
2208  #define UL2_FIFO_WDATA_TESTSRC_SEL_MASK_SFT		(0x1 << 4)
2209  #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_SFT		3
2210  #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK		0x1
2211  #define UL2_FIFO_WCLK_6P5M_TESTCK_SEL_MASK_SFT		(0x1 << 3)
2212  #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_SFT		0
2213  #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK		0x7
2214  #define UL2_FIFO_WCLK_6P5M_TESTCK_SRC_SEL_MASK_SFT	(0x7 << 0)
2215  
2216  /* AFUNC_AUD_CON8 */
2217  #define SPLITTER2_DITHER_EN_SFT				9
2218  #define SPLITTER2_DITHER_EN_MASK			0x1
2219  #define SPLITTER2_DITHER_EN_MASK_SFT			(0x1 << 9)
2220  #define SPLITTER1_DITHER_EN_SFT				8
2221  #define SPLITTER1_DITHER_EN_MASK			0x1
2222  #define SPLITTER1_DITHER_EN_MASK_SFT			(0x1 << 8)
2223  #define SPLITTER2_DITHER_GAIN_SFT			4
2224  #define SPLITTER2_DITHER_GAIN_MASK			0xf
2225  #define SPLITTER2_DITHER_GAIN_MASK_SFT			(0xf << 4)
2226  #define SPLITTER1_DITHER_GAIN_SFT			0
2227  #define SPLITTER1_DITHER_GAIN_MASK			0xf
2228  #define SPLITTER1_DITHER_GAIN_MASK_SFT			(0xf << 0)
2229  
2230  /* AFUNC_AUD_CON9 */
2231  #define CCI_AUD_ANACK_SEL_2ND_SFT			15
2232  #define CCI_AUD_ANACK_SEL_2ND_MASK			0x1
2233  #define CCI_AUD_ANACK_SEL_2ND_MASK_SFT			(0x1 << 15)
2234  #define CCI_AUDIO_FIFO_WPTR_2ND_SFT			12
2235  #define CCI_AUDIO_FIFO_WPTR_2ND_MASK			0x7
2236  #define CCI_AUDIO_FIFO_WPTR_2ND_MASK_SFT		(0x7 << 12)
2237  #define CCI_SCRAMBLER_CG_EN_2ND_SFT			11
2238  #define CCI_SCRAMBLER_CG_EN_2ND_MASK			0x1
2239  #define CCI_SCRAMBLER_CG_EN_2ND_MASK_SFT		 (0x1 << 11)
2240  #define CCI_LCH_INV_2ND_SFT				10
2241  #define CCI_LCH_INV_2ND_MASK				0x1
2242  #define CCI_LCH_INV_2ND_MASK_SFT			(0x1 << 10)
2243  #define CCI_RAND_EN_2ND_SFT				9
2244  #define CCI_RAND_EN_2ND_MASK				0x1
2245  #define CCI_RAND_EN_2ND_MASK_SFT			(0x1 << 9)
2246  #define CCI_SPLT_SCRMB_CLK_ON_2ND_SFT			8
2247  #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK			0x1
2248  #define CCI_SPLT_SCRMB_CLK_ON_2ND_MASK_SFT		(0x1 << 8)
2249  #define CCI_SPLT_SCRMB_ON_2ND_SFT			7
2250  #define CCI_SPLT_SCRMB_ON_2ND_MASK			0x1
2251  #define CCI_SPLT_SCRMB_ON_2ND_MASK_SFT			(0x1 << 7)
2252  #define CCI_AUD_IDAC_TEST_EN_2ND_SFT			6
2253  #define CCI_AUD_IDAC_TEST_EN_2ND_MASK			0x1
2254  #define CCI_AUD_IDAC_TEST_EN_2ND_MASK_SFT		(0x1 << 6)
2255  #define CCI_ZERO_PAD_DISABLE_2ND_SFT			5
2256  #define CCI_ZERO_PAD_DISABLE_2ND_MASK			0x1
2257  #define CCI_ZERO_PAD_DISABLE_2ND_MASK_SFT		(0x1 << 5)
2258  #define CCI_AUD_SPLIT_TEST_EN_2ND_SFT			4
2259  #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK			0x1
2260  #define CCI_AUD_SPLIT_TEST_EN_2ND_MASK_SFT		(0x1 << 4)
2261  #define CCI_AUD_SDM_MUTEL_2ND_SFT			3
2262  #define CCI_AUD_SDM_MUTEL_2ND_MASK			0x1
2263  #define CCI_AUD_SDM_MUTEL_2ND_MASK_SFT			(0x1 << 3)
2264  #define CCI_AUD_SDM_MUTER_2ND_SFT			2
2265  #define CCI_AUD_SDM_MUTER_2ND_MASK			0x1
2266  #define CCI_AUD_SDM_MUTER_2ND_MASK_SFT			(0x1 << 2)
2267  #define CCI_AUD_SDM_7BIT_SEL_2ND_SFT			1
2268  #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK			0x1
2269  #define CCI_AUD_SDM_7BIT_SEL_2ND_MASK_SFT		(0x1 << 1)
2270  #define CCI_SCRAMBLER_EN_2ND_SFT			0
2271  #define CCI_SCRAMBLER_EN_2ND_MASK			0x1
2272  #define CCI_SCRAMBLER_EN_2ND_MASK_SFT			(0x1 << 0)
2273  
2274  /* AFUNC_AUD_CON10 */
2275  #define AUD_SDM_TEST_L_2ND_SFT				8
2276  #define AUD_SDM_TEST_L_2ND_MASK				0xff
2277  #define AUD_SDM_TEST_L_2ND_MASK_SFT			(0xff << 8)
2278  #define AUD_SDM_TEST_R_2ND_SFT				0
2279  #define AUD_SDM_TEST_R_2ND_MASK				0xff
2280  #define AUD_SDM_TEST_R_2ND_MASK_SFT			(0xff << 0)
2281  
2282  /* AFUNC_AUD_CON11 */
2283  #define CCI_AUD_DAC_ANA_MUTE_2ND_SFT			7
2284  #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK			0x1
2285  #define CCI_AUD_DAC_ANA_MUTE_2ND_MASK_SFT		(0x1 << 7)
2286  #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_SFT		6
2287  #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK		0x1
2288  #define CCI_AUD_DAC_ANA_RSTB_SEL_2ND_MASK_SFT		(0x1 << 6)
2289  #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_SFT		4
2290  #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK		0x1
2291  #define CCI_AUDIO_FIFO_CLKIN_INV_2ND_MASK_SFT		(0x1 << 4)
2292  #define CCI_AUDIO_FIFO_ENABLE_2ND_SFT			3
2293  #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK			0x1
2294  #define CCI_AUDIO_FIFO_ENABLE_2ND_MASK_SFT		(0x1 << 3)
2295  #define CCI_ACD_MODE_2ND_SFT				2
2296  #define CCI_ACD_MODE_2ND_MASK				0x1
2297  #define CCI_ACD_MODE_2ND_MASK_SFT			(0x1 << 2)
2298  #define CCI_AFIFO_CLK_PWDB_2ND_SFT			1
2299  #define CCI_AFIFO_CLK_PWDB_2ND_MASK			0x1
2300  #define CCI_AFIFO_CLK_PWDB_2ND_MASK_SFT			(0x1 << 1)
2301  #define CCI_ACD_FUNC_RSTB_2ND_SFT			0
2302  #define CCI_ACD_FUNC_RSTB_2ND_MASK			0x1
2303  #define CCI_ACD_FUNC_RSTB_2ND_MASK_SFT			(0x1 << 0)
2304  
2305  /* AFUNC_AUD_CON12 */
2306  #define SPLITTER2_DITHER_EN_2ND_SFT			9
2307  #define SPLITTER2_DITHER_EN_2ND_MASK			0x1
2308  #define SPLITTER2_DITHER_EN_2ND_MASK_SFT		(0x1 << 9)
2309  #define SPLITTER1_DITHER_EN_2ND_SFT			8
2310  #define SPLITTER1_DITHER_EN_2ND_MASK			0x1
2311  #define SPLITTER1_DITHER_EN_2ND_MASK_SFT		(0x1 << 8)
2312  #define SPLITTER2_DITHER_GAIN_2ND_SFT			4
2313  #define SPLITTER2_DITHER_GAIN_2ND_MASK			0xf
2314  #define SPLITTER2_DITHER_GAIN_2ND_MASK_SFT		(0xf << 4)
2315  #define SPLITTER1_DITHER_GAIN_2ND_SFT			0
2316  #define SPLITTER1_DITHER_GAIN_2ND_MASK			0xf
2317  #define SPLITTER1_DITHER_GAIN_2ND_MASK_SFT		(0xf << 0)
2318  
2319  /* AFUNC_AUD_MON0 */
2320  #define AUD_SCR_OUT_L_SFT				8
2321  #define AUD_SCR_OUT_L_MASK				0xff
2322  #define AUD_SCR_OUT_L_MASK_SFT				(0xff << 8)
2323  #define AUD_SCR_OUT_R_SFT				0
2324  #define AUD_SCR_OUT_R_MASK				0xff
2325  #define AUD_SCR_OUT_R_MASK_SFT				(0xff << 0)
2326  
2327  /* AFUNC_AUD_MON1 */
2328  #define AUD_SCR_OUT_L_2ND_SFT				8
2329  #define AUD_SCR_OUT_L_2ND_MASK				0xff
2330  #define AUD_SCR_OUT_L_2ND_MASK_SFT			(0xff << 8)
2331  #define AUD_SCR_OUT_R_2ND_SFT				0
2332  #define AUD_SCR_OUT_R_2ND_MASK				0xff
2333  #define AUD_SCR_OUT_R_2ND_MASK_SFT			(0xff << 0)
2334  
2335  /* AUDRC_TUNE_MON0 */
2336  #define ASYNC_TEST_OUT_BCK_SFT				15
2337  #define ASYNC_TEST_OUT_BCK_MASK				0x1
2338  #define ASYNC_TEST_OUT_BCK_MASK_SFT			(0x1 << 15)
2339  #define RGS_AUDRCTUNE1READ_SFT				8
2340  #define RGS_AUDRCTUNE1READ_MASK				0x1f
2341  #define RGS_AUDRCTUNE1READ_MASK_SFT			(0x1f << 8)
2342  #define RGS_AUDRCTUNE0READ_SFT				0
2343  #define RGS_AUDRCTUNE0READ_MASK				0x1f
2344  #define RGS_AUDRCTUNE0READ_MASK_SFT			(0x1f << 0)
2345  
2346  /* AFE_ADDA_MTKAIF_FIFO_CFG0 */
2347  #define AFE_RESERVED_SFT				1
2348  #define AFE_RESERVED_MASK				0x7fff
2349  #define AFE_RESERVED_MASK_SFT				(0x7fff << 1)
2350  #define RG_MTKAIF_RXIF_FIFO_INTEN_SFT			0
2351  #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK			0x1
2352  #define RG_MTKAIF_RXIF_FIFO_INTEN_MASK_SFT		(0x1 << 0)
2353  
2354  /* AFE_ADDA_MTKAIF_FIFO_LOG_MON1 */
2355  #define MTKAIF_RXIF_WR_FULL_STATUS_SFT			1
2356  #define MTKAIF_RXIF_WR_FULL_STATUS_MASK			0x1
2357  #define MTKAIF_RXIF_WR_FULL_STATUS_MASK_SFT		(0x1 << 1)
2358  #define MTKAIF_RXIF_RD_EMPTY_STATUS_SFT			0
2359  #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK		0x1
2360  #define MTKAIF_RXIF_RD_EMPTY_STATUS_MASK_SFT		(0x1 << 0)
2361  
2362  /* AFE_ADDA_MTKAIF_MON0 */
2363  #define MTKAIFTX_V3_SYNC_OUT_SFT			15
2364  #define MTKAIFTX_V3_SYNC_OUT_MASK			0x1
2365  #define MTKAIFTX_V3_SYNC_OUT_MASK_SFT			(0x1 << 15)
2366  #define MTKAIFTX_V3_SDATA_OUT3_SFT			14
2367  #define MTKAIFTX_V3_SDATA_OUT3_MASK			0x1
2368  #define MTKAIFTX_V3_SDATA_OUT3_MASK_SFT			(0x1 << 14)
2369  #define MTKAIFTX_V3_SDATA_OUT2_SFT			13
2370  #define MTKAIFTX_V3_SDATA_OUT2_MASK			0x1
2371  #define MTKAIFTX_V3_SDATA_OUT2_MASK_SFT			(0x1 << 13)
2372  #define MTKAIFTX_V3_SDATA_OUT1_SFT			12
2373  #define MTKAIFTX_V3_SDATA_OUT1_MASK			0x1
2374  #define MTKAIFTX_V3_SDATA_OUT1_MASK_SFT			(0x1 << 12)
2375  #define MTKAIF_RXIF_FIFO_STATUS_SFT			0
2376  #define MTKAIF_RXIF_FIFO_STATUS_MASK			0xfff
2377  #define MTKAIF_RXIF_FIFO_STATUS_MASK_SFT		(0xfff << 0)
2378  
2379  /* AFE_ADDA_MTKAIF_MON1 */
2380  #define MTKAIFRX_V3_SYNC_IN_SFT				15
2381  #define MTKAIFRX_V3_SYNC_IN_MASK			0x1
2382  #define MTKAIFRX_V3_SYNC_IN_MASK_SFT			(0x1 << 15)
2383  #define MTKAIFRX_V3_SDATA_IN3_SFT			14
2384  #define MTKAIFRX_V3_SDATA_IN3_MASK			0x1
2385  #define MTKAIFRX_V3_SDATA_IN3_MASK_SFT			(0x1 << 14)
2386  #define MTKAIFRX_V3_SDATA_IN2_SFT			13
2387  #define MTKAIFRX_V3_SDATA_IN2_MASK			0x1
2388  #define MTKAIFRX_V3_SDATA_IN2_MASK_SFT			(0x1 << 13)
2389  #define MTKAIFRX_V3_SDATA_IN1_SFT			12
2390  #define MTKAIFRX_V3_SDATA_IN1_MASK			0x1
2391  #define MTKAIFRX_V3_SDATA_IN1_MASK_SFT			(0x1 << 12)
2392  #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_SFT		11
2393  #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK		0x1
2394  #define MTKAIF_RXIF_SEARCH_FAIL_FLAG_MASK_SFT		(0x1 << 11)
2395  #define MTKAIF_RXIF_INVALID_FLAG_SFT			8
2396  #define MTKAIF_RXIF_INVALID_FLAG_MASK			0x1
2397  #define MTKAIF_RXIF_INVALID_FLAG_MASK_SFT		(0x1 << 8)
2398  #define MTKAIF_RXIF_INVALID_CYCLE_SFT			0
2399  #define MTKAIF_RXIF_INVALID_CYCLE_MASK			0xff
2400  #define MTKAIF_RXIF_INVALID_CYCLE_MASK_SFT		(0xff << 0)
2401  
2402  /* AFE_ADDA_MTKAIF_MON2 */
2403  #define MTKAIF_TXIF_IN_CH2_SFT				8
2404  #define MTKAIF_TXIF_IN_CH2_MASK				0xff
2405  #define MTKAIF_TXIF_IN_CH2_MASK_SFT			(0xff << 8)
2406  #define MTKAIF_TXIF_IN_CH1_SFT				0
2407  #define MTKAIF_TXIF_IN_CH1_MASK				0xff
2408  #define MTKAIF_TXIF_IN_CH1_MASK_SFT			(0xff << 0)
2409  
2410  /* AFE_ADDA6_MTKAIF_MON3 */
2411  #define ADDA6_MTKAIF_TXIF_IN_CH2_SFT			8
2412  #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK			0xff
2413  #define ADDA6_MTKAIF_TXIF_IN_CH2_MASK_SFT		(0xff << 8)
2414  #define ADDA6_MTKAIF_TXIF_IN_CH1_SFT			0
2415  #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK			0xff
2416  #define ADDA6_MTKAIF_TXIF_IN_CH1_MASK_SFT		(0xff << 0)
2417  
2418  /* AFE_ADDA_MTKAIF_MON4 */
2419  #define MTKAIF_RXIF_OUT_CH2_SFT				8
2420  #define MTKAIF_RXIF_OUT_CH2_MASK			0xff
2421  #define MTKAIF_RXIF_OUT_CH2_MASK_SFT			(0xff << 8)
2422  #define MTKAIF_RXIF_OUT_CH1_SFT				0
2423  #define MTKAIF_RXIF_OUT_CH1_MASK			0xff
2424  #define MTKAIF_RXIF_OUT_CH1_MASK_SFT			(0xff << 0)
2425  
2426  /* AFE_ADDA_MTKAIF_MON5 */
2427  #define MTKAIF_RXIF_OUT_CH3_SFT				0
2428  #define MTKAIF_RXIF_OUT_CH3_MASK			0xff
2429  #define MTKAIF_RXIF_OUT_CH3_MASK_SFT			(0xff << 0)
2430  
2431  /* AFE_ADDA_MTKAIF_CFG0 */
2432  #define RG_MTKAIF_RXIF_CLKINV_SFT			15
2433  #define RG_MTKAIF_RXIF_CLKINV_MASK			0x1
2434  #define RG_MTKAIF_RXIF_CLKINV_MASK_SFT			(0x1 << 15)
2435  #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_SFT		9
2436  #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK		0x1
2437  #define RG_ADDA6_MTKAIF_TXIF_PROTOCOL2_MASK_SFT		(0x1 << 9)
2438  #define RG_MTKAIF_RXIF_PROTOCOL2_SFT			8
2439  #define RG_MTKAIF_RXIF_PROTOCOL2_MASK			0x1
2440  #define RG_MTKAIF_RXIF_PROTOCOL2_MASK_SFT		(0x1 << 8)
2441  #define RG_MTKAIF_BYPASS_SRC_MODE_SFT			6
2442  #define RG_MTKAIF_BYPASS_SRC_MODE_MASK			0x3
2443  #define RG_MTKAIF_BYPASS_SRC_MODE_MASK_SFT		(0x3 << 6)
2444  #define RG_MTKAIF_BYPASS_SRC_TEST_SFT			5
2445  #define RG_MTKAIF_BYPASS_SRC_TEST_MASK			0x1
2446  #define RG_MTKAIF_BYPASS_SRC_TEST_MASK_SFT		(0x1 << 5)
2447  #define RG_MTKAIF_TXIF_PROTOCOL2_SFT			4
2448  #define RG_MTKAIF_TXIF_PROTOCOL2_MASK			0x1
2449  #define RG_MTKAIF_TXIF_PROTOCOL2_MASK_SFT		(0x1 << 4)
2450  #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_SFT		3
2451  #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK		0x1
2452  #define RG_ADDA6_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT		(0x1 << 3)
2453  #define RG_MTKAIF_PMIC_TXIF_8TO5_SFT			2
2454  #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK			0x1
2455  #define RG_MTKAIF_PMIC_TXIF_8TO5_MASK_SFT		(0x1 << 2)
2456  #define RG_MTKAIF_LOOPBACK_TEST2_SFT			1
2457  #define RG_MTKAIF_LOOPBACK_TEST2_MASK			0x1
2458  #define RG_MTKAIF_LOOPBACK_TEST2_MASK_SFT		(0x1 << 1)
2459  #define RG_MTKAIF_LOOPBACK_TEST1_SFT			0
2460  #define RG_MTKAIF_LOOPBACK_TEST1_MASK			0x1
2461  #define RG_MTKAIF_LOOPBACK_TEST1_MASK_SFT		(0x1 << 0)
2462  
2463  /* AFE_ADDA_MTKAIF_RX_CFG0 */
2464  #define RG_MTKAIF_RXIF_VOICE_MODE_SFT			12
2465  #define RG_MTKAIF_RXIF_VOICE_MODE_MASK			0xf
2466  #define RG_MTKAIF_RXIF_VOICE_MODE_MASK_SFT		(0xf << 12)
2467  #define RG_MTKAIF_RXIF_DATA_BIT_SFT			8
2468  #define RG_MTKAIF_RXIF_DATA_BIT_MASK			0x7
2469  #define RG_MTKAIF_RXIF_DATA_BIT_MASK_SFT		(0x7 << 8)
2470  #define RG_MTKAIF_RXIF_FIFO_RSP_SFT			4
2471  #define RG_MTKAIF_RXIF_FIFO_RSP_MASK			0x7
2472  #define RG_MTKAIF_RXIF_FIFO_RSP_MASK_SFT		(0x7 << 4)
2473  #define RG_MTKAIF_RXIF_DETECT_ON_SFT			3
2474  #define RG_MTKAIF_RXIF_DETECT_ON_MASK			0x1
2475  #define RG_MTKAIF_RXIF_DETECT_ON_MASK_SFT		(0x1 << 3)
2476  #define RG_MTKAIF_RXIF_DATA_MODE_SFT			0
2477  #define RG_MTKAIF_RXIF_DATA_MODE_MASK			0x1
2478  #define RG_MTKAIF_RXIF_DATA_MODE_MASK_SFT		(0x1 << 0)
2479  
2480  /* AFE_ADDA_MTKAIF_RX_CFG1 */
2481  #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_SFT		12
2482  #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK		0xf
2483  #define RG_MTKAIF_RXIF_SYNC_SEARCH_TABLE_MASK_SFT	(0xf << 12)
2484  #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_SFT	8
2485  #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK	0xf
2486  #define RG_MTKAIF_RXIF_INVALID_SYNC_CHECK_ROUND_MASK_SFT	(0xf << 8)
2487  #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_SFT		4
2488  #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK		0xf
2489  #define RG_MTKAIF_RXIF_SYNC_CHECK_ROUND_MASK_SFT	(0xf << 4)
2490  #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_SFT		0
2491  #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK	0xf
2492  #define RG_MTKAIF_RXIF_VOICE_MODE_PROTOCOL2_MASK_SFT	(0xf << 0)
2493  
2494  /* AFE_ADDA_MTKAIF_RX_CFG2 */
2495  #define RG_MTKAIF_RXIF_P2_INPUT_SEL_SFT			15
2496  #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK		0x1
2497  #define RG_MTKAIF_RXIF_P2_INPUT_SEL_MASK_SFT		(0x1 << 15)
2498  #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_SFT		14
2499  #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK		0x1
2500  #define RG_MTKAIF_RXIF_SYNC_WORD2_DISABLE_MASK_SFT	(0x1 << 14)
2501  #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_SFT		13
2502  #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK		0x1
2503  #define RG_MTKAIF_RXIF_SYNC_WORD1_DISABLE_MASK_SFT	(0x1 << 13)
2504  #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_SFT		12
2505  #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK		0x1
2506  #define RG_MTKAIF_RXIF_CLEAR_SYNC_FAIL_MASK_SFT		(0x1 << 12)
2507  #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_SFT		0
2508  #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK		0xfff
2509  #define RG_MTKAIF_RXIF_SYNC_CNT_TABLE_MASK_SFT		(0xfff << 0)
2510  
2511  /* AFE_ADDA_MTKAIF_RX_CFG3 */
2512  #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_SFT		7
2513  #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK		0x1
2514  #define RG_MTKAIF_RXIF_LOOPBACK_USE_NLE_MASK_SFT	(0x1 << 7)
2515  #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_SFT		4
2516  #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK		0x7
2517  #define RG_MTKAIF_RXIF_FIFO_RSP_PROTOCOL2_MASK_SFT	(0x7 << 4)
2518  #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_SFT		3
2519  #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK		0x1
2520  #define RG_MTKAIF_RXIF_DETECT_ON_PROTOCOL2_MASK_SFT	(0x1 << 3)
2521  
2522  /* AFE_ADDA_MTKAIF_SYNCWORD_CFG0 */
2523  #define RG_MTKAIF_RX_SYNC_WORD2_SFT			4
2524  #define RG_MTKAIF_RX_SYNC_WORD2_MASK			0x7
2525  #define RG_MTKAIF_RX_SYNC_WORD2_MASK_SFT		(0x7 << 4)
2526  #define RG_MTKAIF_RX_SYNC_WORD1_SFT			0
2527  #define RG_MTKAIF_RX_SYNC_WORD1_MASK			0x7
2528  #define RG_MTKAIF_RX_SYNC_WORD1_MASK_SFT		(0x7 << 0)
2529  
2530  /* AFE_ADDA_MTKAIF_SYNCWORD_CFG1 */
2531  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_SFT		12
2532  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK		0x7
2533  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD2_MASK_SFT		(0x7 << 12)
2534  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_SFT		8
2535  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK		0x7
2536  #define RG_ADDA6_MTKAIF_TX_SYNC_WORD1_MASK_SFT		(0x7 << 8)
2537  #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_SFT		4
2538  #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK		0x7
2539  #define RG_ADDA_MTKAIF_TX_SYNC_WORD2_MASK_SFT		(0x7 << 4)
2540  #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_SFT		0
2541  #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK		0x7
2542  #define RG_ADDA_MTKAIF_TX_SYNC_WORD1_MASK_SFT		(0x7 << 0)
2543  
2544  /* AFE_SGEN_CFG0 */
2545  #define SGEN_AMP_DIV_CH1_CTL_SFT			12
2546  #define SGEN_AMP_DIV_CH1_CTL_MASK			0xf
2547  #define SGEN_AMP_DIV_CH1_CTL_MASK_SFT			(0xf << 12)
2548  #define SGEN_DAC_EN_CTL_SFT				7
2549  #define SGEN_DAC_EN_CTL_MASK				0x1
2550  #define SGEN_DAC_EN_CTL_MASK_SFT			(0x1 << 7)
2551  #define SGEN_MUTE_SW_CTL_SFT				6
2552  #define SGEN_MUTE_SW_CTL_MASK				0x1
2553  #define SGEN_MUTE_SW_CTL_MASK_SFT			(0x1 << 6)
2554  #define R_AUD_SDM_MUTE_L_SFT				5
2555  #define R_AUD_SDM_MUTE_L_MASK				0x1
2556  #define R_AUD_SDM_MUTE_L_MASK_SFT			(0x1 << 5)
2557  #define R_AUD_SDM_MUTE_R_SFT				4
2558  #define R_AUD_SDM_MUTE_R_MASK				0x1
2559  #define R_AUD_SDM_MUTE_R_MASK_SFT			(0x1 << 4)
2560  #define R_AUD_SDM_MUTE_L_2ND_SFT			3
2561  #define R_AUD_SDM_MUTE_L_2ND_MASK			0x1
2562  #define R_AUD_SDM_MUTE_L_2ND_MASK_SFT			(0x1 << 3)
2563  #define R_AUD_SDM_MUTE_R_2ND_SFT			2
2564  #define R_AUD_SDM_MUTE_R_2ND_MASK			0x1
2565  #define R_AUD_SDM_MUTE_R_2ND_MASK_SFT			(0x1 << 2)
2566  
2567  /* AFE_SGEN_CFG1 */
2568  #define C_SGEN_RCH_INV_5BIT_SFT				15
2569  #define C_SGEN_RCH_INV_5BIT_MASK			0x1
2570  #define C_SGEN_RCH_INV_5BIT_MASK_SFT			(0x1 << 15)
2571  #define C_SGEN_RCH_INV_8BIT_SFT				14
2572  #define C_SGEN_RCH_INV_8BIT_MASK			0x1
2573  #define C_SGEN_RCH_INV_8BIT_MASK_SFT			(0x1 << 14)
2574  #define SGEN_FREQ_DIV_CH1_CTL_SFT			0
2575  #define SGEN_FREQ_DIV_CH1_CTL_MASK			0x1f
2576  #define SGEN_FREQ_DIV_CH1_CTL_MASK_SFT			(0x1f << 0)
2577  
2578  /* AFE_ADC_ASYNC_FIFO_CFG */
2579  #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_SFT		5
2580  #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK		0x1
2581  #define RG_UL_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT		(0x1 << 5)
2582  #define RG_UL_ASYNC_FIFO_SOFT_RST_SFT			4
2583  #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK			0x1
2584  #define RG_UL_ASYNC_FIFO_SOFT_RST_MASK_SFT		(0x1 << 4)
2585  #define RG_AMIC_UL_ADC_CLK_SEL_SFT			1
2586  #define RG_AMIC_UL_ADC_CLK_SEL_MASK			0x1
2587  #define RG_AMIC_UL_ADC_CLK_SEL_MASK_SFT			(0x1 << 1)
2588  
2589  /* AFE_ADC_ASYNC_FIFO_CFG1 */
2590  #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_SFT		5
2591  #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK		0x1
2592  #define RG_UL2_ASYNC_FIFO_SOFT_RST_EN_MASK_SFT		(0x1 << 5)
2593  #define RG_UL2_ASYNC_FIFO_SOFT_RST_SFT			4
2594  #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK			0x1
2595  #define RG_UL2_ASYNC_FIFO_SOFT_RST_MASK_SFT		(0x1 << 4)
2596  
2597  /* AFE_DCCLK_CFG0 */
2598  #define DCCLK_DIV_SFT					5
2599  #define DCCLK_DIV_MASK					0x7ff
2600  #define DCCLK_DIV_MASK_SFT				(0x7ff << 5)
2601  #define DCCLK_INV_SFT					4
2602  #define DCCLK_INV_MASK					0x1
2603  #define DCCLK_INV_MASK_SFT				(0x1 << 4)
2604  #define DCCLK_REF_CK_SEL_SFT				2
2605  #define DCCLK_REF_CK_SEL_MASK				0x3
2606  #define DCCLK_REF_CK_SEL_MASK_SFT			(0x3 << 2)
2607  #define DCCLK_PDN_SFT					1
2608  #define DCCLK_PDN_MASK					0x1
2609  #define DCCLK_PDN_MASK_SFT				(0x1 << 1)
2610  #define DCCLK_GEN_ON_SFT				0
2611  #define DCCLK_GEN_ON_MASK				0x1
2612  #define DCCLK_GEN_ON_MASK_SFT				(0x1 << 0)
2613  
2614  /* AFE_DCCLK_CFG1 */
2615  #define RESYNC_SRC_SEL_SFT				10
2616  #define RESYNC_SRC_SEL_MASK				0x3
2617  #define RESYNC_SRC_SEL_MASK_SFT				(0x3 << 10)
2618  #define RESYNC_SRC_CK_INV_SFT				9
2619  #define RESYNC_SRC_CK_INV_MASK				0x1
2620  #define RESYNC_SRC_CK_INV_MASK_SFT			(0x1 << 9)
2621  #define DCCLK_RESYNC_BYPASS_SFT				8
2622  #define DCCLK_RESYNC_BYPASS_MASK			0x1
2623  #define DCCLK_RESYNC_BYPASS_MASK_SFT			(0x1 << 8)
2624  #define DCCLK_PHASE_SEL_SFT				4
2625  #define DCCLK_PHASE_SEL_MASK				0xf
2626  #define DCCLK_PHASE_SEL_MASK_SFT			(0xf << 4)
2627  
2628  /* AUDIO_DIG_CFG */
2629  #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_SFT		15
2630  #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK		0x1
2631  #define RG_AUD_PAD_TOP_DAT_MISO2_LOOPBACK_MASK_SFT	(0x1 << 15)
2632  #define RG_AUD_PAD_TOP_PHASE_MODE2_SFT			8
2633  #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK			0x7f
2634  #define RG_AUD_PAD_TOP_PHASE_MODE2_MASK_SFT		(0x7f << 8)
2635  #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_SFT		7
2636  #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK		0x1
2637  #define RG_AUD_PAD_TOP_DAT_MISO_LOOPBACK_MASK_SFT	(0x1 << 7)
2638  #define RG_AUD_PAD_TOP_PHASE_MODE_SFT			0
2639  #define RG_AUD_PAD_TOP_PHASE_MODE_MASK			0x7f
2640  #define RG_AUD_PAD_TOP_PHASE_MODE_MASK_SFT		(0x7f << 0)
2641  
2642  /* AUDIO_DIG_CFG1 */
2643  #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_SFT		7
2644  #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK		0x1
2645  #define RG_AUD_PAD_TOP_DAT_MISO3_LOOPBACK_MASK_SFT	(0x1 << 7)
2646  #define RG_AUD_PAD_TOP_PHASE_MODE3_SFT			0
2647  #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK			0x7f
2648  #define RG_AUD_PAD_TOP_PHASE_MODE3_MASK_SFT		(0x7f << 0)
2649  
2650  /* AFE_AUD_PAD_TOP */
2651  #define RG_AUD_PAD_TOP_TX_FIFO_RSP_SFT			12
2652  #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK			0x7
2653  #define RG_AUD_PAD_TOP_TX_FIFO_RSP_MASK_SFT		(0x7 << 12)
2654  #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_SFT		11
2655  #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK	0x1
2656  #define RG_AUD_PAD_TOP_MTKAIF_CLK_PROTOCOL2_MASK_SFT	(0x1 << 11)
2657  #define RG_AUD_PAD_TOP_TX_FIFO_ON_SFT			8
2658  #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK			0x1
2659  #define RG_AUD_PAD_TOP_TX_FIFO_ON_MASK_SFT		(0x1 << 8)
2660  
2661  /* AFE_AUD_PAD_TOP_MON */
2662  #define ADDA_AUD_PAD_TOP_MON_SFT			0
2663  #define ADDA_AUD_PAD_TOP_MON_MASK			0xffff
2664  #define ADDA_AUD_PAD_TOP_MON_MASK_SFT			(0xffff << 0)
2665  
2666  /* AFE_AUD_PAD_TOP_MON1 */
2667  #define ADDA_AUD_PAD_TOP_MON1_SFT			0
2668  #define ADDA_AUD_PAD_TOP_MON1_MASK			0xffff
2669  #define ADDA_AUD_PAD_TOP_MON1_MASK_SFT			(0xffff << 0)
2670  
2671  /* AFE_AUD_PAD_TOP_MON2 */
2672  #define ADDA_AUD_PAD_TOP_MON2_SFT			0
2673  #define ADDA_AUD_PAD_TOP_MON2_MASK			0xffff
2674  #define ADDA_AUD_PAD_TOP_MON2_MASK_SFT			(0xffff << 0)
2675  
2676  /* AFE_DL_NLE_CFG */
2677  #define NLE_RCH_HPGAIN_SEL_SFT				10
2678  #define NLE_RCH_HPGAIN_SEL_MASK				0x1
2679  #define NLE_RCH_HPGAIN_SEL_MASK_SFT			(0x1 << 10)
2680  #define NLE_RCH_CH_SEL_SFT				9
2681  #define NLE_RCH_CH_SEL_MASK				0x1
2682  #define NLE_RCH_CH_SEL_MASK_SFT				(0x1 << 9)
2683  #define NLE_RCH_ON_SFT					8
2684  #define NLE_RCH_ON_MASK					0x1
2685  #define NLE_RCH_ON_MASK_SFT				(0x1 << 8)
2686  #define NLE_LCH_HPGAIN_SEL_SFT				2
2687  #define NLE_LCH_HPGAIN_SEL_MASK				0x1
2688  #define NLE_LCH_HPGAIN_SEL_MASK_SFT			(0x1 << 2)
2689  #define NLE_LCH_CH_SEL_SFT				1
2690  #define NLE_LCH_CH_SEL_MASK				0x1
2691  #define NLE_LCH_CH_SEL_MASK_SFT				(0x1 << 1)
2692  #define NLE_LCH_ON_SFT					0
2693  #define NLE_LCH_ON_MASK					0x1
2694  #define NLE_LCH_ON_MASK_SFT				(0x1 << 0)
2695  
2696  /* AFE_DL_NLE_MON */
2697  #define NLE_MONITOR_SFT					0
2698  #define NLE_MONITOR_MASK				0x3fff
2699  #define NLE_MONITOR_MASK_SFT				(0x3fff << 0)
2700  
2701  /* AFE_CG_EN_MON */
2702  #define CK_CG_EN_MON_SFT				0
2703  #define CK_CG_EN_MON_MASK				0x3f
2704  #define CK_CG_EN_MON_MASK_SFT				(0x3f << 0)
2705  
2706  /* AFE_MIC_ARRAY_CFG */
2707  #define RG_AMIC_ADC1_SOURCE_SEL_SFT			10
2708  #define RG_AMIC_ADC1_SOURCE_SEL_MASK			0x3
2709  #define RG_AMIC_ADC1_SOURCE_SEL_MASK_SFT		(0x3 << 10)
2710  #define RG_AMIC_ADC2_SOURCE_SEL_SFT			8
2711  #define RG_AMIC_ADC2_SOURCE_SEL_MASK			0x3
2712  #define RG_AMIC_ADC2_SOURCE_SEL_MASK_SFT		(0x3 << 8)
2713  #define RG_AMIC_ADC3_SOURCE_SEL_SFT			6
2714  #define RG_AMIC_ADC3_SOURCE_SEL_MASK			0x3
2715  #define RG_AMIC_ADC3_SOURCE_SEL_MASK_SFT		(0x3 << 6)
2716  #define RG_DMIC_ADC1_SOURCE_SEL_SFT			4
2717  #define RG_DMIC_ADC1_SOURCE_SEL_MASK			0x3
2718  #define RG_DMIC_ADC1_SOURCE_SEL_MASK_SFT		(0x3 << 4)
2719  #define RG_DMIC_ADC2_SOURCE_SEL_SFT			2
2720  #define RG_DMIC_ADC2_SOURCE_SEL_MASK			0x3
2721  #define RG_DMIC_ADC2_SOURCE_SEL_MASK_SFT		(0x3 << 2)
2722  #define RG_DMIC_ADC3_SOURCE_SEL_SFT			0
2723  #define RG_DMIC_ADC3_SOURCE_SEL_MASK			0x3
2724  #define RG_DMIC_ADC3_SOURCE_SEL_MASK_SFT		(0x3 << 0)
2725  
2726  /* AFE_CHOP_CFG0 */
2727  #define RG_CHOP_DIV_SEL_SFT				4
2728  #define RG_CHOP_DIV_SEL_MASK				0x1f
2729  #define RG_CHOP_DIV_SEL_MASK_SFT			(0x1f << 4)
2730  #define RG_CHOP_DIV_EN_SFT				0
2731  #define RG_CHOP_DIV_EN_MASK				0x1
2732  #define RG_CHOP_DIV_EN_MASK_SFT				(0x1 << 0)
2733  
2734  /* AFE_MTKAIF_MUX_CFG */
2735  #define RG_ADDA6_EN_SEL_SFT				12
2736  #define RG_ADDA6_EN_SEL_MASK				0x1
2737  #define RG_ADDA6_EN_SEL_MASK_SFT			(0x1 << 12)
2738  #define RG_ADDA6_CH2_SEL_SFT				10
2739  #define RG_ADDA6_CH2_SEL_MASK				0x3
2740  #define RG_ADDA6_CH2_SEL_MASK_SFT			(0x3 << 10)
2741  #define RG_ADDA6_CH1_SEL_SFT				8
2742  #define RG_ADDA6_CH1_SEL_MASK				0x3
2743  #define RG_ADDA6_CH1_SEL_MASK_SFT			(0x3 << 8)
2744  #define RG_ADDA_EN_SEL_SFT				4
2745  #define RG_ADDA_EN_SEL_MASK				0x1
2746  #define RG_ADDA_EN_SEL_MASK_SFT				(0x1 << 4)
2747  #define RG_ADDA_CH2_SEL_SFT				2
2748  #define RG_ADDA_CH2_SEL_MASK				0x3
2749  #define RG_ADDA_CH2_SEL_MASK_SFT			(0x3 << 2)
2750  #define RG_ADDA_CH1_SEL_SFT				0
2751  #define RG_ADDA_CH1_SEL_MASK				0x3
2752  #define RG_ADDA_CH1_SEL_MASK_SFT			(0x3 << 0)
2753  
2754  /* AFE_PMIC_NEWIF_CFG3 */
2755  #define RG_UP8X_SYNC_WORD_SFT				0
2756  #define RG_UP8X_SYNC_WORD_MASK				0xffff
2757  #define RG_UP8X_SYNC_WORD_MASK_SFT			(0xffff << 0)
2758  
2759  /* AFE_NCP_CFG0 */
2760  #define  RG_NCP_CK1_VALID_CNT_SFT			9
2761  #define  RG_NCP_CK1_VALID_CNT_MASK			0x7f
2762  #define  RG_NCP_CK1_VALID_CNT_MASK_SFT			(0x7f << 9)
2763  #define RG_NCP_ADITH_SFT				8
2764  #define RG_NCP_ADITH_MASK				0x1
2765  #define RG_NCP_ADITH_MASK_SFT				(0x1 << 8)
2766  #define RG_NCP_DITHER_EN_SFT				7
2767  #define RG_NCP_DITHER_EN_MASK				0x1
2768  #define RG_NCP_DITHER_EN_MASK_SFT			(0x1 << 7)
2769  #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_SFT		4
2770  #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK		0x7
2771  #define RG_NCP_DITHER_FIXED_CK0_ACK1_2P_MASK_SFT	(0x7 << 4)
2772  #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_SFT		1
2773  #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK		0x7
2774  #define RG_NCP_DITHER_FIXED_CK0_ACK2_2P_MASK_SFT	(0x7 << 1)
2775  #define RG_NCP_ON_SFT					0
2776  #define RG_NCP_ON_MASK					0x1
2777  #define RG_NCP_ON_MASK_SFT				(0x1 << 0)
2778  
2779  /* AFE_NCP_CFG1 */
2780  #define RG_XY_VAL_CFG_EN_SFT				15
2781  #define RG_XY_VAL_CFG_EN_MASK				0x1
2782  #define RG_XY_VAL_CFG_EN_MASK_SFT			(0x1 << 15)
2783  #define RG_X_VAL_CFG_SFT				8
2784  #define RG_X_VAL_CFG_MASK				0x7f
2785  #define RG_X_VAL_CFG_MASK_SFT				(0x7f << 8)
2786  #define RG_Y_VAL_CFG_SFT				0
2787  #define RG_Y_VAL_CFG_MASK				0x7f
2788  #define RG_Y_VAL_CFG_MASK_SFT				(0x7f << 0)
2789  
2790  /* AFE_NCP_CFG2 */
2791  #define RG_NCP_NONCLK_SET_SFT				1
2792  #define RG_NCP_NONCLK_SET_MASK				0x1
2793  #define RG_NCP_NONCLK_SET_MASK_SFT			(0x1 << 1)
2794  #define RG_NCP_PDDIS_EN_SFT				0
2795  #define RG_NCP_PDDIS_EN_MASK				0x1
2796  #define RG_NCP_PDDIS_EN_MASK_SFT			(0x1 << 0)
2797  
2798  /* AUDENC_ANA_CON0 */
2799  #define RG_AUDPREAMPLON_SFT				0
2800  #define RG_AUDPREAMPLON_MASK				0x1
2801  #define RG_AUDPREAMPLON_MASK_SFT			(0x1 << 0)
2802  #define RG_AUDPREAMPLDCCEN_SFT				1
2803  #define RG_AUDPREAMPLDCCEN_MASK				0x1
2804  #define RG_AUDPREAMPLDCCEN_MASK_SFT			(0x1 << 1)
2805  #define RG_AUDPREAMPLDCPRECHARGE_SFT			2
2806  #define RG_AUDPREAMPLDCPRECHARGE_MASK			0x1
2807  #define RG_AUDPREAMPLDCPRECHARGE_MASK_SFT		(0x1 << 2)
2808  #define RG_AUDPREAMPLPGATEST_SFT			3
2809  #define RG_AUDPREAMPLPGATEST_MASK			0x1
2810  #define RG_AUDPREAMPLPGATEST_MASK_SFT			(0x1 << 3)
2811  #define RG_AUDPREAMPLVSCALE_SFT				4
2812  #define RG_AUDPREAMPLVSCALE_MASK			0x3
2813  #define RG_AUDPREAMPLVSCALE_MASK_SFT			(0x3 << 4)
2814  #define RG_AUDPREAMPLINPUTSEL_SFT			6
2815  #define RG_AUDPREAMPLINPUTSEL_MASK			0x3
2816  #define RG_AUDPREAMPLINPUTSEL_MASK_SFT			(0x3 << 6)
2817  #define RG_AUDPREAMPLGAIN_SFT				8
2818  #define RG_AUDPREAMPLGAIN_MASK				0x7
2819  #define RG_AUDPREAMPLGAIN_MASK_SFT			(0x7 << 8)
2820  #define RG_BULKL_VCM_EN_SFT				11
2821  #define RG_BULKL_VCM_EN_MASK				0x1
2822  #define RG_BULKL_VCM_EN_MASK_SFT			(0x1 << 11)
2823  #define RG_AUDADCLPWRUP_SFT				12
2824  #define RG_AUDADCLPWRUP_MASK				0x1
2825  #define RG_AUDADCLPWRUP_MASK_SFT			(0x1 << 12)
2826  #define RG_AUDADCLINPUTSEL_SFT				13
2827  #define RG_AUDADCLINPUTSEL_MASK				0x3
2828  #define RG_AUDADCLINPUTSEL_MASK_SFT			(0x3 << 13)
2829  
2830  /* AUDENC_ANA_CON1 */
2831  #define RG_AUDPREAMPRON_SFT				0
2832  #define RG_AUDPREAMPRON_MASK				0x1
2833  #define RG_AUDPREAMPRON_MASK_SFT			(0x1 << 0)
2834  #define RG_AUDPREAMPRDCCEN_SFT				1
2835  #define RG_AUDPREAMPRDCCEN_MASK				0x1
2836  #define RG_AUDPREAMPRDCCEN_MASK_SFT			(0x1 << 1)
2837  #define RG_AUDPREAMPRDCPRECHARGE_SFT			2
2838  #define RG_AUDPREAMPRDCPRECHARGE_MASK			0x1
2839  #define RG_AUDPREAMPRDCPRECHARGE_MASK_SFT		(0x1 << 2)
2840  #define RG_AUDPREAMPRPGATEST_SFT			3
2841  #define RG_AUDPREAMPRPGATEST_MASK			0x1
2842  #define RG_AUDPREAMPRPGATEST_MASK_SFT			(0x1 << 3)
2843  #define RG_AUDPREAMPRVSCALE_SFT				4
2844  #define RG_AUDPREAMPRVSCALE_MASK			0x3
2845  #define RG_AUDPREAMPRVSCALE_MASK_SFT			(0x3 << 4)
2846  #define RG_AUDPREAMPRINPUTSEL_SFT			6
2847  #define RG_AUDPREAMPRINPUTSEL_MASK			0x3
2848  #define RG_AUDPREAMPRINPUTSEL_MASK_SFT			(0x3 << 6)
2849  #define RG_AUDPREAMPRGAIN_SFT				8
2850  #define RG_AUDPREAMPRGAIN_MASK				0x7
2851  #define RG_AUDPREAMPRGAIN_MASK_SFT			(0x7 << 8)
2852  #define RG_BULKR_VCM_EN_SFT				11
2853  #define RG_BULKR_VCM_EN_MASK				0x1
2854  #define RG_BULKR_VCM_EN_MASK_SFT			(0x1 << 11)
2855  #define RG_AUDADCRPWRUP_SFT				12
2856  #define RG_AUDADCRPWRUP_MASK				0x1
2857  #define RG_AUDADCRPWRUP_MASK_SFT			(0x1 << 12)
2858  #define RG_AUDADCRINPUTSEL_SFT				13
2859  #define RG_AUDADCRINPUTSEL_MASK				0x3
2860  #define RG_AUDADCRINPUTSEL_MASK_SFT			(0x3 << 13)
2861  
2862  /* AUDENC_ANA_CON2 */
2863  #define RG_AUDPREAMP3ON_SFT				0
2864  #define RG_AUDPREAMP3ON_MASK				0x1
2865  #define RG_AUDPREAMP3ON_MASK_SFT			(0x1 << 0)
2866  #define RG_AUDPREAMP3DCCEN_SFT				1
2867  #define RG_AUDPREAMP3DCCEN_MASK				0x1
2868  #define RG_AUDPREAMP3DCCEN_MASK_SFT			(0x1 << 1)
2869  #define RG_AUDPREAMP3DCPRECHARGE_SFT			2
2870  #define RG_AUDPREAMP3DCPRECHARGE_MASK			0x1
2871  #define RG_AUDPREAMP3DCPRECHARGE_MASK_SFT		(0x1 << 2)
2872  #define RG_AUDPREAMP3PGATEST_SFT			3
2873  #define RG_AUDPREAMP3PGATEST_MASK			0x1
2874  #define RG_AUDPREAMP3PGATEST_MASK_SFT			(0x1 << 3)
2875  #define RG_AUDPREAMP3VSCALE_SFT				4
2876  #define RG_AUDPREAMP3VSCALE_MASK			0x3
2877  #define RG_AUDPREAMP3VSCALE_MASK_SFT			(0x3 << 4)
2878  #define RG_AUDPREAMP3INPUTSEL_SFT			6
2879  #define RG_AUDPREAMP3INPUTSEL_MASK			0x3
2880  #define RG_AUDPREAMP3INPUTSEL_MASK_SFT			(0x3 << 6)
2881  #define RG_AUDPREAMP3GAIN_SFT				8
2882  #define RG_AUDPREAMP3GAIN_MASK				0x7
2883  #define RG_AUDPREAMP3GAIN_MASK_SFT			(0x7 << 8)
2884  #define RG_BULK3_VCM_EN_SFT				11
2885  #define RG_BULK3_VCM_EN_MASK				0x1
2886  #define RG_BULK3_VCM_EN_MASK_SFT			(0x1 << 11)
2887  #define RG_AUDADC3PWRUP_SFT				12
2888  #define RG_AUDADC3PWRUP_MASK				0x1
2889  #define RG_AUDADC3PWRUP_MASK_SFT			(0x1 << 12)
2890  #define RG_AUDADC3INPUTSEL_SFT				13
2891  #define RG_AUDADC3INPUTSEL_MASK				0x3
2892  #define RG_AUDADC3INPUTSEL_MASK_SFT			(0x3 << 13)
2893  
2894  /* AUDENC_ANA_CON3 */
2895  #define RG_AUDULHALFBIAS_SFT				0
2896  #define RG_AUDULHALFBIAS_MASK				0x1
2897  #define RG_AUDULHALFBIAS_MASK_SFT			(0x1 << 0)
2898  #define RG_AUDGLBVOWLPWEN_SFT				1
2899  #define RG_AUDGLBVOWLPWEN_MASK				0x1
2900  #define RG_AUDGLBVOWLPWEN_MASK_SFT			(0x1 << 1)
2901  #define RG_AUDPREAMPLPEN_SFT				2
2902  #define RG_AUDPREAMPLPEN_MASK				0x1
2903  #define RG_AUDPREAMPLPEN_MASK_SFT			(0x1 << 2)
2904  #define RG_AUDADC1STSTAGELPEN_SFT			3
2905  #define RG_AUDADC1STSTAGELPEN_MASK			0x1
2906  #define RG_AUDADC1STSTAGELPEN_MASK_SFT			(0x1 << 3)
2907  #define RG_AUDADC2NDSTAGELPEN_SFT			4
2908  #define RG_AUDADC2NDSTAGELPEN_MASK			0x1
2909  #define RG_AUDADC2NDSTAGELPEN_MASK_SFT			(0x1 << 4)
2910  #define RG_AUDADCFLASHLPEN_SFT				5
2911  #define RG_AUDADCFLASHLPEN_MASK				0x1
2912  #define RG_AUDADCFLASHLPEN_MASK_SFT			(0x1 << 5)
2913  #define RG_AUDPREAMPIDDTEST_SFT				6
2914  #define RG_AUDPREAMPIDDTEST_MASK			0x3
2915  #define RG_AUDPREAMPIDDTEST_MASK_SFT			(0x3 << 6)
2916  #define RG_AUDADC1STSTAGEIDDTEST_SFT			8
2917  #define RG_AUDADC1STSTAGEIDDTEST_MASK			0x3
2918  #define RG_AUDADC1STSTAGEIDDTEST_MASK_SFT		(0x3 << 8)
2919  #define RG_AUDADC2NDSTAGEIDDTEST_SFT			10
2920  #define RG_AUDADC2NDSTAGEIDDTEST_MASK			0x3
2921  #define RG_AUDADC2NDSTAGEIDDTEST_MASK_SFT		(0x3 << 10)
2922  #define RG_AUDADCREFBUFIDDTEST_SFT			12
2923  #define RG_AUDADCREFBUFIDDTEST_MASK			0x3
2924  #define RG_AUDADCREFBUFIDDTEST_MASK_SFT			(0x3 << 12)
2925  #define RG_AUDADCFLASHIDDTEST_SFT			14
2926  #define RG_AUDADCFLASHIDDTEST_MASK			0x3
2927  #define RG_AUDADCFLASHIDDTEST_MASK_SFT			(0x3 << 14)
2928  
2929  /* AUDENC_ANA_CON4 */
2930  #define RG_AUDRULHALFBIAS_SFT				0
2931  #define RG_AUDRULHALFBIAS_MASK				0x1
2932  #define RG_AUDRULHALFBIAS_MASK_SFT			(0x1 << 0)
2933  #define RG_AUDGLBRVOWLPWEN_SFT				1
2934  #define RG_AUDGLBRVOWLPWEN_MASK				0x1
2935  #define RG_AUDGLBRVOWLPWEN_MASK_SFT			(0x1 << 1)
2936  #define RG_AUDRPREAMPLPEN_SFT				2
2937  #define RG_AUDRPREAMPLPEN_MASK				0x1
2938  #define RG_AUDRPREAMPLPEN_MASK_SFT			(0x1 << 2)
2939  #define RG_AUDRADC1STSTAGELPEN_SFT			3
2940  #define RG_AUDRADC1STSTAGELPEN_MASK			0x1
2941  #define RG_AUDRADC1STSTAGELPEN_MASK_SFT			(0x1 << 3)
2942  #define RG_AUDRADC2NDSTAGELPEN_SFT			4
2943  #define RG_AUDRADC2NDSTAGELPEN_MASK			0x1
2944  #define RG_AUDRADC2NDSTAGELPEN_MASK_SFT			(0x1 << 4)
2945  #define RG_AUDRADCFLASHLPEN_SFT				5
2946  #define RG_AUDRADCFLASHLPEN_MASK			0x1
2947  #define RG_AUDRADCFLASHLPEN_MASK_SFT			(0x1 << 5)
2948  #define RG_AUDRPREAMPIDDTEST_SFT			6
2949  #define RG_AUDRPREAMPIDDTEST_MASK			0x3
2950  #define RG_AUDRPREAMPIDDTEST_MASK_SFT			(0x3 << 6)
2951  #define RG_AUDRADC1STSTAGEIDDTEST_SFT			8
2952  #define RG_AUDRADC1STSTAGEIDDTEST_MASK			0x3
2953  #define RG_AUDRADC1STSTAGEIDDTEST_MASK_SFT		(0x3 << 8)
2954  #define RG_AUDRADC2NDSTAGEIDDTEST_SFT			10
2955  #define RG_AUDRADC2NDSTAGEIDDTEST_MASK			0x3
2956  #define RG_AUDRADC2NDSTAGEIDDTEST_MASK_SFT		(0x3 << 10)
2957  #define RG_AUDRADCREFBUFIDDTEST_SFT			12
2958  #define RG_AUDRADCREFBUFIDDTEST_MASK			0x3
2959  #define RG_AUDRADCREFBUFIDDTEST_MASK_SFT		(0x3 << 12)
2960  #define RG_AUDRADCFLASHIDDTEST_SFT			14
2961  #define RG_AUDRADCFLASHIDDTEST_MASK			0x3
2962  #define RG_AUDRADCFLASHIDDTEST_MASK_SFT			(0x3 << 14)
2963  
2964  /* AUDENC_ANA_CON5 */
2965  #define RG_AUDADCCLKRSTB_SFT				0
2966  #define RG_AUDADCCLKRSTB_MASK				0x1
2967  #define RG_AUDADCCLKRSTB_MASK_SFT			(0x1 << 0)
2968  #define RG_AUDADCCLKSEL_SFT				1
2969  #define RG_AUDADCCLKSEL_MASK				0x3
2970  #define RG_AUDADCCLKSEL_MASK_SFT			(0x3 << 1)
2971  #define RG_AUDADCCLKSOURCE_SFT				3
2972  #define RG_AUDADCCLKSOURCE_MASK				0x3
2973  #define RG_AUDADCCLKSOURCE_MASK_SFT			(0x3 << 3)
2974  #define RG_AUDADCCLKGENMODE_SFT				5
2975  #define RG_AUDADCCLKGENMODE_MASK			0x3
2976  #define RG_AUDADCCLKGENMODE_MASK_SFT			(0x3 << 5)
2977  #define RG_AUDPREAMP_ACCFS_SFT				7
2978  #define RG_AUDPREAMP_ACCFS_MASK				0x1
2979  #define RG_AUDPREAMP_ACCFS_MASK_SFT			(0x1 << 7)
2980  #define RG_AUDPREAMPAAFEN_SFT				8
2981  #define RG_AUDPREAMPAAFEN_MASK				0x1
2982  #define RG_AUDPREAMPAAFEN_MASK_SFT			(0x1 << 8)
2983  #define RG_DCCVCMBUFLPMODSEL_SFT			9
2984  #define RG_DCCVCMBUFLPMODSEL_MASK			0x1
2985  #define RG_DCCVCMBUFLPMODSEL_MASK_SFT			(0x1 << 9)
2986  #define RG_DCCVCMBUFLPSWEN_SFT				10
2987  #define RG_DCCVCMBUFLPSWEN_MASK				0x1
2988  #define RG_DCCVCMBUFLPSWEN_MASK_SFT			(0x1 << 10)
2989  #define RG_AUDSPAREPGA_SFT				11
2990  #define RG_AUDSPAREPGA_MASK				0x1f
2991  #define RG_AUDSPAREPGA_MASK_SFT				(0x1f << 11)
2992  
2993  /* AUDENC_ANA_CON6 */
2994  #define RG_AUDADC1STSTAGESDENB_SFT			0
2995  #define RG_AUDADC1STSTAGESDENB_MASK			0x1
2996  #define RG_AUDADC1STSTAGESDENB_MASK_SFT			(0x1 << 0)
2997  #define RG_AUDADC2NDSTAGERESET_SFT			1
2998  #define RG_AUDADC2NDSTAGERESET_MASK			0x1
2999  #define RG_AUDADC2NDSTAGERESET_MASK_SFT			(0x1 << 1)
3000  #define RG_AUDADC3RDSTAGERESET_SFT			2
3001  #define RG_AUDADC3RDSTAGERESET_MASK			0x1
3002  #define RG_AUDADC3RDSTAGERESET_MASK_SFT			(0x1 << 2)
3003  #define RG_AUDADCFSRESET_SFT				3
3004  #define RG_AUDADCFSRESET_MASK				0x1
3005  #define RG_AUDADCFSRESET_MASK_SFT			(0x1 << 3)
3006  #define RG_AUDADCWIDECM_SFT				4
3007  #define RG_AUDADCWIDECM_MASK				0x1
3008  #define RG_AUDADCWIDECM_MASK_SFT			(0x1 << 4)
3009  #define RG_AUDADCNOPATEST_SFT				5
3010  #define RG_AUDADCNOPATEST_MASK				0x1
3011  #define RG_AUDADCNOPATEST_MASK_SFT			(0x1 << 5)
3012  #define RG_AUDADCBYPASS_SFT				6
3013  #define RG_AUDADCBYPASS_MASK				0x1
3014  #define RG_AUDADCBYPASS_MASK_SFT			(0x1 << 6)
3015  #define RG_AUDADCFFBYPASS_SFT				7
3016  #define RG_AUDADCFFBYPASS_MASK				0x1
3017  #define RG_AUDADCFFBYPASS_MASK_SFT			(0x1 << 7)
3018  #define RG_AUDADCDACFBCURRENT_SFT			8
3019  #define RG_AUDADCDACFBCURRENT_MASK			0x1
3020  #define RG_AUDADCDACFBCURRENT_MASK_SFT			(0x1 << 8)
3021  #define RG_AUDADCDACIDDTEST_SFT				9
3022  #define RG_AUDADCDACIDDTEST_MASK			0x3
3023  #define RG_AUDADCDACIDDTEST_MASK_SFT			(0x3 << 9)
3024  #define RG_AUDADCDACNRZ_SFT				11
3025  #define RG_AUDADCDACNRZ_MASK				0x1
3026  #define RG_AUDADCDACNRZ_MASK_SFT			(0x1 << 11)
3027  #define RG_AUDADCNODEM_SFT				12
3028  #define RG_AUDADCNODEM_MASK				0x1
3029  #define RG_AUDADCNODEM_MASK_SFT				(0x1 << 12)
3030  #define RG_AUDADCDACTEST_SFT				13
3031  #define RG_AUDADCDACTEST_MASK				0x1
3032  #define RG_AUDADCDACTEST_MASK_SFT			(0x1 << 13)
3033  #define RG_AUDADCDAC0P25FS_SFT				14
3034  #define RG_AUDADCDAC0P25FS_MASK				0x1
3035  #define RG_AUDADCDAC0P25FS_MASK_SFT			(0x1 << 14)
3036  #define RG_AUDADCRDAC0P25FS_SFT				15
3037  #define RG_AUDADCRDAC0P25FS_MASK			0x1
3038  #define RG_AUDADCRDAC0P25FS_MASK_SFT			(0x1 << 15)
3039  
3040  /* AUDENC_ANA_CON7 */
3041  #define RG_AUDADCTESTDATA_SFT				0
3042  #define RG_AUDADCTESTDATA_MASK				0xffff
3043  #define RG_AUDADCTESTDATA_MASK_SFT			(0xffff << 0)
3044  
3045  /* AUDENC_ANA_CON8 */
3046  #define RG_AUDRCTUNEL_SFT				0
3047  #define RG_AUDRCTUNEL_MASK				0x1f
3048  #define RG_AUDRCTUNEL_MASK_SFT				(0x1f << 0)
3049  #define RG_AUDRCTUNELSEL_SFT				5
3050  #define RG_AUDRCTUNELSEL_MASK				0x1
3051  #define RG_AUDRCTUNELSEL_MASK_SFT			(0x1 << 5)
3052  #define RG_AUDRCTUNER_SFT				8
3053  #define RG_AUDRCTUNER_MASK				0x1f
3054  #define RG_AUDRCTUNER_MASK_SFT				(0x1f << 8)
3055  #define RG_AUDRCTUNERSEL_SFT				13
3056  #define RG_AUDRCTUNERSEL_MASK				0x1
3057  #define RG_AUDRCTUNERSEL_MASK_SFT			(0x1 << 13)
3058  
3059  /* AUDENC_ANA_CON9 */
3060  #define RG_AUD3CTUNEL_SFT				0
3061  #define RG_AUD3CTUNEL_MASK				0x1f
3062  #define RG_AUD3CTUNEL_MASK_SFT				(0x1f << 0)
3063  #define RG_AUD3CTUNELSEL_SFT				5
3064  #define RG_AUD3CTUNELSEL_MASK				0x1
3065  #define RG_AUD3CTUNELSEL_MASK_SFT			(0x1 << 5)
3066  #define RGS_AUDRCTUNE3READ_SFT				6
3067  #define RGS_AUDRCTUNE3READ_MASK				0x1f
3068  #define RGS_AUDRCTUNE3READ_MASK_SFT			(0x1f << 6)
3069  #define RG_AUD3SPARE_SFT				11
3070  #define RG_AUD3SPARE_MASK				0x1f
3071  #define RG_AUD3SPARE_MASK_SFT				(0x1f << 11)
3072  
3073  /* AUDENC_ANA_CON10 */
3074  #define RGS_AUDRCTUNELREAD_SFT				0
3075  #define RGS_AUDRCTUNELREAD_MASK				0x1f
3076  #define RGS_AUDRCTUNELREAD_MASK_SFT			(0x1f << 0)
3077  #define RGS_AUDRCTUNERREAD_SFT				8
3078  #define RGS_AUDRCTUNERREAD_MASK				0x1f
3079  #define RGS_AUDRCTUNERREAD_MASK_SFT			(0x1f << 8)
3080  
3081  /* AUDENC_ANA_CON11 */
3082  #define RG_AUDSPAREVA30_SFT				0
3083  #define RG_AUDSPAREVA30_MASK				0xff
3084  #define RG_AUDSPAREVA30_MASK_SFT			(0xff << 0)
3085  #define RG_AUDSPAREVA18_SFT				8
3086  #define RG_AUDSPAREVA18_MASK				0xff
3087  #define RG_AUDSPAREVA18_MASK_SFT			(0xff << 8)
3088  
3089  /* AUDENC_ANA_CON12 */
3090  #define RG_AUDPGA_DECAP_SFT				0
3091  #define RG_AUDPGA_DECAP_MASK				0x1
3092  #define RG_AUDPGA_DECAP_MASK_SFT			(0x1 << 0)
3093  #define RG_AUDPGA_CAPRA_SFT				1
3094  #define RG_AUDPGA_CAPRA_MASK				0x1
3095  #define RG_AUDPGA_CAPRA_MASK_SFT			(0x1 << 1)
3096  #define RG_AUDPGA_ACCCMP_SFT				2
3097  #define RG_AUDPGA_ACCCMP_MASK				0x1
3098  #define RG_AUDPGA_ACCCMP_MASK_SFT			(0x1 << 2)
3099  #define RG_AUDENC_SPARE2_SFT				3
3100  #define RG_AUDENC_SPARE2_MASK				0x1fff
3101  #define RG_AUDENC_SPARE2_MASK_SFT			(0x1fff << 3)
3102  
3103  /* AUDENC_ANA_CON13 */
3104  #define RG_AUDDIGMICEN_SFT				0
3105  #define RG_AUDDIGMICEN_MASK				0x1
3106  #define RG_AUDDIGMICEN_MASK_SFT				(0x1 << 0)
3107  #define RG_AUDDIGMICBIAS_SFT				1
3108  #define RG_AUDDIGMICBIAS_MASK				0x3
3109  #define RG_AUDDIGMICBIAS_MASK_SFT			(0x3 << 1)
3110  #define RG_DMICHPCLKEN_SFT				3
3111  #define RG_DMICHPCLKEN_MASK				0x1
3112  #define RG_DMICHPCLKEN_MASK_SFT				(0x1 << 3)
3113  #define RG_AUDDIGMICPDUTY_SFT				4
3114  #define RG_AUDDIGMICPDUTY_MASK				0x3
3115  #define RG_AUDDIGMICPDUTY_MASK_SFT			(0x3 << 4)
3116  #define RG_AUDDIGMICNDUTY_SFT				6
3117  #define RG_AUDDIGMICNDUTY_MASK				0x3
3118  #define RG_AUDDIGMICNDUTY_MASK_SFT			(0x3 << 6)
3119  #define RG_DMICMONEN_SFT				8
3120  #define RG_DMICMONEN_MASK				0x1
3121  #define RG_DMICMONEN_MASK_SFT				(0x1 << 8)
3122  #define RG_DMICMONSEL_SFT				9
3123  #define RG_DMICMONSEL_MASK				0x7
3124  #define RG_DMICMONSEL_MASK_SFT				(0x7 << 9)
3125  
3126  /* AUDENC_ANA_CON14 */
3127  #define RG_AUDDIGMIC1EN_SFT				0
3128  #define RG_AUDDIGMIC1EN_MASK				0x1
3129  #define RG_AUDDIGMIC1EN_MASK_SFT			(0x1 << 0)
3130  #define RG_AUDDIGMICBIAS1_SFT				1
3131  #define RG_AUDDIGMICBIAS1_MASK				0x3
3132  #define RG_AUDDIGMICBIAS1_MASK_SFT			(0x3 << 1)
3133  #define RG_DMIC1HPCLKEN_SFT				3
3134  #define RG_DMIC1HPCLKEN_MASK				0x1
3135  #define RG_DMIC1HPCLKEN_MASK_SFT			(0x1 << 3)
3136  #define RG_AUDDIGMIC1PDUTY_SFT				4
3137  #define RG_AUDDIGMIC1PDUTY_MASK				0x3
3138  #define RG_AUDDIGMIC1PDUTY_MASK_SFT			(0x3 << 4)
3139  #define RG_AUDDIGMIC1NDUTY_SFT				6
3140  #define RG_AUDDIGMIC1NDUTY_MASK				0x3
3141  #define RG_AUDDIGMIC1NDUTY_MASK_SFT			(0x3 << 6)
3142  #define RG_DMIC1MONEN_SFT				8
3143  #define RG_DMIC1MONEN_MASK				0x1
3144  #define RG_DMIC1MONEN_MASK_SFT				(0x1 << 8)
3145  #define RG_DMIC1MONSEL_SFT				9
3146  #define RG_DMIC1MONSEL_MASK				0x7
3147  #define RG_DMIC1MONSEL_MASK_SFT				(0x7 << 9)
3148  #define RG_AUDSPAREVMIC_SFT				12
3149  #define RG_AUDSPAREVMIC_MASK				0xf
3150  #define RG_AUDSPAREVMIC_MASK_SFT			(0xf << 12)
3151  
3152  /* AUDENC_ANA_CON15 */
3153  #define RG_AUDPWDBMICBIAS0_SFT				0
3154  #define RG_AUDPWDBMICBIAS0_MASK				0x1
3155  #define RG_AUDPWDBMICBIAS0_MASK_SFT			(0x1 << 0)
3156  #define RG_AUDMICBIAS0BYPASSEN_SFT			1
3157  #define RG_AUDMICBIAS0BYPASSEN_MASK			0x1
3158  #define RG_AUDMICBIAS0BYPASSEN_MASK_SFT			(0x1 << 1)
3159  #define RG_AUDMICBIAS0LOWPEN_SFT			2
3160  #define RG_AUDMICBIAS0LOWPEN_MASK			0x1
3161  #define RG_AUDMICBIAS0LOWPEN_MASK_SFT			(0x1 << 2)
3162  #define RG_AUDPWDBMICBIAS3_SFT				3
3163  #define RG_AUDPWDBMICBIAS3_MASK				0x1
3164  #define RG_AUDPWDBMICBIAS3_MASK_SFT			(0x1 << 3)
3165  #define RG_AUDMICBIAS0VREF_SFT				4
3166  #define RG_AUDMICBIAS0VREF_MASK				0x7
3167  #define RG_AUDMICBIAS0VREF_MASK_SFT			(0x7 << 4)
3168  #define RG_AUDMICBIAS0DCSW0P1EN_SFT			8
3169  #define RG_AUDMICBIAS0DCSW0P1EN_MASK			0x1
3170  #define RG_AUDMICBIAS0DCSW0P1EN_MASK_SFT		(0x1 << 8)
3171  #define RG_AUDMICBIAS0DCSW0P2EN_SFT			9
3172  #define RG_AUDMICBIAS0DCSW0P2EN_MASK			0x1
3173  #define RG_AUDMICBIAS0DCSW0P2EN_MASK_SFT		(0x1 << 9)
3174  #define RG_AUDMICBIAS0DCSW0NEN_SFT			10
3175  #define RG_AUDMICBIAS0DCSW0NEN_MASK			0x1
3176  #define RG_AUDMICBIAS0DCSW0NEN_MASK_SFT			(0x1 << 10)
3177  #define RG_AUDMICBIAS0DCSW2P1EN_SFT			12
3178  #define RG_AUDMICBIAS0DCSW2P1EN_MASK			0x1
3179  #define RG_AUDMICBIAS0DCSW2P1EN_MASK_SFT		(0x1 << 12)
3180  #define RG_AUDMICBIAS0DCSW2P2EN_SFT			13
3181  #define RG_AUDMICBIAS0DCSW2P2EN_MASK			0x1
3182  #define RG_AUDMICBIAS0DCSW2P2EN_MASK_SFT		(0x1 << 13)
3183  #define RG_AUDMICBIAS0DCSW2NEN_SFT			14
3184  #define RG_AUDMICBIAS0DCSW2NEN_MASK			0x1
3185  #define RG_AUDMICBIAS0DCSW2NEN_MASK_SFT			(0x1 << 14)
3186  
3187  /* AUDENC_ANA_CON16 */
3188  #define RG_AUDPWDBMICBIAS1_SFT				0
3189  #define RG_AUDPWDBMICBIAS1_MASK				0x1
3190  #define RG_AUDPWDBMICBIAS1_MASK_SFT			(0x1 << 0)
3191  #define RG_AUDMICBIAS1BYPASSEN_SFT			1
3192  #define RG_AUDMICBIAS1BYPASSEN_MASK			0x1
3193  #define RG_AUDMICBIAS1BYPASSEN_MASK_SFT			(0x1 << 1)
3194  #define RG_AUDMICBIAS1LOWPEN_SFT			2
3195  #define RG_AUDMICBIAS1LOWPEN_MASK			0x1
3196  #define RG_AUDMICBIAS1LOWPEN_MASK_SFT			(0x1 << 2)
3197  #define RG_AUDMICBIAS1VREF_SFT				4
3198  #define RG_AUDMICBIAS1VREF_MASK				0x7
3199  #define RG_AUDMICBIAS1VREF_MASK_SFT			(0x7 << 4)
3200  #define RG_AUDMICBIAS1DCSW1PEN_SFT			8
3201  #define RG_AUDMICBIAS1DCSW1PEN_MASK			0x1
3202  #define RG_AUDMICBIAS1DCSW1PEN_MASK_SFT			(0x1 << 8)
3203  #define RG_AUDMICBIAS1DCSW1NEN_SFT			9
3204  #define RG_AUDMICBIAS1DCSW1NEN_MASK			0x1
3205  #define RG_AUDMICBIAS1DCSW1NEN_MASK_SFT			(0x1 << 9)
3206  #define RG_BANDGAPGEN_SFT				10
3207  #define RG_BANDGAPGEN_MASK				0x1
3208  #define RG_BANDGAPGEN_MASK_SFT				(0x1 << 10)
3209  #define RG_AUDMICBIAS1HVEN_SFT				12
3210  #define RG_AUDMICBIAS1HVEN_MASK				0x1
3211  #define RG_AUDMICBIAS1HVEN_MASK_SFT			(0x1 << 12)
3212  #define RG_AUDMICBIAS1HVVREF_SFT			13
3213  #define RG_AUDMICBIAS1HVVREF_MASK			0x1
3214  #define RG_AUDMICBIAS1HVVREF_MASK_SFT			(0x1 << 13)
3215  
3216  /* AUDENC_ANA_CON17 */
3217  #define RG_AUDPWDBMICBIAS2_SFT				0
3218  #define RG_AUDPWDBMICBIAS2_MASK				0x1
3219  #define RG_AUDPWDBMICBIAS2_MASK_SFT			(0x1 << 0)
3220  #define RG_AUDMICBIAS2BYPASSEN_SFT			1
3221  #define RG_AUDMICBIAS2BYPASSEN_MASK			0x1
3222  #define RG_AUDMICBIAS2BYPASSEN_MASK_SFT			(0x1 << 1)
3223  #define RG_AUDMICBIAS2LOWPEN_SFT			2
3224  #define RG_AUDMICBIAS2LOWPEN_MASK			0x1
3225  #define RG_AUDMICBIAS2LOWPEN_MASK_SFT			(0x1 << 2)
3226  #define RG_AUDMICBIAS2VREF_SFT				4
3227  #define RG_AUDMICBIAS2VREF_MASK				0x7
3228  #define RG_AUDMICBIAS2VREF_MASK_SFT			(0x7 << 4)
3229  #define RG_AUDMICBIAS2DCSW3P1EN_SFT			8
3230  #define RG_AUDMICBIAS2DCSW3P1EN_MASK			0x1
3231  #define RG_AUDMICBIAS2DCSW3P1EN_MASK_SFT		(0x1 << 8)
3232  #define RG_AUDMICBIAS2DCSW3P2EN_SFT			9
3233  #define RG_AUDMICBIAS2DCSW3P2EN_MASK			0x1
3234  #define RG_AUDMICBIAS2DCSW3P2EN_MASK_SFT		(0x1 << 9)
3235  #define RG_AUDMICBIAS2DCSW3NEN_SFT			10
3236  #define RG_AUDMICBIAS2DCSW3NEN_MASK			0x1
3237  #define RG_AUDMICBIAS2DCSW3NEN_MASK_SFT			(0x1 << 10)
3238  #define RG_AUDMICBIASSPARE_SFT				12
3239  #define RG_AUDMICBIASSPARE_MASK				0xf
3240  #define RG_AUDMICBIASSPARE_MASK_SFT			(0xf << 12)
3241  
3242  /* AUDENC_ANA_CON18 */
3243  #define RG_AUDACCDETMICBIAS0PULLLOW_SFT			0
3244  #define RG_AUDACCDETMICBIAS0PULLLOW_MASK		0x1
3245  #define RG_AUDACCDETMICBIAS0PULLLOW_MASK_SFT		(0x1 << 0)
3246  #define RG_AUDACCDETMICBIAS1PULLLOW_SFT			1
3247  #define RG_AUDACCDETMICBIAS1PULLLOW_MASK		0x1
3248  #define RG_AUDACCDETMICBIAS1PULLLOW_MASK_SFT		(0x1 << 1)
3249  #define RG_AUDACCDETMICBIAS2PULLLOW_SFT			2
3250  #define RG_AUDACCDETMICBIAS2PULLLOW_MASK		0x1
3251  #define RG_AUDACCDETMICBIAS2PULLLOW_MASK_SFT		(0x1 << 2)
3252  #define RG_AUDACCDETVIN1PULLLOW_SFT			3
3253  #define RG_AUDACCDETVIN1PULLLOW_MASK			0x1
3254  #define RG_AUDACCDETVIN1PULLLOW_MASK_SFT		(0x1 << 3)
3255  #define RG_AUDACCDETVTHACAL_SFT				4
3256  #define RG_AUDACCDETVTHACAL_MASK			0x1
3257  #define RG_AUDACCDETVTHACAL_MASK_SFT			(0x1 << 4)
3258  #define RG_AUDACCDETVTHBCAL_SFT				5
3259  #define RG_AUDACCDETVTHBCAL_MASK			0x1
3260  #define RG_AUDACCDETVTHBCAL_MASK_SFT			(0x1 << 5)
3261  #define RG_AUDACCDETTVDET_SFT				6
3262  #define RG_AUDACCDETTVDET_MASK				0x1
3263  #define RG_AUDACCDETTVDET_MASK_SFT			(0x1 << 6)
3264  #define RG_ACCDETSEL_SFT				7
3265  #define RG_ACCDETSEL_MASK				0x1
3266  #define RG_ACCDETSEL_MASK_SFT				(0x1 << 7)
3267  #define RG_SWBUFMODSEL_SFT				8
3268  #define RG_SWBUFMODSEL_MASK				0x1
3269  #define RG_SWBUFMODSEL_MASK_SFT				(0x1 << 8)
3270  #define RG_SWBUFSWEN_SFT				9
3271  #define RG_SWBUFSWEN_MASK				0x1
3272  #define RG_SWBUFSWEN_MASK_SFT				(0x1 << 9)
3273  #define RG_EINT0NOHYS_SFT				10
3274  #define RG_EINT0NOHYS_MASK				0x1
3275  #define RG_EINT0NOHYS_MASK_SFT				(0x1 << 10)
3276  #define RG_EINT0CONFIGACCDET_SFT			11
3277  #define RG_EINT0CONFIGACCDET_MASK			0x1
3278  #define RG_EINT0CONFIGACCDET_MASK_SFT			(0x1 << 11)
3279  #define RG_EINT0HIRENB_SFT				12
3280  #define RG_EINT0HIRENB_MASK				0x1
3281  #define RG_EINT0HIRENB_MASK_SFT				(0x1 << 12)
3282  #define RG_ACCDET2AUXRESBYPASS_SFT			13
3283  #define RG_ACCDET2AUXRESBYPASS_MASK			0x1
3284  #define RG_ACCDET2AUXRESBYPASS_MASK_SFT			(0x1 << 13)
3285  #define RG_ACCDET2AUXSWEN_SFT				14
3286  #define RG_ACCDET2AUXSWEN_MASK				0x1
3287  #define RG_ACCDET2AUXSWEN_MASK_SFT			(0x1 << 14)
3288  #define RG_AUDACCDETMICBIAS3PULLLOW_SFT			15
3289  #define RG_AUDACCDETMICBIAS3PULLLOW_MASK		0x1
3290  #define RG_AUDACCDETMICBIAS3PULLLOW_MASK_SFT		(0x1 << 15)
3291  
3292  /* AUDENC_ANA_CON19 */
3293  #define RG_EINT1CONFIGACCDET_SFT			0
3294  #define RG_EINT1CONFIGACCDET_MASK			0x1
3295  #define RG_EINT1CONFIGACCDET_MASK_SFT			(0x1 << 0)
3296  #define RG_EINT1HIRENB_SFT				1
3297  #define RG_EINT1HIRENB_MASK				0x1
3298  #define RG_EINT1HIRENB_MASK_SFT				(0x1 << 1)
3299  #define RG_EINT1NOHYS_SFT				2
3300  #define RG_EINT1NOHYS_MASK				0x1
3301  #define RG_EINT1NOHYS_MASK_SFT				(0x1 << 2)
3302  #define RG_EINTCOMPVTH_SFT				4
3303  #define RG_EINTCOMPVTH_MASK				0xf
3304  #define RG_EINTCOMPVTH_MASK_SFT				(0xf << 4)
3305  #define RG_MTEST_EN_SFT					8
3306  #define RG_MTEST_EN_MASK				0x1
3307  #define RG_MTEST_EN_MASK_SFT				(0x1 << 8)
3308  #define RG_MTEST_SEL_SFT				9
3309  #define RG_MTEST_SEL_MASK				0x1
3310  #define RG_MTEST_SEL_MASK_SFT				(0x1 << 9)
3311  #define RG_MTEST_CURRENT_SFT				10
3312  #define RG_MTEST_CURRENT_MASK				0x1
3313  #define RG_MTEST_CURRENT_MASK_SFT			(0x1 << 10)
3314  #define RG_ANALOGFDEN_SFT				12
3315  #define RG_ANALOGFDEN_MASK				0x1
3316  #define RG_ANALOGFDEN_MASK_SFT				(0x1 << 12)
3317  #define RG_FDVIN1PPULLLOW_SFT				13
3318  #define RG_FDVIN1PPULLLOW_MASK				0x1
3319  #define RG_FDVIN1PPULLLOW_MASK_SFT			(0x1 << 13)
3320  #define RG_FDEINT0TYPE_SFT				14
3321  #define RG_FDEINT0TYPE_MASK				0x1
3322  #define RG_FDEINT0TYPE_MASK_SFT				(0x1 << 14)
3323  #define RG_FDEINT1TYPE_SFT				15
3324  #define RG_FDEINT1TYPE_MASK				0x1
3325  #define RG_FDEINT1TYPE_MASK_SFT				(0x1 << 15)
3326  
3327  /* AUDENC_ANA_CON20 */
3328  #define RG_EINT0CMPEN_SFT				0
3329  #define RG_EINT0CMPEN_MASK				0x1
3330  #define RG_EINT0CMPEN_MASK_SFT				(0x1 << 0)
3331  #define RG_EINT0CMPMEN_SFT				1
3332  #define RG_EINT0CMPMEN_MASK				0x1
3333  #define RG_EINT0CMPMEN_MASK_SFT				(0x1 << 1)
3334  #define RG_EINT0EN_SFT					2
3335  #define RG_EINT0EN_MASK					0x1
3336  #define RG_EINT0EN_MASK_SFT				(0x1 << 2)
3337  #define RG_EINT0CEN_SFT					3
3338  #define RG_EINT0CEN_MASK				0x1
3339  #define RG_EINT0CEN_MASK_SFT				(0x1 << 3)
3340  #define RG_EINT0INVEN_SFT				4
3341  #define RG_EINT0INVEN_MASK				0x1
3342  #define RG_EINT0INVEN_MASK_SFT				(0x1 << 4)
3343  #define RG_EINT0CTURBO_SFT				5
3344  #define RG_EINT0CTURBO_MASK				0x7
3345  #define RG_EINT0CTURBO_MASK_SFT				(0x7 << 5)
3346  #define RG_EINT1CMPEN_SFT				8
3347  #define RG_EINT1CMPEN_MASK				0x1
3348  #define RG_EINT1CMPEN_MASK_SFT				(0x1 << 8)
3349  #define RG_EINT1CMPMEN_SFT				9
3350  #define RG_EINT1CMPMEN_MASK				0x1
3351  #define RG_EINT1CMPMEN_MASK_SFT				(0x1 << 9)
3352  #define RG_EINT1EN_SFT					10
3353  #define RG_EINT1EN_MASK					0x1
3354  #define RG_EINT1EN_MASK_SFT				(0x1 << 10)
3355  #define RG_EINT1CEN_SFT					11
3356  #define RG_EINT1CEN_MASK				0x1
3357  #define RG_EINT1CEN_MASK_SFT				(0x1 << 11)
3358  #define RG_EINT1INVEN_SFT				12
3359  #define RG_EINT1INVEN_MASK				0x1
3360  #define RG_EINT1INVEN_MASK_SFT				(0x1 << 12)
3361  #define RG_EINT1CTURBO_SFT				13
3362  #define RG_EINT1CTURBO_MASK				0x7
3363  #define RG_EINT1CTURBO_MASK_SFT				(0x7 << 13)
3364  
3365  /* AUDENC_ANA_CON21 */
3366  #define RG_ACCDETSPARE_SFT				0
3367  #define RG_ACCDETSPARE_MASK				0xffff
3368  #define RG_ACCDETSPARE_MASK_SFT				(0xffff << 0)
3369  
3370  /* AUDENC_ANA_CON22 */
3371  #define RG_AUDENCSPAREVA30_SFT				0
3372  #define RG_AUDENCSPAREVA30_MASK				0xff
3373  #define RG_AUDENCSPAREVA30_MASK_SFT			(0xff << 0)
3374  #define RG_AUDENCSPAREVA18_SFT				8
3375  #define RG_AUDENCSPAREVA18_MASK				0xff
3376  #define RG_AUDENCSPAREVA18_MASK_SFT			(0xff << 8)
3377  
3378  /* AUDENC_ANA_CON23 */
3379  #define RG_CLKSQ_EN_SFT					0
3380  #define RG_CLKSQ_EN_MASK				0x1
3381  #define RG_CLKSQ_EN_MASK_SFT				(0x1 << 0)
3382  #define RG_CLKSQ_IN_SEL_TEST_SFT			1
3383  #define RG_CLKSQ_IN_SEL_TEST_MASK			0x1
3384  #define RG_CLKSQ_IN_SEL_TEST_MASK_SFT			(0x1 << 1)
3385  #define RG_CM_REFGENSEL_SFT				2
3386  #define RG_CM_REFGENSEL_MASK				0x1
3387  #define RG_CM_REFGENSEL_MASK_SFT			(0x1 << 2)
3388  #define RG_AUDIO_VOW_EN_SFT				3
3389  #define RG_AUDIO_VOW_EN_MASK				0x1
3390  #define RG_AUDIO_VOW_EN_MASK_SFT			(0x1 << 3)
3391  #define RG_CLKSQ_EN_VOW_SFT				4
3392  #define RG_CLKSQ_EN_VOW_MASK				0x1
3393  #define RG_CLKSQ_EN_VOW_MASK_SFT			(0x1 << 4)
3394  #define RG_CLKAND_EN_VOW_SFT				5
3395  #define RG_CLKAND_EN_VOW_MASK				0x1
3396  #define RG_CLKAND_EN_VOW_MASK_SFT			(0x1 << 5)
3397  #define RG_VOWCLK_SEL_EN_VOW_SFT			6
3398  #define RG_VOWCLK_SEL_EN_VOW_MASK			0x1
3399  #define RG_VOWCLK_SEL_EN_VOW_MASK_SFT			(0x1 << 6)
3400  #define RG_SPARE_VOW_SFT				7
3401  #define RG_SPARE_VOW_MASK				0x7
3402  #define RG_SPARE_VOW_MASK_SFT				(0x7 << 7)
3403  
3404  /* AUDDEC_ANA_CON0 */
3405  #define RG_AUDDACLPWRUP_VAUDP32_SFT			0
3406  #define RG_AUDDACLPWRUP_VAUDP32_MASK			0x1
3407  #define RG_AUDDACLPWRUP_VAUDP32_MASK_SFT		(0x1 << 0)
3408  #define RG_AUDDACRPWRUP_VAUDP32_SFT			1
3409  #define RG_AUDDACRPWRUP_VAUDP32_MASK			0x1
3410  #define RG_AUDDACRPWRUP_VAUDP32_MASK_SFT		(0x1 << 1)
3411  #define RG_AUD_DAC_PWR_UP_VA32_SFT			2
3412  #define RG_AUD_DAC_PWR_UP_VA32_MASK			0x1
3413  #define RG_AUD_DAC_PWR_UP_VA32_MASK_SFT			(0x1 << 2)
3414  #define RG_AUD_DAC_PWL_UP_VA32_SFT			3
3415  #define RG_AUD_DAC_PWL_UP_VA32_MASK			0x1
3416  #define RG_AUD_DAC_PWL_UP_VA32_MASK_SFT			(0x1 << 3)
3417  #define RG_AUDHPLPWRUP_VAUDP32_SFT			4
3418  #define RG_AUDHPLPWRUP_VAUDP32_MASK			0x1
3419  #define RG_AUDHPLPWRUP_VAUDP32_MASK_SFT			(0x1 << 4)
3420  #define RG_AUDHPRPWRUP_VAUDP32_SFT			5
3421  #define RG_AUDHPRPWRUP_VAUDP32_MASK			0x1
3422  #define RG_AUDHPRPWRUP_VAUDP32_MASK_SFT			(0x1 << 5)
3423  #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_SFT		6
3424  #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK		0x1
3425  #define RG_AUDHPLPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 6)
3426  #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_SFT		7
3427  #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK		0x1
3428  #define RG_AUDHPRPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 7)
3429  #define RG_AUDHPLMUXINPUTSEL_VAUDP32_SFT		8
3430  #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK		0x3
3431  #define RG_AUDHPLMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 8)
3432  #define RG_AUDHPRMUXINPUTSEL_VAUDP32_SFT		10
3433  #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK		0x3
3434  #define RG_AUDHPRMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 10)
3435  #define RG_AUDHPLSCDISABLE_VAUDP32_SFT			12
3436  #define RG_AUDHPLSCDISABLE_VAUDP32_MASK			0x1
3437  #define RG_AUDHPLSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 12)
3438  #define RG_AUDHPRSCDISABLE_VAUDP32_SFT			13
3439  #define RG_AUDHPRSCDISABLE_VAUDP32_MASK			0x1
3440  #define RG_AUDHPRSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 13)
3441  #define RG_AUDHPLBSCCURRENT_VAUDP32_SFT			14
3442  #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK		0x1
3443  #define RG_AUDHPLBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 14)
3444  #define RG_AUDHPRBSCCURRENT_VAUDP32_SFT			15
3445  #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK		0x1
3446  #define RG_AUDHPRBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 15)
3447  
3448  /* AUDDEC_ANA_CON1 */
3449  #define RG_AUDHPLOUTPWRUP_VAUDP32_SFT			0
3450  #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK			0x1
3451  #define RG_AUDHPLOUTPWRUP_VAUDP32_MASK_SFT		(0x1 << 0)
3452  #define RG_AUDHPROUTPWRUP_VAUDP32_SFT			1
3453  #define RG_AUDHPROUTPWRUP_VAUDP32_MASK			0x1
3454  #define RG_AUDHPROUTPWRUP_VAUDP32_MASK_SFT		(0x1 << 1)
3455  #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_SFT		2
3456  #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK		0x1
3457  #define RG_AUDHPLOUTAUXPWRUP_VAUDP32_MASK_SFT		(0x1 << 2)
3458  #define RG_AUDHPROUTAUXPWRUP_VAUDP32_SFT		3
3459  #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK		0x1
3460  #define RG_AUDHPROUTAUXPWRUP_VAUDP32_MASK_SFT		(0x1 << 3)
3461  #define RG_HPLAUXFBRSW_EN_VAUDP32_SFT			4
3462  #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK			0x1
3463  #define RG_HPLAUXFBRSW_EN_VAUDP32_MASK_SFT		(0x1 << 4)
3464  #define RG_HPRAUXFBRSW_EN_VAUDP32_SFT			5
3465  #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK			0x1
3466  #define RG_HPRAUXFBRSW_EN_VAUDP32_MASK_SFT		(0x1 << 5)
3467  #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_SFT		6
3468  #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK		0x1
3469  #define RG_HPLSHORT2HPLAUX_EN_VAUDP32_MASK_SFT		(0x1 << 6)
3470  #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_SFT		7
3471  #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK		0x1
3472  #define RG_HPRSHORT2HPRAUX_EN_VAUDP32_MASK_SFT		(0x1 << 7)
3473  #define RG_HPLOUTSTGCTRL_VAUDP32_SFT			8
3474  #define RG_HPLOUTSTGCTRL_VAUDP32_MASK			0x7
3475  #define RG_HPLOUTSTGCTRL_VAUDP32_MASK_SFT		(0x7 << 8)
3476  #define RG_HPROUTSTGCTRL_VAUDP32_SFT			12
3477  #define RG_HPROUTSTGCTRL_VAUDP32_MASK			0x7
3478  #define RG_HPROUTSTGCTRL_VAUDP32_MASK_SFT		(0x7 << 12)
3479  
3480  /* AUDDEC_ANA_CON2 */
3481  #define RG_HPLOUTPUTSTBENH_VAUDP32_SFT			0
3482  #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK			0x7
3483  #define RG_HPLOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x7 << 0)
3484  #define RG_HPROUTPUTSTBENH_VAUDP32_SFT			4
3485  #define RG_HPROUTPUTSTBENH_VAUDP32_MASK			0x7
3486  #define RG_HPROUTPUTSTBENH_VAUDP32_MASK_SFT		(0x7 << 4)
3487  #define RG_AUDHPSTARTUP_VAUDP32_SFT			7
3488  #define RG_AUDHPSTARTUP_VAUDP32_MASK			0x1
3489  #define RG_AUDHPSTARTUP_VAUDP32_MASK_SFT		(0x1 << 7)
3490  #define RG_AUDREFN_DERES_EN_VAUDP32_SFT			8
3491  #define RG_AUDREFN_DERES_EN_VAUDP32_MASK		0x1
3492  #define RG_AUDREFN_DERES_EN_VAUDP32_MASK_SFT		(0x1 << 8)
3493  #define RG_HPINPUTSTBENH_VAUDP32_SFT			9
3494  #define RG_HPINPUTSTBENH_VAUDP32_MASK			0x1
3495  #define RG_HPINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 9)
3496  #define RG_HPINPUTRESET0_VAUDP32_SFT			10
3497  #define RG_HPINPUTRESET0_VAUDP32_MASK			0x1
3498  #define RG_HPINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
3499  #define RG_HPOUTPUTRESET0_VAUDP32_SFT			11
3500  #define RG_HPOUTPUTRESET0_VAUDP32_MASK			0x1
3501  #define RG_HPOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 11)
3502  #define RG_HPPSHORT2VCM_VAUDP32_SFT			12
3503  #define RG_HPPSHORT2VCM_VAUDP32_MASK			0x7
3504  #define RG_HPPSHORT2VCM_VAUDP32_MASK_SFT		(0x7 << 12)
3505  #define RG_AUDHPTRIM_EN_VAUDP32_SFT			15
3506  #define RG_AUDHPTRIM_EN_VAUDP32_MASK			0x1
3507  #define RG_AUDHPTRIM_EN_VAUDP32_MASK_SFT		(0x1 << 15)
3508  
3509  /* AUDDEC_ANA_CON3 */
3510  #define RG_AUDHPLTRIM_VAUDP32_SFT			0
3511  #define RG_AUDHPLTRIM_VAUDP32_MASK			0x1f
3512  #define RG_AUDHPLTRIM_VAUDP32_MASK_SFT			(0x1f << 0)
3513  #define RG_AUDHPLFINETRIM_VAUDP32_SFT			5
3514  #define RG_AUDHPLFINETRIM_VAUDP32_MASK			0x7
3515  #define RG_AUDHPLFINETRIM_VAUDP32_MASK_SFT		(0x7 << 5)
3516  #define RG_AUDHPRTRIM_VAUDP32_SFT			8
3517  #define RG_AUDHPRTRIM_VAUDP32_MASK			0x1f
3518  #define RG_AUDHPRTRIM_VAUDP32_MASK_SFT			(0x1f << 8)
3519  #define RG_AUDHPRFINETRIM_VAUDP32_SFT			13
3520  #define RG_AUDHPRFINETRIM_VAUDP32_MASK			0x7
3521  #define RG_AUDHPRFINETRIM_VAUDP32_MASK_SFT		(0x7 << 13)
3522  
3523  /* AUDDEC_ANA_CON4 */
3524  #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_SFT		0
3525  #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK		0x7
3526  #define RG_AUDHPDIFFINPBIASADJ_VAUDP32_MASK_SFT		(0x7 << 0)
3527  #define RG_AUDHPLFCOMPRESSEL_VAUDP32_SFT		4
3528  #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK		0x7
3529  #define RG_AUDHPLFCOMPRESSEL_VAUDP32_MASK_SFT		(0x7 << 4)
3530  #define RG_AUDHPHFCOMPRESSEL_VAUDP32_SFT		8
3531  #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK		0x7
3532  #define RG_AUDHPHFCOMPRESSEL_VAUDP32_MASK_SFT		(0x7 << 8)
3533  #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_SFT		12
3534  #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK		0x3
3535  #define RG_AUDHPHFCOMPBUFGAINSEL_VAUDP32_MASK_SFT	(0x3 << 12)
3536  #define RG_AUDHPCOMP_EN_VAUDP32_SFT			15
3537  #define RG_AUDHPCOMP_EN_VAUDP32_MASK			0x1
3538  #define RG_AUDHPCOMP_EN_VAUDP32_MASK_SFT		(0x1 << 15)
3539  
3540  /* AUDDEC_ANA_CON5 */
3541  #define RG_AUDHPDECMGAINADJ_VAUDP32_SFT			0
3542  #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK		0x7
3543  #define RG_AUDHPDECMGAINADJ_VAUDP32_MASK_SFT		(0x7 << 0)
3544  #define RG_AUDHPDEDMGAINADJ_VAUDP32_SFT			4
3545  #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK		0x7
3546  #define RG_AUDHPDEDMGAINADJ_VAUDP32_MASK_SFT		(0x7 << 4)
3547  
3548  /* AUDDEC_ANA_CON6 */
3549  #define RG_AUDHSPWRUP_VAUDP32_SFT			0
3550  #define RG_AUDHSPWRUP_VAUDP32_MASK			0x1
3551  #define RG_AUDHSPWRUP_VAUDP32_MASK_SFT			(0x1 << 0)
3552  #define RG_AUDHSPWRUP_IBIAS_VAUDP32_SFT			1
3553  #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK		0x1
3554  #define RG_AUDHSPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 1)
3555  #define RG_AUDHSMUXINPUTSEL_VAUDP32_SFT			2
3556  #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK		0x3
3557  #define RG_AUDHSMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 2)
3558  #define RG_AUDHSSCDISABLE_VAUDP32_SFT			4
3559  #define RG_AUDHSSCDISABLE_VAUDP32_MASK			0x1
3560  #define RG_AUDHSSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 4)
3561  #define RG_AUDHSBSCCURRENT_VAUDP32_SFT			5
3562  #define RG_AUDHSBSCCURRENT_VAUDP32_MASK			0x1
3563  #define RG_AUDHSBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 5)
3564  #define RG_AUDHSSTARTUP_VAUDP32_SFT			6
3565  #define RG_AUDHSSTARTUP_VAUDP32_MASK			0x1
3566  #define RG_AUDHSSTARTUP_VAUDP32_MASK_SFT		(0x1 << 6)
3567  #define RG_HSOUTPUTSTBENH_VAUDP32_SFT			7
3568  #define RG_HSOUTPUTSTBENH_VAUDP32_MASK			0x1
3569  #define RG_HSOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 7)
3570  #define RG_HSINPUTSTBENH_VAUDP32_SFT			8
3571  #define RG_HSINPUTSTBENH_VAUDP32_MASK			0x1
3572  #define RG_HSINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 8)
3573  #define RG_HSINPUTRESET0_VAUDP32_SFT			9
3574  #define RG_HSINPUTRESET0_VAUDP32_MASK			0x1
3575  #define RG_HSINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 9)
3576  #define RG_HSOUTPUTRESET0_VAUDP32_SFT			10
3577  #define RG_HSOUTPUTRESET0_VAUDP32_MASK			0x1
3578  #define RG_HSOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
3579  #define RG_HSOUT_SHORTVCM_VAUDP32_SFT			11
3580  #define RG_HSOUT_SHORTVCM_VAUDP32_MASK			0x1
3581  #define RG_HSOUT_SHORTVCM_VAUDP32_MASK_SFT		(0x1 << 11)
3582  
3583  /* AUDDEC_ANA_CON7 */
3584  #define RG_AUDLOLPWRUP_VAUDP32_SFT			0
3585  #define RG_AUDLOLPWRUP_VAUDP32_MASK			0x1
3586  #define RG_AUDLOLPWRUP_VAUDP32_MASK_SFT			(0x1 << 0)
3587  #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_SFT		1
3588  #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK		0x1
3589  #define RG_AUDLOLPWRUP_IBIAS_VAUDP32_MASK_SFT		(0x1 << 1)
3590  #define RG_AUDLOLMUXINPUTSEL_VAUDP32_SFT		2
3591  #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK		0x3
3592  #define RG_AUDLOLMUXINPUTSEL_VAUDP32_MASK_SFT		(0x3 << 2)
3593  #define RG_AUDLOLSCDISABLE_VAUDP32_SFT			4
3594  #define RG_AUDLOLSCDISABLE_VAUDP32_MASK			0x1
3595  #define RG_AUDLOLSCDISABLE_VAUDP32_MASK_SFT		(0x1 << 4)
3596  #define RG_AUDLOLBSCCURRENT_VAUDP32_SFT			5
3597  #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK		0x1
3598  #define RG_AUDLOLBSCCURRENT_VAUDP32_MASK_SFT		(0x1 << 5)
3599  #define RG_AUDLOSTARTUP_VAUDP32_SFT			6
3600  #define RG_AUDLOSTARTUP_VAUDP32_MASK			0x1
3601  #define RG_AUDLOSTARTUP_VAUDP32_MASK_SFT		(0x1 << 6)
3602  #define RG_LOINPUTSTBENH_VAUDP32_SFT			7
3603  #define RG_LOINPUTSTBENH_VAUDP32_MASK			0x1
3604  #define RG_LOINPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 7)
3605  #define RG_LOOUTPUTSTBENH_VAUDP32_SFT			8
3606  #define RG_LOOUTPUTSTBENH_VAUDP32_MASK			0x1
3607  #define RG_LOOUTPUTSTBENH_VAUDP32_MASK_SFT		(0x1 << 8)
3608  #define RG_LOINPUTRESET0_VAUDP32_SFT			9
3609  #define RG_LOINPUTRESET0_VAUDP32_MASK			0x1
3610  #define RG_LOINPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 9)
3611  #define RG_LOOUTPUTRESET0_VAUDP32_SFT			10
3612  #define RG_LOOUTPUTRESET0_VAUDP32_MASK			0x1
3613  #define RG_LOOUTPUTRESET0_VAUDP32_MASK_SFT		(0x1 << 10)
3614  #define RG_LOOUT_SHORTVCM_VAUDP32_SFT			11
3615  #define RG_LOOUT_SHORTVCM_VAUDP32_MASK			0x1
3616  #define RG_LOOUT_SHORTVCM_VAUDP32_MASK_SFT		(0x1 << 11)
3617  #define RG_AUDDACTPWRUP_VAUDP32_SFT			12
3618  #define RG_AUDDACTPWRUP_VAUDP32_MASK			0x1
3619  #define RG_AUDDACTPWRUP_VAUDP32_MASK_SFT		(0x1 << 12)
3620  #define RG_AUD_DAC_PWT_UP_VA32_SFT			13
3621  #define RG_AUD_DAC_PWT_UP_VA32_MASK			0x1
3622  #define RG_AUD_DAC_PWT_UP_VA32_MASK_SFT			(0x1 << 13)
3623  
3624  /* AUDDEC_ANA_CON8 */
3625  #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_SFT		0
3626  #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK		0xf
3627  #define RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP32_MASK_SFT	(0xf << 0)
3628  #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_SFT		4
3629  #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK		0x3
3630  #define RG_AUDTRIMBUF_GAINSEL_VAUDP32_MASK_SFT		(0x3 << 4)
3631  #define RG_AUDTRIMBUF_EN_VAUDP32_SFT			6
3632  #define RG_AUDTRIMBUF_EN_VAUDP32_MASK			0x1
3633  #define RG_AUDTRIMBUF_EN_VAUDP32_MASK_SFT		(0x1 << 6)
3634  #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_SFT		8
3635  #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK		0x3
3636  #define RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP32_MASK_SFT	(0x3 << 8)
3637  #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_SFT		10
3638  #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK	0x3
3639  #define RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP32_MASK_SFT	(0x3 << 10)
3640  #define RG_AUDHPSPKDET_EN_VAUDP32_SFT			12
3641  #define RG_AUDHPSPKDET_EN_VAUDP32_MASK			0x1
3642  #define RG_AUDHPSPKDET_EN_VAUDP32_MASK_SFT		(0x1 << 12)
3643  
3644  /* AUDDEC_ANA_CON9 */
3645  #define RG_ABIDEC_RSVD0_VA32_SFT			0
3646  #define RG_ABIDEC_RSVD0_VA32_MASK			0xff
3647  #define RG_ABIDEC_RSVD0_VA32_MASK_SFT			(0xff << 0)
3648  #define RG_ABIDEC_RSVD0_VAUDP32_SFT			8
3649  #define RG_ABIDEC_RSVD0_VAUDP32_MASK			0xff
3650  #define RG_ABIDEC_RSVD0_VAUDP32_MASK_SFT		(0xff << 8)
3651  
3652  /* AUDDEC_ANA_CON10 */
3653  #define RG_ABIDEC_RSVD1_VAUDP32_SFT			0
3654  #define RG_ABIDEC_RSVD1_VAUDP32_MASK			0xff
3655  #define RG_ABIDEC_RSVD1_VAUDP32_MASK_SFT		(0xff << 0)
3656  #define RG_ABIDEC_RSVD2_VAUDP32_SFT			8
3657  #define RG_ABIDEC_RSVD2_VAUDP32_MASK			0xff
3658  #define RG_ABIDEC_RSVD2_VAUDP32_MASK_SFT		(0xff << 8)
3659  
3660  /* AUDDEC_ANA_CON11 */
3661  #define RG_AUDZCDMUXSEL_VAUDP32_SFT			0
3662  #define RG_AUDZCDMUXSEL_VAUDP32_MASK			0x7
3663  #define RG_AUDZCDMUXSEL_VAUDP32_MASK_SFT		(0x7 << 0)
3664  #define RG_AUDZCDCLKSEL_VAUDP32_SFT			3
3665  #define RG_AUDZCDCLKSEL_VAUDP32_MASK			0x1
3666  #define RG_AUDZCDCLKSEL_VAUDP32_MASK_SFT		(0x1 << 3)
3667  #define RG_AUDBIASADJ_0_VAUDP32_SFT			7
3668  #define RG_AUDBIASADJ_0_VAUDP32_MASK			0x1ff
3669  #define RG_AUDBIASADJ_0_VAUDP32_MASK_SFT		(0x1ff << 7)
3670  
3671  /* AUDDEC_ANA_CON12 */
3672  #define RG_AUDBIASADJ_1_VAUDP32_SFT			0
3673  #define RG_AUDBIASADJ_1_VAUDP32_MASK			0xff
3674  #define RG_AUDBIASADJ_1_VAUDP32_MASK_SFT		(0xff << 0)
3675  #define RG_AUDIBIASPWRDN_VAUDP32_SFT			8
3676  #define RG_AUDIBIASPWRDN_VAUDP32_MASK			0x1
3677  #define RG_AUDIBIASPWRDN_VAUDP32_MASK_SFT		(0x1 << 8)
3678  
3679  /* AUDDEC_ANA_CON13 */
3680  #define RG_RSTB_DECODER_VA32_SFT			0
3681  #define RG_RSTB_DECODER_VA32_MASK			0x1
3682  #define RG_RSTB_DECODER_VA32_MASK_SFT			(0x1 << 0)
3683  #define RG_SEL_DECODER_96K_VA32_SFT			1
3684  #define RG_SEL_DECODER_96K_VA32_MASK			0x1
3685  #define RG_SEL_DECODER_96K_VA32_MASK_SFT		(0x1 << 1)
3686  #define RG_SEL_DELAY_VCORE_SFT				2
3687  #define RG_SEL_DELAY_VCORE_MASK				0x1
3688  #define RG_SEL_DELAY_VCORE_MASK_SFT			(0x1 << 2)
3689  #define RG_AUDGLB_PWRDN_VA32_SFT			4
3690  #define RG_AUDGLB_PWRDN_VA32_MASK			0x1
3691  #define RG_AUDGLB_PWRDN_VA32_MASK_SFT			(0x1 << 4)
3692  #define RG_AUDGLB_LP_VOW_EN_VA32_SFT			5
3693  #define RG_AUDGLB_LP_VOW_EN_VA32_MASK			0x1
3694  #define RG_AUDGLB_LP_VOW_EN_VA32_MASK_SFT		(0x1 << 5)
3695  #define RG_AUDGLB_LP2_VOW_EN_VA32_SFT			6
3696  #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK			0x1
3697  #define RG_AUDGLB_LP2_VOW_EN_VA32_MASK_SFT		(0x1 << 6)
3698  
3699  /* AUDDEC_ANA_CON14 */
3700  #define RG_LCLDO_DEC_EN_VA32_SFT			0
3701  #define RG_LCLDO_DEC_EN_VA32_MASK			0x1
3702  #define RG_LCLDO_DEC_EN_VA32_MASK_SFT			(0x1 << 0)
3703  #define RG_LCLDO_DEC_PDDIS_EN_VA18_SFT			1
3704  #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK			0x1
3705  #define RG_LCLDO_DEC_PDDIS_EN_VA18_MASK_SFT		(0x1 << 1)
3706  #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_SFT		2
3707  #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK		0x1
3708  #define RG_LCLDO_DEC_REMOTE_SENSE_VA18_MASK_SFT		(0x1 << 2)
3709  #define RG_NVREG_EN_VAUDP32_SFT				4
3710  #define RG_NVREG_EN_VAUDP32_MASK			0x1
3711  #define RG_NVREG_EN_VAUDP32_MASK_SFT			(0x1 << 4)
3712  #define RG_NVREG_PULL0V_VAUDP32_SFT			5
3713  #define RG_NVREG_PULL0V_VAUDP32_MASK			0x1
3714  #define RG_NVREG_PULL0V_VAUDP32_MASK_SFT		(0x1 << 5)
3715  #define RG_AUDPMU_RSVD_VA18_SFT				8
3716  #define RG_AUDPMU_RSVD_VA18_MASK			0xff
3717  #define RG_AUDPMU_RSVD_VA18_MASK_SFT			(0xff << 8)
3718  
3719  /* MT6359_ZCD_CON0 */
3720  #define RG_AUDZCDENABLE_SFT				0
3721  #define RG_AUDZCDENABLE_MASK				0x1
3722  #define RG_AUDZCDENABLE_MASK_SFT			(0x1 << 0)
3723  #define RG_AUDZCDGAINSTEPTIME_SFT			1
3724  #define RG_AUDZCDGAINSTEPTIME_MASK			0x7
3725  #define RG_AUDZCDGAINSTEPTIME_MASK_SFT			(0x7 << 1)
3726  #define RG_AUDZCDGAINSTEPSIZE_SFT			4
3727  #define RG_AUDZCDGAINSTEPSIZE_MASK			0x3
3728  #define RG_AUDZCDGAINSTEPSIZE_MASK_SFT			(0x3 << 4)
3729  #define RG_AUDZCDTIMEOUTMODESEL_SFT			6
3730  #define RG_AUDZCDTIMEOUTMODESEL_MASK			0x1
3731  #define RG_AUDZCDTIMEOUTMODESEL_MASK_SFT		(0x1 << 6)
3732  
3733  /* MT6359_ZCD_CON1 */
3734  #define RG_AUDLOLGAIN_SFT				0
3735  #define RG_AUDLOLGAIN_MASK				0x1f
3736  #define RG_AUDLOLGAIN_MASK_SFT				(0x1f << 0)
3737  #define RG_AUDLORGAIN_SFT				7
3738  #define RG_AUDLORGAIN_MASK				0x1f
3739  #define RG_AUDLORGAIN_MASK_SFT				(0x1f << 7)
3740  
3741  /* MT6359_ZCD_CON2 */
3742  #define RG_AUDHPLGAIN_SFT				0
3743  #define RG_AUDHPLGAIN_MASK				0x1f
3744  #define RG_AUDHPLGAIN_MASK_SFT				(0x1f << 0)
3745  #define RG_AUDHPRGAIN_SFT				7
3746  #define RG_AUDHPRGAIN_MASK				0x1f
3747  #define RG_AUDHPRGAIN_MASK_SFT				(0x1f << 7)
3748  
3749  /* MT6359_ZCD_CON3 */
3750  #define RG_AUDHSGAIN_SFT				0
3751  #define RG_AUDHSGAIN_MASK				0x1f
3752  #define RG_AUDHSGAIN_MASK_SFT				(0x1f << 0)
3753  
3754  /* MT6359_ZCD_CON4 */
3755  #define RG_AUDIVLGAIN_SFT				0
3756  #define RG_AUDIVLGAIN_MASK				0x7
3757  #define RG_AUDIVLGAIN_MASK_SFT				(0x7 << 0)
3758  #define RG_AUDIVRGAIN_SFT				8
3759  #define RG_AUDIVRGAIN_MASK				0x7
3760  #define RG_AUDIVRGAIN_MASK_SFT				(0x7 << 8)
3761  
3762  /* MT6359_ZCD_CON5 */
3763  #define RG_AUDINTGAIN1_SFT				0
3764  #define RG_AUDINTGAIN1_MASK				0x3f
3765  #define RG_AUDINTGAIN1_MASK_SFT				(0x3f << 0)
3766  #define RG_AUDINTGAIN2_SFT				8
3767  #define RG_AUDINTGAIN2_MASK				0x3f
3768  #define RG_AUDINTGAIN2_MASK_SFT				(0x3f << 8)
3769  
3770  /* audio register */
3771  #define MT6359_GPIO_DIR0				0x88
3772  #define MT6359_GPIO_DIR0_SET				0x8a
3773  #define MT6359_GPIO_DIR0_CLR				0x8c
3774  #define MT6359_GPIO_DIR1				0x8e
3775  #define MT6359_GPIO_DIR1_SET				0x90
3776  #define MT6359_GPIO_DIR1_CLR				0x92
3777  
3778  #define MT6359_DCXO_CW11				0x7a6
3779  #define MT6359_DCXO_CW12				0x7a8
3780  
3781  #define MT6359_GPIO_MODE0				0xcc
3782  #define MT6359_GPIO_MODE0_SET				0xce
3783  #define MT6359_GPIO_MODE0_CLR				0xd0
3784  #define MT6359_GPIO_MODE1				0xd2
3785  #define MT6359_GPIO_MODE1_SET				0xd4
3786  #define MT6359_GPIO_MODE1_CLR				0xd6
3787  #define MT6359_GPIO_MODE2				0xd8
3788  #define MT6359_GPIO_MODE2_SET				0xda
3789  #define MT6359_GPIO_MODE2_CLR				0xdc
3790  #define MT6359_GPIO_MODE3				0xde
3791  #define MT6359_GPIO_MODE3_SET				0xe0
3792  #define MT6359_GPIO_MODE3_CLR				0xe2
3793  #define MT6359_GPIO_MODE4				0xe4
3794  #define MT6359_GPIO_MODE4_SET				0xe6
3795  #define MT6359_GPIO_MODE4_CLR				0xe8
3796  
3797  #define MT6359_AUD_TOP_ID				0x2300
3798  #define MT6359_AUD_TOP_REV0				0x2302
3799  #define MT6359_AUD_TOP_DBI				0x2304
3800  #define MT6359_AUD_TOP_DXI				0x2306
3801  #define MT6359_AUD_TOP_CKPDN_TPM0			0x2308
3802  #define MT6359_AUD_TOP_CKPDN_TPM1			0x230a
3803  #define MT6359_AUD_TOP_CKPDN_CON0			0x230c
3804  #define MT6359_AUD_TOP_CKPDN_CON0_SET			0x230e
3805  #define MT6359_AUD_TOP_CKPDN_CON0_CLR			0x2310
3806  #define MT6359_AUD_TOP_CKSEL_CON0			0x2312
3807  #define MT6359_AUD_TOP_CKSEL_CON0_SET			0x2314
3808  #define MT6359_AUD_TOP_CKSEL_CON0_CLR			0x2316
3809  #define MT6359_AUD_TOP_CKTST_CON0			0x2318
3810  #define MT6359_AUD_TOP_CLK_HWEN_CON0			0x231a
3811  #define MT6359_AUD_TOP_CLK_HWEN_CON0_SET		0x231c
3812  #define MT6359_AUD_TOP_CLK_HWEN_CON0_CLR		0x231e
3813  #define MT6359_AUD_TOP_RST_CON0				0x2320
3814  #define MT6359_AUD_TOP_RST_CON0_SET			0x2322
3815  #define MT6359_AUD_TOP_RST_CON0_CLR			0x2324
3816  #define MT6359_AUD_TOP_RST_BANK_CON0			0x2326
3817  #define MT6359_AUD_TOP_INT_CON0				0x2328
3818  #define MT6359_AUD_TOP_INT_CON0_SET			0x232a
3819  #define MT6359_AUD_TOP_INT_CON0_CLR			0x232c
3820  #define MT6359_AUD_TOP_INT_MASK_CON0			0x232e
3821  #define MT6359_AUD_TOP_INT_MASK_CON0_SET		0x2330
3822  #define MT6359_AUD_TOP_INT_MASK_CON0_CLR		0x2332
3823  #define MT6359_AUD_TOP_INT_STATUS0			0x2334
3824  #define MT6359_AUD_TOP_INT_RAW_STATUS0			0x2336
3825  #define MT6359_AUD_TOP_INT_MISC_CON0			0x2338
3826  #define MT6359_AUD_TOP_MON_CON0				0x233a
3827  #define MT6359_AUDIO_DIG_DSN_ID				0x2380
3828  #define MT6359_AUDIO_DIG_DSN_REV0			0x2382
3829  #define MT6359_AUDIO_DIG_DSN_DBI			0x2384
3830  #define MT6359_AUDIO_DIG_DSN_DXI			0x2386
3831  #define MT6359_AFE_UL_DL_CON0				0x2388
3832  #define MT6359_AFE_DL_SRC2_CON0_L			0x238a
3833  #define MT6359_AFE_UL_SRC_CON0_H			0x238c
3834  #define MT6359_AFE_UL_SRC_CON0_L			0x238e
3835  #define MT6359_AFE_ADDA6_L_SRC_CON0_H			0x2390
3836  #define MT6359_AFE_ADDA6_UL_SRC_CON0_L			0x2392
3837  #define MT6359_AFE_TOP_CON0				0x2394
3838  #define MT6359_AUDIO_TOP_CON0				0x2396
3839  #define MT6359_AFE_MON_DEBUG0				0x2398
3840  #define MT6359_AFUNC_AUD_CON0				0x239a
3841  #define MT6359_AFUNC_AUD_CON1				0x239c
3842  #define MT6359_AFUNC_AUD_CON2				0x239e
3843  #define MT6359_AFUNC_AUD_CON3				0x23a0
3844  #define MT6359_AFUNC_AUD_CON4				0x23a2
3845  #define MT6359_AFUNC_AUD_CON5				0x23a4
3846  #define MT6359_AFUNC_AUD_CON6				0x23a6
3847  #define MT6359_AFUNC_AUD_CON7				0x23a8
3848  #define MT6359_AFUNC_AUD_CON8				0x23aa
3849  #define MT6359_AFUNC_AUD_CON9				0x23ac
3850  #define MT6359_AFUNC_AUD_CON10				0x23ae
3851  #define MT6359_AFUNC_AUD_CON11				0x23b0
3852  #define MT6359_AFUNC_AUD_CON12				0x23b2
3853  #define MT6359_AFUNC_AUD_MON0				0x23b4
3854  #define MT6359_AFUNC_AUD_MON1				0x23b6
3855  #define MT6359_AUDRC_TUNE_MON0				0x23b8
3856  #define MT6359_AFE_ADDA_MTKAIF_FIFO_CFG0		0x23ba
3857  #define MT6359_AFE_ADDA_MTKAIF_FIFO_LOG_MON1		0x23bc
3858  #define MT6359_AFE_ADDA_MTKAIF_MON0			0x23be
3859  #define MT6359_AFE_ADDA_MTKAIF_MON1			0x23c0
3860  #define MT6359_AFE_ADDA_MTKAIF_MON2			0x23c2
3861  #define MT6359_AFE_ADDA6_MTKAIF_MON3			0x23c4
3862  #define MT6359_AFE_ADDA_MTKAIF_MON4			0x23c6
3863  #define MT6359_AFE_ADDA_MTKAIF_MON5			0x23c8
3864  #define MT6359_AFE_ADDA_MTKAIF_CFG0			0x23ca
3865  #define MT6359_AFE_ADDA_MTKAIF_RX_CFG0			0x23cc
3866  #define MT6359_AFE_ADDA_MTKAIF_RX_CFG1			0x23ce
3867  #define MT6359_AFE_ADDA_MTKAIF_RX_CFG2			0x23d0
3868  #define MT6359_AFE_ADDA_MTKAIF_RX_CFG3			0x23d2
3869  #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG0		0x23d4
3870  #define MT6359_AFE_ADDA_MTKAIF_SYNCWORD_CFG1		0x23d6
3871  #define MT6359_AFE_SGEN_CFG0				0x23d8
3872  #define MT6359_AFE_SGEN_CFG1				0x23da
3873  #define MT6359_AFE_ADC_ASYNC_FIFO_CFG			0x23dc
3874  #define MT6359_AFE_ADC_ASYNC_FIFO_CFG1			0x23de
3875  #define MT6359_AFE_DCCLK_CFG0				0x23e0
3876  #define MT6359_AFE_DCCLK_CFG1				0x23e2
3877  #define MT6359_AUDIO_DIG_CFG				0x23e4
3878  #define MT6359_AUDIO_DIG_CFG1				0x23e6
3879  #define MT6359_AFE_AUD_PAD_TOP				0x23e8
3880  #define MT6359_AFE_AUD_PAD_TOP_MON			0x23ea
3881  #define MT6359_AFE_AUD_PAD_TOP_MON1			0x23ec
3882  #define MT6359_AFE_AUD_PAD_TOP_MON2			0x23ee
3883  #define MT6359_AFE_DL_NLE_CFG				0x23f0
3884  #define MT6359_AFE_DL_NLE_MON				0x23f2
3885  #define MT6359_AFE_CG_EN_MON				0x23f4
3886  #define MT6359_AFE_MIC_ARRAY_CFG			0x23f6
3887  #define MT6359_AFE_CHOP_CFG0				0x23f8
3888  #define MT6359_AFE_MTKAIF_MUX_CFG			0x23fa
3889  #define MT6359_AUDIO_DIG_2ND_DSN_ID			0x2400
3890  #define MT6359_AUDIO_DIG_2ND_DSN_REV0			0x2402
3891  #define MT6359_AUDIO_DIG_2ND_DSN_DBI			0x2404
3892  #define MT6359_AUDIO_DIG_2ND_DSN_DXI			0x2406
3893  #define MT6359_AFE_PMIC_NEWIF_CFG3			0x2408
3894  #define MT6359_AUDIO_DIG_3RD_DSN_ID			0x2480
3895  #define MT6359_AUDIO_DIG_3RD_DSN_REV0			0x2482
3896  #define MT6359_AUDIO_DIG_3RD_DSN_DBI			0x2484
3897  #define MT6359_AUDIO_DIG_3RD_DSN_DXI			0x2486
3898  #define MT6359_AFE_NCP_CFG0				0x24de
3899  #define MT6359_AFE_NCP_CFG1				0x24e0
3900  #define MT6359_AFE_NCP_CFG2				0x24e2
3901  #define MT6359_AUDENC_DSN_ID				0x2500
3902  #define MT6359_AUDENC_DSN_REV0				0x2502
3903  #define MT6359_AUDENC_DSN_DBI				0x2504
3904  #define MT6359_AUDENC_DSN_FPI				0x2506
3905  #define MT6359_AUDENC_ANA_CON0				0x2508
3906  #define MT6359_AUDENC_ANA_CON1				0x250a
3907  #define MT6359_AUDENC_ANA_CON2				0x250c
3908  #define MT6359_AUDENC_ANA_CON3				0x250e
3909  #define MT6359_AUDENC_ANA_CON4				0x2510
3910  #define MT6359_AUDENC_ANA_CON5				0x2512
3911  #define MT6359_AUDENC_ANA_CON6				0x2514
3912  #define MT6359_AUDENC_ANA_CON7				0x2516
3913  #define MT6359_AUDENC_ANA_CON8				0x2518
3914  #define MT6359_AUDENC_ANA_CON9				0x251a
3915  #define MT6359_AUDENC_ANA_CON10				0x251c
3916  #define MT6359_AUDENC_ANA_CON11				0x251e
3917  #define MT6359_AUDENC_ANA_CON12				0x2520
3918  #define MT6359_AUDENC_ANA_CON13				0x2522
3919  #define MT6359_AUDENC_ANA_CON14				0x2524
3920  #define MT6359_AUDENC_ANA_CON15				0x2526
3921  #define MT6359_AUDENC_ANA_CON16				0x2528
3922  #define MT6359_AUDENC_ANA_CON17				0x252a
3923  #define MT6359_AUDENC_ANA_CON18				0x252c
3924  #define MT6359_AUDENC_ANA_CON19				0x252e
3925  #define MT6359_AUDENC_ANA_CON20				0x2530
3926  #define MT6359_AUDENC_ANA_CON21				0x2532
3927  #define MT6359_AUDENC_ANA_CON22				0x2534
3928  #define MT6359_AUDENC_ANA_CON23				0x2536
3929  #define MT6359_AUDDEC_DSN_ID				0x2580
3930  #define MT6359_AUDDEC_DSN_REV0				0x2582
3931  #define MT6359_AUDDEC_DSN_DBI				0x2584
3932  #define MT6359_AUDDEC_DSN_FPI				0x2586
3933  #define MT6359_AUDDEC_ANA_CON0				0x2588
3934  #define MT6359_AUDDEC_ANA_CON1				0x258a
3935  #define MT6359_AUDDEC_ANA_CON2				0x258c
3936  #define MT6359_AUDDEC_ANA_CON3				0x258e
3937  #define MT6359_AUDDEC_ANA_CON4				0x2590
3938  #define MT6359_AUDDEC_ANA_CON5				0x2592
3939  #define MT6359_AUDDEC_ANA_CON6				0x2594
3940  #define MT6359_AUDDEC_ANA_CON7				0x2596
3941  #define MT6359_AUDDEC_ANA_CON8				0x2598
3942  #define MT6359_AUDDEC_ANA_CON9				0x259a
3943  #define MT6359_AUDDEC_ANA_CON10				0x259c
3944  #define MT6359_AUDDEC_ANA_CON11				0x259e
3945  #define MT6359_AUDDEC_ANA_CON12				0x25a0
3946  #define MT6359_AUDDEC_ANA_CON13				0x25a2
3947  #define MT6359_AUDDEC_ANA_CON14				0x25a4
3948  #define MT6359_AUDZCD_DSN_ID				0x2600
3949  #define MT6359_AUDZCD_DSN_REV0				0x2602
3950  #define MT6359_AUDZCD_DSN_DBI				0x2604
3951  #define MT6359_AUDZCD_DSN_FPI				0x2606
3952  #define MT6359_ZCD_CON0					0x2608
3953  #define MT6359_ZCD_CON1					0x260a
3954  #define MT6359_ZCD_CON2					0x260c
3955  #define MT6359_ZCD_CON3					0x260e
3956  #define MT6359_ZCD_CON4					0x2610
3957  #define MT6359_ZCD_CON5					0x2612
3958  #define MT6359_ACCDET_DSN_DIG_ID			0x2680
3959  #define MT6359_ACCDET_DSN_DIG_REV0			0x2682
3960  #define MT6359_ACCDET_DSN_DBI				0x2684
3961  #define MT6359_ACCDET_DSN_FPI				0x2686
3962  #define MT6359_ACCDET_CON0				0x2688
3963  #define MT6359_ACCDET_CON1				0x268a
3964  #define MT6359_ACCDET_CON2				0x268c
3965  #define MT6359_ACCDET_CON3				0x268e
3966  #define MT6359_ACCDET_CON4				0x2690
3967  #define MT6359_ACCDET_CON5				0x2692
3968  #define MT6359_ACCDET_CON6				0x2694
3969  #define MT6359_ACCDET_CON7				0x2696
3970  #define MT6359_ACCDET_CON8				0x2698
3971  #define MT6359_ACCDET_CON9				0x269a
3972  #define MT6359_ACCDET_CON10				0x269c
3973  #define MT6359_ACCDET_CON11				0x269e
3974  #define MT6359_ACCDET_CON12				0x26a0
3975  #define MT6359_ACCDET_CON13				0x26a2
3976  #define MT6359_ACCDET_CON14				0x26a4
3977  #define MT6359_ACCDET_CON15				0x26a6
3978  #define MT6359_ACCDET_CON16				0x26a8
3979  #define MT6359_ACCDET_CON17				0x26aa
3980  #define MT6359_ACCDET_CON18				0x26ac
3981  #define MT6359_ACCDET_CON19				0x26ae
3982  #define MT6359_ACCDET_CON20				0x26b0
3983  #define MT6359_ACCDET_CON21				0x26b2
3984  #define MT6359_ACCDET_CON22				0x26b4
3985  #define MT6359_ACCDET_CON23				0x26b6
3986  #define MT6359_ACCDET_CON24				0x26b8
3987  #define MT6359_ACCDET_CON25				0x26ba
3988  #define MT6359_ACCDET_CON26				0x26bc
3989  #define MT6359_ACCDET_CON27				0x26be
3990  #define MT6359_ACCDET_CON28				0x26c0
3991  #define MT6359_ACCDET_CON29				0x26c2
3992  #define MT6359_ACCDET_CON30				0x26c4
3993  #define MT6359_ACCDET_CON31				0x26c6
3994  #define MT6359_ACCDET_CON32				0x26c8
3995  #define MT6359_ACCDET_CON33				0x26ca
3996  #define MT6359_ACCDET_CON34				0x26cc
3997  #define MT6359_ACCDET_CON35				0x26ce
3998  #define MT6359_ACCDET_CON36				0x26d0
3999  #define MT6359_ACCDET_CON37				0x26d2
4000  #define MT6359_ACCDET_CON38				0x26d4
4001  #define MT6359_ACCDET_CON39				0x26d6
4002  #define MT6359_ACCDET_CON40				0x26d8
4003  #define MT6359_MAX_REGISTER				MT6359_ZCD_CON5
4004  
4005  /* dl bias */
4006  #define DRBIAS_MASK 0x7
4007  #define DRBIAS_HP_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 0)
4008  #define DRBIAS_HP_MASK_SFT (DRBIAS_MASK << DRBIAS_HP_SFT)
4009  #define DRBIAS_HS_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 3)
4010  #define DRBIAS_HS_MASK_SFT (DRBIAS_MASK << DRBIAS_HS_SFT)
4011  #define DRBIAS_LO_SFT (RG_AUDBIASADJ_0_VAUDP32_SFT + 6)
4012  #define DRBIAS_LO_MASK_SFT (DRBIAS_MASK << DRBIAS_LO_SFT)
4013  #define IBIAS_MASK 0x3
4014  #define IBIAS_HP_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 0)
4015  #define IBIAS_HP_MASK_SFT (IBIAS_MASK << IBIAS_HP_SFT)
4016  #define IBIAS_HS_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 2)
4017  #define IBIAS_HS_MASK_SFT (IBIAS_MASK << IBIAS_HS_SFT)
4018  #define IBIAS_LO_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 4)
4019  #define IBIAS_LO_MASK_SFT (IBIAS_MASK << IBIAS_LO_SFT)
4020  #define IBIAS_ZCD_SFT (RG_AUDBIASADJ_1_VAUDP32_SFT + 6)
4021  #define IBIAS_ZCD_MASK_SFT (IBIAS_MASK << IBIAS_ZCD_SFT)
4022  
4023  /* dl gain */
4024  #define DL_GAIN_N_10DB_REG (DL_GAIN_N_10DB << 7 | DL_GAIN_N_10DB)
4025  #define DL_GAIN_N_22DB_REG (DL_GAIN_N_22DB << 7 | DL_GAIN_N_22DB)
4026  #define DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
4027  #define DL_GAIN_REG_MASK 0x0f9f
4028  
4029  /* mic type mux */
4030  #define MT_SOC_ENUM_EXT_ID(xname, xenum, xhandler_get, xhandler_put, id) \
4031  {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .device = id,\
4032  	.info = snd_soc_info_enum_double, \
4033  	.get = xhandler_get, .put = xhandler_put, \
4034  	.private_value = (unsigned long)&(xenum) }
4035  
4036  enum {
4037  	MT6359_MTKAIF_PROTOCOL_1 = 0,
4038  	MT6359_MTKAIF_PROTOCOL_2,
4039  	MT6359_MTKAIF_PROTOCOL_2_CLK_P2,
4040  };
4041  
4042  enum {
4043  	MT6359_AIF_1 = 0,	/* dl: hp, rcv, hp+lo */
4044  	MT6359_AIF_2,		/* dl: lo only */
4045  	MT6359_AIF_NUM,
4046  };
4047  
4048  enum {
4049  	AUDIO_ANALOG_VOLUME_HSOUTL,
4050  	AUDIO_ANALOG_VOLUME_HSOUTR,
4051  	AUDIO_ANALOG_VOLUME_HPOUTL,
4052  	AUDIO_ANALOG_VOLUME_HPOUTR,
4053  	AUDIO_ANALOG_VOLUME_LINEOUTL,
4054  	AUDIO_ANALOG_VOLUME_LINEOUTR,
4055  	AUDIO_ANALOG_VOLUME_MICAMP1,
4056  	AUDIO_ANALOG_VOLUME_MICAMP2,
4057  	AUDIO_ANALOG_VOLUME_MICAMP3,
4058  	AUDIO_ANALOG_VOLUME_TYPE_MAX
4059  };
4060  
4061  enum {
4062  	MUX_MIC_TYPE_0,	/* ain0, micbias 0 */
4063  	MUX_MIC_TYPE_1,	/* ain1, micbias 1 */
4064  	MUX_MIC_TYPE_2,	/* ain2/3, micbias 2 */
4065  	MUX_PGA_L,
4066  	MUX_PGA_R,
4067  	MUX_PGA_3,
4068  	MUX_HP,
4069  	MUX_NUM,
4070  };
4071  
4072  enum {
4073  	DEVICE_HP,
4074  	DEVICE_LO,
4075  	DEVICE_RCV,
4076  	DEVICE_MIC1,
4077  	DEVICE_MIC2,
4078  	DEVICE_NUM
4079  };
4080  
4081  enum {
4082  	HP_GAIN_CTL_ZCD = 0,
4083  	HP_GAIN_CTL_NLE,
4084  	HP_GAIN_CTL_NUM,
4085  };
4086  
4087  enum {
4088  	HP_MUX_OPEN = 0,
4089  	HP_MUX_HPSPK,
4090  	HP_MUX_HP,
4091  	HP_MUX_TEST_MODE,
4092  	HP_MUX_HP_IMPEDANCE,
4093  	HP_MUX_MASK = 0x7,
4094  };
4095  
4096  enum {
4097  	RCV_MUX_OPEN = 0,
4098  	RCV_MUX_MUTE,
4099  	RCV_MUX_VOICE_PLAYBACK,
4100  	RCV_MUX_TEST_MODE,
4101  	RCV_MUX_MASK = 0x3,
4102  };
4103  
4104  enum {
4105  	LO_MUX_OPEN = 0,
4106  	LO_MUX_L_DAC,
4107  	LO_MUX_3RD_DAC,
4108  	LO_MUX_TEST_MODE,
4109  	LO_MUX_MASK = 0x3,
4110  };
4111  
4112  /* Supply widget subseq */
4113  enum {
4114  	/* common */
4115  	SUPPLY_SEQ_CLK_BUF,
4116  	SUPPLY_SEQ_AUD_GLB,
4117  	SUPPLY_SEQ_HP_PULL_DOWN,
4118  	SUPPLY_SEQ_CLKSQ,
4119  	SUPPLY_SEQ_ADC_CLKGEN,
4120  	SUPPLY_SEQ_TOP_CK,
4121  	SUPPLY_SEQ_TOP_CK_LAST,
4122  	SUPPLY_SEQ_DCC_CLK,
4123  	SUPPLY_SEQ_MIC_BIAS,
4124  	SUPPLY_SEQ_DMIC,
4125  	SUPPLY_SEQ_AUD_TOP,
4126  	SUPPLY_SEQ_AUD_TOP_LAST,
4127  	SUPPLY_SEQ_DL_SDM_FIFO_CLK,
4128  	SUPPLY_SEQ_DL_SDM,
4129  	SUPPLY_SEQ_DL_NCP,
4130  	SUPPLY_SEQ_AFE,
4131  	/* playback */
4132  	SUPPLY_SEQ_DL_SRC,
4133  	SUPPLY_SEQ_DL_ESD_RESIST,
4134  	SUPPLY_SEQ_HP_DAMPING_OFF_RESET_CMFB,
4135  	SUPPLY_SEQ_HP_MUTE,
4136  	SUPPLY_SEQ_DL_LDO_REMOTE_SENSE,
4137  	SUPPLY_SEQ_DL_LDO,
4138  	SUPPLY_SEQ_DL_NV,
4139  	SUPPLY_SEQ_HP_ANA_TRIM,
4140  	SUPPLY_SEQ_DL_IBIST,
4141  	/* capture */
4142  	SUPPLY_SEQ_UL_PGA,
4143  	SUPPLY_SEQ_UL_ADC,
4144  	SUPPLY_SEQ_UL_MTKAIF,
4145  	SUPPLY_SEQ_UL_SRC_DMIC,
4146  	SUPPLY_SEQ_UL_SRC,
4147  };
4148  
4149  enum {
4150  	CH_L = 0,
4151  	CH_R,
4152  	NUM_CH,
4153  };
4154  
4155  enum {
4156  	DRBIAS_4UA = 0,
4157  	DRBIAS_5UA,
4158  	DRBIAS_6UA,
4159  	DRBIAS_7UA,
4160  	DRBIAS_8UA,
4161  	DRBIAS_9UA,
4162  	DRBIAS_10UA,
4163  	DRBIAS_11UA,
4164  };
4165  
4166  enum {
4167  	IBIAS_4UA = 0,
4168  	IBIAS_5UA,
4169  	IBIAS_6UA,
4170  	IBIAS_7UA,
4171  };
4172  
4173  enum {
4174  	IBIAS_ZCD_3UA = 0,
4175  	IBIAS_ZCD_4UA,
4176  	IBIAS_ZCD_5UA,
4177  	IBIAS_ZCD_6UA,
4178  };
4179  
4180  enum {
4181  	MIC_BIAS_1P7 = 0,
4182  	MIC_BIAS_1P8,
4183  	MIC_BIAS_1P9,
4184  	MIC_BIAS_2P0,
4185  	MIC_BIAS_2P1,
4186  	MIC_BIAS_2P5,
4187  	MIC_BIAS_2P6,
4188  	MIC_BIAS_2P7,
4189  };
4190  
4191  /* dl pga gain */
4192  enum {
4193  	DL_GAIN_8DB = 0,
4194  	DL_GAIN_0DB = 8,
4195  	DL_GAIN_N_1DB = 9,
4196  	DL_GAIN_N_10DB = 18,
4197  	DL_GAIN_N_22DB = 30,
4198  	DL_GAIN_N_40DB = 0x1f,
4199  };
4200  
4201  /* Mic Type MUX */
4202  enum {
4203  	MIC_TYPE_MUX_IDLE = 0,
4204  	MIC_TYPE_MUX_ACC,
4205  	MIC_TYPE_MUX_DMIC,
4206  	MIC_TYPE_MUX_DCC,
4207  	MIC_TYPE_MUX_DCC_ECM_DIFF,
4208  	MIC_TYPE_MUX_DCC_ECM_SINGLE,
4209  };
4210  
4211  /* UL SRC MUX */
4212  enum {
4213  	UL_SRC_MUX_AMIC = 0,
4214  	UL_SRC_MUX_DMIC,
4215  };
4216  
4217  /* MISO MUX */
4218  enum {
4219  	MISO_MUX_UL1_CH1 = 0,
4220  	MISO_MUX_UL1_CH2,
4221  	MISO_MUX_UL2_CH1,
4222  	MISO_MUX_UL2_CH2,
4223  };
4224  
4225  /* DMIC MUX */
4226  enum {
4227  	DMIC_MUX_DMIC_DATA0 = 0,
4228  	DMIC_MUX_DMIC_DATA1_L,
4229  	DMIC_MUX_DMIC_DATA1_L_1,
4230  	DMIC_MUX_DMIC_DATA1_R,
4231  };
4232  
4233  /* ADC L MUX */
4234  enum {
4235  	ADC_MUX_IDLE = 0,
4236  	ADC_MUX_AIN0,
4237  	ADC_MUX_PREAMPLIFIER,
4238  	ADC_MUX_IDLE1,
4239  };
4240  
4241  /* PGA L MUX */
4242  enum {
4243  	PGA_L_MUX_NONE = 0,
4244  	PGA_L_MUX_AIN0,
4245  	PGA_L_MUX_AIN1,
4246  };
4247  
4248  /* PGA R MUX */
4249  enum {
4250  	PGA_R_MUX_NONE = 0,
4251  	PGA_R_MUX_AIN2,
4252  	PGA_R_MUX_AIN3,
4253  	PGA_R_MUX_AIN0,
4254  };
4255  
4256  /* PGA 3 MUX */
4257  enum {
4258  	PGA_3_MUX_NONE = 0,
4259  	PGA_3_MUX_AIN3,
4260  	PGA_3_MUX_AIN2,
4261  };
4262  
4263  struct mt6359_priv {
4264  	struct device *dev;
4265  	struct regmap *regmap;
4266  	unsigned int dl_rate[MT6359_AIF_NUM];
4267  	unsigned int ul_rate[MT6359_AIF_NUM];
4268  	int ana_gain[AUDIO_ANALOG_VOLUME_TYPE_MAX];
4269  	unsigned int mux_select[MUX_NUM];
4270  	unsigned int dmic_one_wire_mode;
4271  	int dev_counter[DEVICE_NUM];
4272  	int hp_gain_ctl;
4273  	int hp_hifi_mode;
4274  	int mtkaif_protocol;
4275  };
4276  
4277  #define CODEC_MT6359_NAME "mtk-codec-mt6359"
4278  #define IS_DCC_BASE(type) ((type) == MIC_TYPE_MUX_DCC || \
4279  			   (type) == MIC_TYPE_MUX_DCC_ECM_DIFF || \
4280  			   (type) == MIC_TYPE_MUX_DCC_ECM_SINGLE)
4281  
4282  void mt6359_set_mtkaif_protocol(struct snd_soc_component *cmpnt,
4283  				int mtkaif_protocol);
4284  void mt6359_mtkaif_calibration_enable(struct snd_soc_component *cmpnt);
4285  void mt6359_mtkaif_calibration_disable(struct snd_soc_component *cmpnt);
4286  void mt6359_set_mtkaif_calibration_phase(struct snd_soc_component *cmpnt,
4287  					 int phase_1, int phase_2, int phase_3);
4288  
4289  #endif/* end _MT6359_H_ */
4290