Home
last modified time | relevance | path

Searched refs:GML_48KHZ (Results 1 – 4 of 4) sorted by relevance

/sound/pci/echoaudio/
Dgina24_dsp.c156 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
195 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
Dlayla24_dsp.c152 err = write_control_reg(chip, GML_CONVERTER_ENABLE | GML_48KHZ, in load_asic()
192 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
Dmona_dsp.c152 control_reg = GML_CONVERTER_ENABLE | GML_48KHZ; in load_asic()
258 clock = GML_48KHZ | GML_SPDIF_SAMPLE_RATE1; in set_sample_rate()
Dechoaudio_dsp.h480 #define GML_48KHZ 0x2 macro