Searched refs:mr (Results 1 – 5 of 5) sorted by relevance
204 u32 mr; in mchp_spdiftx_is_running() local206 regmap_read(dev->regmap, SPDIFTX_MR, &mr); in mchp_spdiftx_is_running()207 return !!(mr & SPDIFTX_MR_TXEN_ENABLE); in mchp_spdiftx_is_running()310 u32 mr; in mchp_spdiftx_trigger() local316 regmap_read(dev->regmap, SPDIFTX_MR, &mr); in mchp_spdiftx_trigger()317 running = !!(mr & SPDIFTX_MR_TXEN_ENABLE); in mchp_spdiftx_trigger()324 mr &= ~SPDIFTX_MR_TXEN_MASK; in mchp_spdiftx_trigger()325 mr |= SPDIFTX_MR_TXEN_ENABLE; in mchp_spdiftx_trigger()332 mr &= ~SPDIFTX_MR_TXEN_MASK; in mchp_spdiftx_trigger()333 mr |= SPDIFTX_MR_TXEN_DISABLE; in mchp_spdiftx_trigger()[all …]
328 unsigned int mr = 0, mr_mask; in atmel_i2s_hw_params() local340 mr |= ATMEL_I2SC_MR_FORMAT_I2S; in atmel_i2s_hw_params()351 mr |= ATMEL_I2SC_MR_MODE_MASTER; in atmel_i2s_hw_params()359 mr |= ATMEL_I2SC_MR_MODE_SLAVE; in atmel_i2s_hw_params()371 mr |= ATMEL_I2SC_MR_TXMONO; in atmel_i2s_hw_params()373 mr |= ATMEL_I2SC_MR_RXMONO; in atmel_i2s_hw_params()384 mr |= ATMEL_I2SC_MR_DATALENGTH_8_BITS; in atmel_i2s_hw_params()388 mr |= ATMEL_I2SC_MR_DATALENGTH_16_BITS; in atmel_i2s_hw_params()392 mr |= ATMEL_I2SC_MR_DATALENGTH_18_BITS | ATMEL_I2SC_MR_IWS; in atmel_i2s_hw_params()396 mr |= ATMEL_I2SC_MR_DATALENGTH_20_BITS | ATMEL_I2SC_MR_IWS; in atmel_i2s_hw_params()[all …]
365 u32 mr = 0; in mchp_spdifrx_hw_params() local388 mr |= SPDIFRX_MR_ENDIAN_BIG; in mchp_spdifrx_hw_params()394 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params)); in mchp_spdifrx_hw_params()431 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr); in mchp_spdifrx_hw_params()
371 u32 mr; in fsl_dma_open() local453 mr = in_be32(&dma_channel->mr) & in fsl_dma_open()471 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN | in fsl_dma_open()476 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ? in fsl_dma_open()479 out_be32(&dma_channel->mr, mr); in fsl_dma_open()538 u32 mr; /* DMA Mode Register */ in fsl_dma_hw_params() local553 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK | in fsl_dma_hw_params()563 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1; in fsl_dma_hw_params()567 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2; in fsl_dma_hw_params()571 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4; in fsl_dma_hw_params()[all …]
12 __be32 mr; /* Mode register */ member