/sound/soc/intel/skylake/ |
D | skl-sst-cldma.h | 14 #define BDL_ALIGN(x) (x >> DMA_ADDRESS_128_BITS_ALIGNMENT) argument 51 #define CL_SD_CTL_SRST(x) \ argument 52 ((x << CL_SD_CTL_SRST_SHIFT) & CL_SD_CTL_SRST_MASK) 57 #define CL_SD_CTL_RUN(x) \ argument 58 ((x << CL_SD_CTL_RUN_SHIFT) & CL_SD_CTL_RUN_MASK) 63 #define CL_SD_CTL_IOCE(x) \ argument 64 ((x << CL_SD_CTL_IOCE_SHIFT) & CL_SD_CTL_IOCE_MASK) 69 #define CL_SD_CTL_FEIE(x) \ argument 70 ((x << CL_SD_CTL_FEIE_SHIFT) & CL_SD_CTL_FEIE_MASK) 75 #define CL_SD_CTL_DEIE(x) \ argument [all …]
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D | skl-sst-ipc.c | 22 #define IPC_GLB_TYPE(x) ((x) << IPC_GLB_TYPE_SHIFT) argument 27 #define IPC_GLB_REPLY_STATUS(x) ((x) << IPC_GLB_REPLY_STATUS_SHIFT) argument 31 #define IPC_GLB_REPLY_TYPE(x) (((x) >> IPC_GLB_REPLY_TYPE_SHIFT) \ argument 40 #define IPC_MSG_TARGET(x) (((x) & IPC_MSG_TARGET_MASK) \ argument 45 #define IPC_MSG_DIR(x) (((x) & IPC_MSG_DIR_MASK) \ argument 50 #define IPC_GLB_NOTIFY_TYPE(x) (((x) >> IPC_GLB_NOTIFY_TYPE_SHIFT) \ argument 55 #define IPC_GLB_NOTIFY_MSG_TYPE(x) (((x) >> IPC_GLB_NOTIFY_MSG_TYPE_SHIFT) \ argument 60 #define IPC_GLB_NOTIFY_RSP_TYPE(x) (((x) >> IPC_GLB_NOTIFY_RSP_SHIFT) \ argument 68 #define IPC_PPL_MEM_SIZE(x) (((x) & IPC_PPL_MEM_SIZE_MASK) \ argument 73 #define IPC_PPL_TYPE(x) (((x) & IPC_PPL_TYPE_MASK) \ argument [all …]
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/sound/usb/ |
D | mixer_us16x08.h | 18 #define SND_US16X08_KCBIAS(x) (((x)->private_value >> 24) & 0xff) argument 19 #define SND_US16X08_KCSTEP(x) (((x)->private_value >> 16) & 0xff) argument 20 #define SND_US16X08_KCMIN(x) (((x)->private_value >> 8) & 0xff) argument 21 #define SND_US16X08_KCMAX(x) (((x)->private_value >> 0) & 0xff) argument 34 #define MUA0(x, y) ((x)[(y) * 10 + 4]) argument 35 #define MUA1(x, y) ((x)[(y) * 10 + 5]) argument 36 #define MUA2(x, y) ((x)[(y) * 10 + 6]) argument 37 #define MUB0(x, y) ((x)[(y) * 10 + 7]) argument 38 #define MUB1(x, y) ((x)[(y) * 10 + 8]) argument 39 #define MUB2(x, y) ((x)[(y) * 10 + 9]) argument [all …]
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/sound/soc/fsl/ |
D | imx-ssi.h | 102 #define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) argument 103 #define SSI_SRCCR_DC(x) (((x) & 0x1f) << 8) argument 104 #define SSI_SRCCR_PM(x) (((x) & 0xff) << 0) argument 112 #define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) argument 113 #define SSI_STCCR_DC(x) (((x) & 0x1f) << 8) argument 114 #define SSI_STCCR_PM(x) (((x) & 0xff) << 0) argument 120 #define SSI_SFCSR_RFCNT1(x) (((x) & 0xf) << 28) argument 122 #define SSI_SFCSR_TFCNT1(x) (((x) & 0xf) << 24) argument 124 #define SSI_SFCSR_RFWM1(x) (((x) & 0xf) << 20) argument 125 #define SSI_SFCSR_TFWM1(x) (((x) & 0xf) << 16) argument [all …]
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D | fsl_ssi.h | 186 #define SSI_SxCCR_WL(x) \ argument 187 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK) 190 #define SSI_SxCCR_DC(x) \ argument 191 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK) 194 #define SSI_SxCCR_PM(x) \ argument 195 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK) 205 #define SSI_SFCSR_RFCNT1(x) \ argument 206 (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT) 209 #define SSI_SFCSR_TFCNT1(x) \ argument 210 (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT) [all …]
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/sound/pci/au88x0/ |
D | au8830.h | 105 #define ADB_DMA(x) (x) argument 106 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument 107 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument 108 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument 109 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument 110 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument 111 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument 112 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) argument 113 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument 114 #define ADB_SPDIFIN(x) (x + OFFSET_SPDIFIN) argument [all …]
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D | au8810.h | 84 #define ADB_DMA(x) (x) argument 85 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument 86 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument 87 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument 88 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument 89 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument 90 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument 91 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) argument 92 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument 93 #define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT) argument [all …]
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D | au8820.h | 76 #define ADB_DMA(x) (x + OFFSET_ADBDMA) argument 77 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT) argument 78 #define ADB_SRCIN(x) (x + OFFSET_SRCIN) argument 79 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT) argument 80 #define ADB_MIXIN(x) (x + OFFSET_MIXIN) argument 81 #define ADB_CODECIN(x) (x + OFFSET_CODECIN) argument 82 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT) argument 83 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT) argument 84 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */ argument 85 #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */ argument [all …]
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D | au88x0_wt.h | 18 #define WT_BAR(x) (((x)&0xffe0)<<0x8) argument 19 #define WT_BANK(x) (x>>5) argument 34 #define WT_PARM(x,y) (((WT_BAR(x))+ 0x80 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0200 */ argument 35 #define WT_DELAY(x,y) (((WT_BAR(x))+ 0x100 +(((x)&0x1f)<<2)+(y))<<2) /* 0x0400 */ argument
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D | au88x0.h | 26 #define hwread(x,y) readl((x)+(y)) argument 27 #define hwwrite(x,y,z) writel((z),(x)+(y)) argument 37 #define SRC_RATIO(x,y) ((((x<<15)/y) + 1)/2) argument 74 #define VORTEX_IS_QUAD(x) ((x)->isquad) argument 76 #define IS_BAD_CHIP(x) (\ argument 77 (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_VORTEX_2) || \ 78 (x->rev == 0xfe && x->device == PCI_DEVICE_ID_AUREAL_ADVANTAGE)) 89 #define MIX_CAPT(x) (vortex->mixcapt[x]) argument 90 #define MIX_PLAYB(x) (vortex->mixplayb[x]) argument 91 #define MIX_SPDIF(x) (vortex->mixspdif[x]) argument
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/sound/soc/codecs/ |
D | tlv320dac33.h | 103 #define DAC33_ADJSTEP(x) (x << 0) argument 104 #define DAC33_ADJTHRSHLD(x) (x << 4) argument 107 #define DAC33_REFDIV(x) (x << 4) argument 136 #define DAC33_DATA_DELAY(x) (x << 2) argument 149 #define DAC33_THRREG(x) (((x) & 0x1FFF) << 3) argument 167 #define DAC33_UTM(x) (x << 0) argument 168 #define DAC33_UFM(x) (x << 2) argument 169 #define DAC33_OFM(x) (x << 4) argument 172 #define DAC33_NSM(x) (x << 0) argument 173 #define DAC33_PSM(x) (x << 2) argument [all …]
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D | cs42l51.h | 39 #define CS42L51_MIC_POWER_CTL_SPEED(x) (((x)&3)<<5) argument 53 #define CS42L51_INTF_CTL_DAC_FORMAT(x) (((x)&7)<<3) argument 69 #define CS42L51_MIC_CTL_MICBIAS_LVL(x) (((x)&3)<<2) argument 84 #define CS42L51_ADC_INPUT_AINB_MUX(x) (((x)&3)<<6) argument 85 #define CS42L51_ADC_INPUT_AINA_MUX(x) (((x)&3)<<4) argument 92 #define CS42L51_DAC_OUT_CTL_HP_GAIN(x) (((x)&7)<<5) argument 100 #define CS42L51_DAC_CTL_DATA_SEL(x) (((x)&3)<<6) argument 104 #define CS42L51_DAC_CTL_DACSZ(x) (((x)&3)<<0) argument 110 #define CS42L51_ALC_PGX_PGX_VOL(x) (((x)&0x1f)<<0) argument 120 #define CS42L51_MIX_VOLUME(x) (((x)&0x7f)<<0) argument [all …]
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D | ad73311.h | 32 #define REGA_DEVC(x) ((x & 0x7) << 4) argument 38 #define REGB_DIRATE(x) (x & 0x3) argument 39 #define REGB_SCDIV(x) ((x & 0x3) << 2) argument 40 #define REGB_MCDIV(x) ((x & 0x7) << 4) argument 55 #define REGD_IGS(x) (x & 0x7) argument 57 #define REGD_OGS(x) ((x & 0x7) << 4) argument 63 #define REGE_DA(x) (x & 0x1f) argument
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/sound/soc/au1x/ |
D | psc.h | 26 #define PSC_CTRL(x) ((x)->mmio + PSC_CTRL_OFFSET) argument 27 #define PSC_SEL(x) ((x)->mmio + PSC_SEL_OFFSET) argument 28 #define I2S_STAT(x) ((x)->mmio + PSC_I2SSTAT_OFFSET) argument 29 #define I2S_CFG(x) ((x)->mmio + PSC_I2SCFG_OFFSET) argument 30 #define I2S_PCR(x) ((x)->mmio + PSC_I2SPCR_OFFSET) argument 31 #define AC97_CFG(x) ((x)->mmio + PSC_AC97CFG_OFFSET) argument 32 #define AC97_CDC(x) ((x)->mmio + PSC_AC97CDC_OFFSET) argument 33 #define AC97_EVNT(x) ((x)->mmio + PSC_AC97EVNT_OFFSET) argument 34 #define AC97_PCR(x) ((x)->mmio + PSC_AC97PCR_OFFSET) argument 35 #define AC97_RST(x) ((x)->mmio + PSC_AC97RST_OFFSET) argument [all …]
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/sound/soc/rockchip/ |
D | rockchip_i2s_tdm.h | 17 #define I2S_TXCR_PATH_SHIFT(x) (23 + (x) * 2) argument 18 #define I2S_TXCR_PATH_MASK(x) (0x3 << I2S_TXCR_PATH_SHIFT(x)) argument 19 #define I2S_TXCR_PATH(x, v) ((v) << I2S_TXCR_PATH_SHIFT(x)) argument 23 #define I2S_TXCR_CSR(x) ((x) << I2S_TXCR_CSR_SHIFT) argument 38 #define I2S_TXCR_PBM_MODE(x) ((x) << I2S_TXCR_PBM_SHIFT) argument 47 #define I2S_TXCR_VDW(x) (((x) - 1) << I2S_TXCR_VDW_SHIFT) argument 54 #define I2S_RXCR_PATH_SHIFT(x) (17 + (x) * 2) argument 55 #define I2S_RXCR_PATH_MASK(x) (0x3 << I2S_RXCR_PATH_SHIFT(x)) argument 56 #define I2S_RXCR_PATH(x, v) ((v) << I2S_RXCR_PATH_SHIFT(x)) argument 58 #define I2S_RXCR_CSR(x) ((x) << I2S_RXCR_CSR_SHIFT) argument [all …]
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D | rockchip_i2s.h | 21 #define I2S_TXCR_CSR(x) (x << I2S_TXCR_CSR_SHIFT) argument 36 #define I2S_TXCR_PBM_MODE(x) (x << I2S_TXCR_PBM_SHIFT) argument 43 #define I2S_TXCR_VDW(x) ((x - 1) << I2S_TXCR_VDW_SHIFT) argument 51 #define I2S_RXCR_CSR(x) (x << I2S_RXCR_CSR_SHIFT) argument 66 #define I2S_RXCR_PBM_MODE(x) (x << I2S_RXCR_PBM_SHIFT) argument 73 #define I2S_RXCR_VDW(x) ((x - 1) << I2S_RXCR_VDW_SHIFT) argument 81 #define I2S_CKR_TRCM(x) (x << I2S_CKR_TRCM_SHIFT) argument 103 #define I2S_CKR_MDIV(x) ((x - 1) << I2S_CKR_MDIV_SHIFT) argument 106 #define I2S_CKR_RSD(x) ((x - 1) << I2S_CKR_RSD_SHIFT) argument 109 #define I2S_CKR_TSD(x) ((x - 1) << I2S_CKR_TSD_SHIFT) argument [all …]
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/sound/pci/ice1712/ |
D | hoontech.h | 30 #define ICE1712_STDSP24_0_BOX(r, x) r[0] = ((r[0] & ~3) | ((x)&3)) argument 31 #define ICE1712_STDSP24_0_DAREAR(r, x) r[0] = ((r[0] & ~4) | (((x)&1)<<2)) argument 32 #define ICE1712_STDSP24_1_CHN1(r, x) r[1] = ((r[1] & ~1) | ((x)&1)) argument 33 #define ICE1712_STDSP24_1_CHN2(r, x) r[1] = ((r[1] & ~2) | (((x)&1)<<1)) argument 34 #define ICE1712_STDSP24_1_CHN3(r, x) r[1] = ((r[1] & ~4) | (((x)&1)<<2)) argument 35 #define ICE1712_STDSP24_2_CHN4(r, x) r[2] = ((r[2] & ~1) | ((x)&1)) argument 36 #define ICE1712_STDSP24_2_MIDIIN(r, x) r[2] = ((r[2] & ~2) | (((x)&1)<<1)) argument 37 #define ICE1712_STDSP24_2_MIDI1(r, x) r[2] = ((r[2] & ~4) | (((x)&1)<<2)) argument 38 #define ICE1712_STDSP24_3_MIDI2(r, x) r[3] = ((r[3] & ~1) | ((x)&1)) argument 39 #define ICE1712_STDSP24_3_MUTE(r, x) r[3] = ((r[3] & ~2) | (((x)&1)<<1)) argument [all …]
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/sound/soc/dwc/ |
D | local.h | 35 #define LRBR_LTHR(x) (0x40 * x + 0x020) argument 36 #define RRBR_RTHR(x) (0x40 * x + 0x024) argument 37 #define RER(x) (0x40 * x + 0x028) argument 38 #define TER(x) (0x40 * x + 0x02C) argument 39 #define RCR(x) (0x40 * x + 0x030) argument 40 #define TCR(x) (0x40 * x + 0x034) argument 41 #define ISR(x) (0x40 * x + 0x038) argument 42 #define IMR(x) (0x40 * x + 0x03C) argument 43 #define ROR(x) (0x40 * x + 0x040) argument 44 #define TOR(x) (0x40 * x + 0x044) argument [all …]
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/sound/soc/intel/keembay/ |
D | kmb_platform.h | 34 #define LRBR_LTHR(x) (0x40 * (x) + 0x020) argument 35 #define RRBR_RTHR(x) (0x40 * (x) + 0x024) argument 36 #define RER(x) (0x40 * (x) + 0x028) argument 37 #define TER(x) (0x40 * (x) + 0x02C) argument 38 #define RCR(x) (0x40 * (x) + 0x030) argument 39 #define TCR(x) (0x40 * (x) + 0x034) argument 40 #define ISR(x) (0x40 * (x) + 0x038) argument 41 #define IMR(x) (0x40 * (x) + 0x03C) argument 42 #define ROR(x) (0x40 * (x) + 0x040) argument 43 #define TOR(x) (0x40 * (x) + 0x044) argument [all …]
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/sound/soc/pxa/ |
D | mmp-sspa.h | 28 #define SSPA_CTL_XFRLEN2(x) ((x) << 24) /* Transmit Frame Length in Phase 2 */ argument 30 #define SSPA_CTL_XWDLEN2(x) ((x) << 21) /* Transmit Word Length in Phase 2 */ argument 31 #define SSPA_CTL_XDATDLY(x) ((x) << 19) /* Transmit Data Delay */ argument 33 #define SSPA_CTL_XSSZ2(x) ((x) << 16) /* Transmit Sample Audio Size */ argument 35 #define SSPA_CTL_XFRLEN1(x) ((x) << 8) /* Transmit Frame Length in Phase 1 */ argument 37 #define SSPA_CTL_XWDLEN1(x) ((x) << 5) /* Transmit Word Length in Phase 1 */ argument 39 #define SSPA_CTL_XSSZ1(x) ((x) << 0) /* XSSZ1 */ argument 57 #define SSPA_SP_FWID(x) ((x) << 20) /* Frame-Sync Width */ argument 59 #define SSPA_TXSP_FPER(x) ((x) << 4) /* Frame-Sync Active */ argument
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/sound/soc/stm/ |
D | stm32_sai.h | 54 #define SAI_XCR1_PRTCFG_SET(x) ((x) << SAI_XCR1_PRTCFG_SHIFT) argument 58 #define SAI_XCR1_DS_SET(x) ((x) << SAI_XCR1_DS_SHIFT) argument 67 #define SAI_XCR1_SYNCEN_SET(x) ((x) << SAI_XCR1_SYNCEN_SHIFT) argument 81 #define SAI_XCR1_MCKDIV_WIDTH(x) (((x) == STM_SAI_STM32F4) ? 4 : 6) argument 82 #define SAI_XCR1_MCKDIV_MASK(x) GENMASK((SAI_XCR1_MCKDIV_SHIFT + (x) - 1),\ argument 84 #define SAI_XCR1_MCKDIV_SET(x) ((x) << SAI_XCR1_MCKDIV_SHIFT) argument 85 #define SAI_XCR1_MCKDIV_MAX(x) ((1 << SAI_XCR1_MCKDIV_WIDTH(x)) - 1) argument 96 #define SAI_XCR2_FTH_SET(x) ((x) << SAI_XCR2_FTH_SHIFT) argument 109 #define SAI_XCR2_MUTECNT_SET(x) ((x) << SAI_XCR2_MUTECNT_SHIFT) argument 116 #define SAI_XCR2_COMP_SET(x) ((x) << SAI_XCR2_COMP_SHIFT) argument [all …]
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/sound/soc/mediatek/mt8195/ |
D | mt8195-reg.h | 2518 #define PWR2_TOP_CON_DMIC8_SRC_SEL_VAL(x) ((x) << 29) argument 2519 #define PWR2_TOP_CON_DMIC7_SRC_SEL_VAL(x) ((x) << 26) argument 2520 #define PWR2_TOP_CON_DMIC6_SRC_SEL_VAL(x) ((x) << 23) argument 2521 #define PWR2_TOP_CON_DMIC5_SRC_SEL_VAL(x) ((x) << 20) argument 2522 #define PWR2_TOP_CON_DMIC4_SRC_SEL_VAL(x) ((x) << 17) argument 2523 #define PWR2_TOP_CON_DMIC3_SRC_SEL_VAL(x) ((x) << 14) argument 2524 #define PWR2_TOP_CON_DMIC2_SRC_SEL_VAL(x) ((x) << 11) argument 2525 #define PWR2_TOP_CON_DMIC1_SRC_SEL_VAL(x) ((x) << 8) argument 2543 #define PCM_INTF_CON1_SYNC_LENGTH(x) (((x) & 0x1f) << 9) argument 2548 #define PCM_INTF_CON1_PCM_MODE(x) (((x) & 0x3) << 3) argument [all …]
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/sound/soc/sof/intel/ |
D | hda-loader-skl.c | 33 #define HDA_CL_SD_CTL_SRST(x) (((x) & 0x1) << \ argument 38 #define HDA_CL_SD_CTL_RUN(x) (((x) & 0x1) << \ argument 43 #define HDA_CL_SD_CTL_IOCE(x) (((x) & 0x1) << \ argument 48 #define HDA_CL_SD_CTL_FEIE(x) (((x) & 0x1) << \ argument 53 #define HDA_CL_SD_CTL_DEIE(x) (((x) & 0x1) << \ argument 58 #define HDA_CL_SD_CTL_FIFOLC(x) (((x) & 0x1) << \ argument 63 #define HDA_CL_SD_CTL_STRIPE(x) (((x) & 0x3) << \ argument 68 #define HDA_CL_SD_CTL_TP(x) (((x) & 0x1) << \ argument 73 #define HDA_CL_SD_CTL_DIR(x) (((x) & 0x1) << \ argument 78 #define HDA_CL_SD_CTL_STRM(x) (((x) & 0xf) << \ argument [all …]
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/sound/soc/samsung/ |
D | regs-i2s-v2.h | 100 #define S3C64XX_IISFIC_TX2COUNT(x) (((x) >> 24) & 0xf) argument 101 #define S3C64XX_IISFIC_TX1COUNT(x) (((x) >> 16) & 0xf) argument 105 #define S3C2412_IISFIC_TXCOUNT(x) (((x) >> 8) & 0xf) argument 106 #define S3C2412_IISFIC_RXCOUNT(x) (((x) >> 0) & 0xf) argument 109 #define S5PC1XX_IISFICS_TXCOUNT(x) (((x) >> 8) & 0x7f) argument
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/sound/soc/sof/ |
D | ipc4-topology.h | 15 #define SOF_IPC4_FW_PAGE(x) ((((x) + BIT(12) - 1) & ~(BIT(12) - 1)) >> 12) argument 16 #define SOF_IPC4_FW_ROUNDUP(x) (((x) + BIT(6) - 1) & (~(BIT(6) - 1))) argument 42 #define SOF_IPC4_NODE_INDEX(x) ((x) & SOF_IPC4_NODE_INDEX_MASK) argument 43 #define SOF_IPC4_NODE_TYPE(x) ((x) << 8) argument 46 #define SOF_IPC4_NODE_INDEX_INTEL_SSP(x) (((x) & 0xf) << 4) argument 49 #define SOF_IPC4_NODE_INDEX_INTEL_DMIC(x) ((x) & 0x7) argument
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