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Searched refs:NumDispClkLevelsEnabled (Results 1 – 13 of 13) sorted by relevance

/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c588 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn31_clk_mgr_helper_populate_bw_params()
589 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn31_clk_mgr_helper_populate_bw_params()
590 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
591 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn31_clk_mgr_helper_populate_bw_params()
763 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn31_clk_mgr_construct()
774 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn31_clk_mgr_construct()
Ddcn31_smu.h141 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c593 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn314_clk_mgr_helper_populate_bw_params()
594 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn314_clk_mgr_helper_populate_bw_params()
595 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
596 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn314_clk_mgr_helper_populate_bw_params()
809 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn314_clk_mgr_construct()
820 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn314_clk_mgr_construct()
Ddcn314_smu.h60 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c520 if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS && in dcn316_clk_mgr_helper_populate_bw_params()
521 clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) { in dcn316_clk_mgr_helper_populate_bw_params()
522 max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
523 max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled); in dcn316_clk_mgr_helper_populate_bw_params()
Ddcn316_smu.h87 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
Dsmu13_driver_if_v13_0_5.h121 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
Dsmu13_driver_if_yellow_carp.h132 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
Dsmu11_driver_if_vangogh.h145 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member
Dsmu13_driver_if_v13_0_4.h133 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_smu.h79 uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk member
Ddcn315_clk_mgr.c691 smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled, in dcn315_clk_mgr_construct()
702 for (i = 0; i < smu_dpm_clks.dpm_clks->NumDispClkLevelsEnabled; i++) { in dcn315_clk_mgr_construct()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Ddcn301_smu.h116 uint8_t NumDispClkLevelsEnabled; //applies to both dispclk and dppclk member