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Searched refs:SDMA0 (Results 1 – 14 of 14) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Dsdma_v4_4.c60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
96 { "SDMA_MBANK_DATA_BUF9_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
[all …]
Dsdma_v4_0.c90 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
91 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
92 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
93 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
94 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
95 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000),
97 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_IB_CNTL, 0x800f0100, 0x00000100),
98 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC0_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
[all …]
Damdgpu_amdkfd_gfx_v10_3.c141 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
145 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
149 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
153 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
Damdgpu_amdkfd_arcturus.c79 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
Damdgpu_amdkfd_gfx_v10.c162 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
Damdgpu_amdkfd_gfx_v11.c132 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
Damdgpu_amdkfd_gfx_v9.c192 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
Dsoc21.c239 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
Dnv.c342 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
Dsdma_v2_4.c285 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v2_4_ring_emit_hdp_flush()
Dsoc15.c385 { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
Dsdma_v3_0.c459 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush()
/drivers/gpu/drm/radeon/
Dcik_sdma.c177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
Dcikd.h860 #define SDMA0 (1 << 10) macro