Searched refs:TRCSSCCRn (Results 1 – 3 of 3) sorted by relevance
| /drivers/hwtracing/coresight/ |
| D | coresight-etm4x.h | 81 #define TRCSSCCRn(n) (0x280 + (n * 4)) macro
368 CASE_##op((val), TRCSSCCRn(0)) \
369 CASE_##op((val), TRCSSCCRn(1)) \
370 CASE_##op((val), TRCSSCCRn(2)) \
371 CASE_##op((val), TRCSSCCRn(3)) \
372 CASE_##op((val), TRCSSCCRn(4)) \
373 CASE_##op((val), TRCSSCCRn(5)) \
374 CASE_##op((val), TRCSSCCRn(6)) \
375 CASE_##op((val), TRCSSCCRn(7)) \
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| D | coresight-etm4x-cfg.c | 83 } else if ((offset >= TRCSSCCRn(0)) && (offset <= TRCSSPCICRn(7))) { in etm4_cfg_map_reg_offset()
88 CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); in etm4_cfg_map_reg_offset()
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| D | coresight-etm4x-core.c | 449 etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); in etm4_enable_hw()
1648 state->trcssccr[i] = etm4x_read32(csa, TRCSSCCRn(i)); in __etm4_cpu_save()
1779 etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); in __etm4_cpu_restore()
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