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Searched refs:UVD_CGC_GATE__MPC_MASK (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c650 UVD_CGC_GATE__MPC_MASK |
683 UVD_CGC_GATE__MPC_MASK |
1307 UVD_CGC_GATE__MPC_MASK | in uvd_v6_0_enable_clock_gating()
1395 UVD_CGC_GATE__MPC_MASK |
Duvd_v5_0.c650 UVD_CGC_GATE__MPC_MASK | in uvd_v5_0_enable_clock_gating()
737 UVD_CGC_GATE__MPC_MASK |
Duvd_v7_0.c1679 UVD_CGC_GATE__MPC_MASK |
Dvcn_v4_0.c662 | UVD_CGC_GATE__MPC_MASK in vcn_v4_0_disable_clock_gating()
Dvcn_v2_0.c514 | UVD_CGC_GATE__MPC_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v1_0.c489 | UVD_CGC_GATE__MPC_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c581 | UVD_CGC_GATE__MPC_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v3_0.c719 | UVD_CGC_GATE__MPC_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h406 #define UVD_CGC_GATE__MPC_MASK macro
Duvd_4_2_sh_mask.h141 #define UVD_CGC_GATE__MPC_MASK 0x200 macro
Duvd_3_1_sh_mask.h141 #define UVD_CGC_GATE__MPC_MASK 0x200 macro
Duvd_4_0_sh_mask.h88 #define UVD_CGC_GATE__MPC_MASK 0x00000200L macro
Duvd_5_0_sh_mask.h153 #define UVD_CGC_GATE__MPC_MASK 0x200 macro
Duvd_6_0_sh_mask.h155 #define UVD_CGC_GATE__MPC_MASK 0x200 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h834 #define UVD_CGC_GATE__MPC_MASK macro
Dvcn_2_5_sh_mask.h1904 #define UVD_CGC_GATE__MPC_MASK macro
Dvcn_2_0_0_sh_mask.h1853 #define UVD_CGC_GATE__MPC_MASK macro
Dvcn_2_6_0_sh_mask.h3575 #define UVD_CGC_GATE__MPC_MASK macro
Dvcn_3_0_0_sh_mask.h2634 #define UVD_CGC_GATE__MPC_MASK macro
Dvcn_4_0_0_sh_mask.h69 #define UVD_CGC_GATE__MPC_MASK macro