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Searched refs:UVD_CGC_GATE__UDEC_IT_MASK (Results 1 – 20 of 20) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v6_0.c655 UVD_CGC_GATE__UDEC_IT_MASK |
688 UVD_CGC_GATE__UDEC_IT_MASK |
1312 UVD_CGC_GATE__UDEC_IT_MASK | in uvd_v6_0_enable_clock_gating()
1400 UVD_CGC_GATE__UDEC_IT_MASK |
Duvd_v5_0.c655 UVD_CGC_GATE__UDEC_IT_MASK | in uvd_v5_0_enable_clock_gating()
742 UVD_CGC_GATE__UDEC_IT_MASK |
Duvd_v7_0.c1684 UVD_CGC_GATE__UDEC_IT_MASK |
Dvcn_v4_0.c667 | UVD_CGC_GATE__UDEC_IT_MASK in vcn_v4_0_disable_clock_gating()
Dvcn_v2_0.c519 | UVD_CGC_GATE__UDEC_IT_MASK in vcn_v2_0_disable_clock_gating()
Dvcn_v1_0.c494 | UVD_CGC_GATE__UDEC_IT_MASK in vcn_v1_0_disable_clock_gating()
Dvcn_v2_5.c586 | UVD_CGC_GATE__UDEC_IT_MASK in vcn_v2_5_disable_clock_gating()
Dvcn_v3_0.c724 | UVD_CGC_GATE__UDEC_IT_MASK in vcn_v3_0_disable_clock_gating()
/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h411 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Duvd_4_2_sh_mask.h151 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 macro
Duvd_3_1_sh_mask.h151 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 macro
Duvd_4_0_sh_mask.h106 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L macro
Duvd_5_0_sh_mask.h163 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 macro
Duvd_6_0_sh_mask.h165 #define UVD_CGC_GATE__UDEC_IT_MASK 0x4000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h839 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Dvcn_2_5_sh_mask.h1909 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Dvcn_2_0_0_sh_mask.h1858 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Dvcn_2_6_0_sh_mask.h3580 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Dvcn_3_0_0_sh_mask.h2639 #define UVD_CGC_GATE__UDEC_IT_MASK … macro
Dvcn_4_0_0_sh_mask.h74 #define UVD_CGC_GATE__UDEC_IT_MASK … macro