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Searched refs:UVD_MPC_SET_MUXA1__VARA_7_MASK (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h614 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Duvd_4_2_sh_mask.h495 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
Duvd_3_1_sh_mask.h491 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
Duvd_4_0_sh_mask.h510 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003f000L macro
Duvd_5_0_sh_mask.h527 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
Duvd_6_0_sh_mask.h529 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x3f000 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1121 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Dvcn_2_5_sh_mask.h2862 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Dvcn_2_0_0_sh_mask.h2627 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Dvcn_2_6_0_sh_mask.h2854 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Dvcn_3_0_0_sh_mask.h3935 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro
Dvcn_4_0_0_sh_mask.h4185 #define UVD_MPC_SET_MUXA1__VARA_7_MASK … macro