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Searched refs:UVD_MPC_SET_MUXB1__VARB_7__SHIFT (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_7_0_sh_mask.h629 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Duvd_4_2_sh_mask.h512 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc macro
Duvd_3_1_sh_mask.h508 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc macro
Duvd_4_0_sh_mask.h527 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0x0000000c macro
Duvd_5_0_sh_mask.h544 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc macro
Duvd_6_0_sh_mask.h546 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h1136 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Dvcn_2_5_sh_mask.h2877 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Dvcn_2_0_0_sh_mask.h2642 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Dvcn_2_6_0_sh_mask.h2869 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Dvcn_3_0_0_sh_mask.h3950 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro
Dvcn_4_0_0_sh_mask.h4200 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT … macro