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Searched refs:UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT (Results 1 – 8 of 8) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_5_0_sh_mask.h776 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb macro
Duvd_6_0_sh_mask.h774 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_sh_mask.h491 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro
Dvcn_2_5_sh_mask.h2121 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro
Dvcn_2_0_0_sh_mask.h3247 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro
Dvcn_2_6_0_sh_mask.h3792 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro
Dvcn_3_0_0_sh_mask.h2863 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro
Dvcn_4_0_0_sh_mask.h3916 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT … macro